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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose re lating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ship s, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use re nesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of c ontrolled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any fo rm, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. r8c/26 group, r8c/27 group hardware manual 16 users manual rev.2.10 2008.09 renesas 16-bit single-chip mcu r8c family / r8c/2x series all information contained in these materials, including products and product specifcations, represents information on the product at the time of publication and is subject to change by renesas electronics corp. without notice. please review the latest information published by renesas electronics corp. through various means, including the renesas electronics corp. website (http://www.renesas.com). 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes regarding these materials general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products. how to use this manual 1. purpose and target readers this manual is designed to provide the user with an understanding of the hardwa re functions and electrical characteristics of the mcu. it is intended for users de signing application systems incorporating the mcu. a basic knowledge of electric circuits, logi cal circuits, and mcus is necessa ry in order to use this manual. the manual comprises an overview of the product; descriptions of the cpu, system control functions, peripheral functions, and electrical charac teristics; and usage notes. particular attention should be paid to the precautio nary notes when using the manual. these notes occur within the body of the text, at the end of each section, and in the usage notes section. the revision history summarizes the loca tions of revisions and additions. it does not list all revisions. refer to the text of the manual for details. the following documents apply to the r8c/26 group, r8c/27 group . make sure to refer to the latest versions of these documents. the newest versions of the documents listed may be obtained from the renesas technology web site. document type description document title document no. datasheet hardware overview and electr ical characteristics r8c/26, r8c/27 group datasheet rej03b0168 hardware manual hardware specifications (pin assignments, memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description note: refer to the applic ation notes for details on using peripheral functions. r8c/26 group, r8c/27 group hardware manual this hardware manual software manual description of cpu instruction set r8c/tiny series software manual rej09b0001 application note information on using peripheral functions and application examples sample programs information on writing programs in assembly language and c available from renesas technology web site. renesas technical update product specifications, updates on documents, etc. 2. notation of numbers and symbols the notation conventions for register na mes, bit names, numbers, and symbols used in this manual are described below. (1) register names, bit names, and pin names registers, bits, and pins are referred to in the text by symbols. the symbol is accompanied by the word ?register,? ?bit,? or ?pin? to distinguish the three categories. examples the pm03 bit in the pm0 register p3_5 pin, vcc pin (2) notation of numbers the indication ?b? is appended to numeric values given in binary format. however, nothing is appended to the values of single bits. the indication ?h? is appended to numeric values given in hexadecimal format. nothing is appended to numeric values given in decimal format. examples binary: 11b hexadecimal: efa0h decimal: 1234 3. register notation the symbols and terms used in register diagrams are described below. *1 blank: set to 0 or 1 acco rding to the application. 0: set to 0. 1: set to 1. x: nothing is assigned. *2 rw: read and write. ro: read only. wo: write only. ? : nothing is assigned. *3 ? reserved bit reserved bit. set to specified value. *4 ? nothing is assigned nothing is assigned to the bit. as the bit may be used for future functions, if necessary, set to 0. ? do not set to a value operation is not guaranteed when a value is set. ? function varies according to the operating mode. the function of the bit varies with the peripheral functi on mode. refer to the regist er diagram for information on the individual modes. xxx register symbol address after reset xxx xxx 00h bit name bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 xxx bits 1 0: xxx 0 1: xxx 1 0: do not set. 1 1: xxx b1 b0 xxx1 xxx0 xxx4 reserved bits xxx5 xxx7 xxx6 function nothing is assigned. if necessary, set to 0. when read, the content is undefined. xxx bit function varies according to the operating mode. set to 0. 0 (b3) (b2) rw rw rw rw wo rw ro xxx bits 0: xxx 1: xxx *1 *2 *3 *4 4. list of abbrevia tions and acronyms abbreviation full form acia asynchronous communication interface adapter bps bits per second crc cyclic redundancy check dma direct memory access dmac direct memory access controller gsm global system for mobile communications hi-z high impedance iebus inter equipment bus i/o input / output irda infrared data association lsb least significant bit msb most significant bit nc non-connect pll phase locked loop pwm pulse width modulation sim subscriber identity module uart universal asynchronous receiver / transmitter vco voltage controlled oscillator all trademarks and registered trademarks are the property of thei r respective owners. a - 1 sfr page reference ............................................................................................................ ............... b - 1 1. overview .................................................................................................................... ..................... 1 1.1 applications ............................................................................................................... ................................ 1 1.2 performance overview ....................................................................................................... ....................... 2 1.3 block diagram .............................................................................................................. ............................ 4 1.4 product information .................................... .................................................................... .......................... 5 1.5 pin assignments ............................................................................................................ ............................ 9 1.6 pin functions .............................................................................................................. ............................. 10 2. central processing unit (cpu) ............................................................................................... ...... 12 2.1 data registers (r0, r1, r2, and r3) ........................................................................................ .............. 13 2.2 address registers (a0 and a1) .............................................................................................. ................. 13 2.3 frame base register (fb) ................................................................................................... .................... 13 2.4 interrupt table register (intb) ..................... ....................................................................... .................. 13 2.5 program counter (pc) ....................................................................................................... ...................... 13 2.6 user stack pointer (usp) and interrupt stack pointer (isp) ................................................................. . 13 2.7 static base register (sb) .................................................................................................. ...................... 13 2.8 flag register (flg) ........................................................................................................ ........................ 13 2.8.1 carry flag (c) ........................................................................................................... .......................... 13 2.8.2 debug flag (d) ........................................................................................................... ........................ 13 2.8.3 zero flag (z) ............................................................................................................ ........................... 13 2.8.4 sign flag (s) ............................................................................................................ ........................... 13 2.8.5 register bank select flag (b) ............................................................................................ ................ 13 2.8.6 overflow flag (o) ........................................................................................................ ...................... 13 2.8.7 interrupt enable flag (i) ................................................................................................ ..................... 14 2.8.8 stack pointer select flag (u) ............................................................................................ .................. 14 2.8.9 processor interrupt priority le vel (ipl) ................................................................................. ............ 14 2.8.10 reserved bit ............................................................................................................ ............................ 14 3. memory ...................................................................................................................... ................... 15 3.1 r8c/26 group .............. .............. .............. .............. .............. .............. .............. ............. .......................... 15 3.2 r8c/27 group .............. .............. .............. .............. .............. .............. .............. ............. .......................... 16 4. special function registers (sfrs) ........................................................................................... .... 17 5. resets ...................................................................................................................... ..................... 24 5.1 hardware reset ............................................................................................................. .......................... 28 5.1.1 when power supply is stable .............................................................................................. ............... 28 5.1.2 power on ................................................................................................................. ........................... 28 5.2 power-on reset function .................................................................................................... ................... 30 5.3 voltage monitor 0 reset (n, d version) ..................................................................................... ........... 32 5.4 voltage monitor 1 reset (n, d version) ..................................................................................... ........... 32 5.5 voltage monitor 1 reset (j, k version) ..................................................................................... ............. 32 5.6 voltage monitor 2 reset .................................................................................................... ..................... 33 5.7 watchdog timer reset .... .............. .............. .............. .............. ........... ............ ........... ......... ..................... 33 5.8 software reset ............................................................................................................. ............................ 33 table of contents a - 2 6. voltage detection circuit ................................................................................................... ........... 34 6.1 vcc input voltage .......................................................................................................... ........................ 45 6.1.1 monitoring vdet0 ......................................................................................................... ...................... 45 6.1.2 monitoring vdet1 ......................................................................................................... ...................... 45 6.1.3 monitoring vdet2 ......................................................................................................... ...................... 45 6.2 voltage monitor 0 reset (for n, d version only) ............................................................................ ..... 46 6.3 voltage monitor 1 interrupt and voltage monitor 1 re set (n, d version) ............................................ 47 6.4 voltage monitor 1 reset (j, k version) ..................................................................................... ............. 49 6.5 voltage monitor 2 interrupt and voltage monitor 2 re set .................................................................... . 50 7. programmable i/o ports ...................................................................................................... ......... 52 7.1 functions of programmable i/o ports ........................................................................................ ............. 52 7.2 effect on peripheral functions ............................................................................................. ................... 53 7.3 pins other than programmable i/ o ports ..................................................................................... ........... 53 7.4 port setting ............................................................................................................... ............................... 65 7.5 unassigned pin handling .................................................................................................... .................... 76 8. processor mode .............................................................................................................. .............. 77 8.1 processor modes ............................................................................................................ .......................... 77 9. bus ......................................................................................................................... ....................... 78 10. clock generation circuit ................................................................................................... ............ 79 10.1 xin clock ................................................................................................................. .............................. 89 10.2 on-chip oscillator clocks ...... .............. .............. .............. ............... .............. ........... ......... ..................... 90 10.2.1 low-speed on-chip os cillator clock ...................................................................................... .......... 90 10.2.2 high-speed on-chip oscillator clock ..................................................................................... .......... 90 10.3 xcin clock (for n, d version on ly) ........................................................................................ ............ 91 10.4 cpu clock and peripheral function clock ................................................................................... .......... 92 10.4.1 system clock ............................................................................................................ .......................... 92 10.4.2 cpu clock ............................................................................................................... ........................... 92 10.4.3 peripheral function clock (f1, f2, f4, f8, and f3 2) ..................................................................... ........ 92 10.4.4 foco .................................................................................................................... ............................... 92 10.4.5 foco40m ................................................................................................................. .......................... 92 10.4.6 foco-f .................................................................................................................. ............................. 92 10.4.7 foco-s .................................................................................................................. ............................. 92 10.4.8 fc4 and fc32 ............................................................................................................ ........................... 93 10.4.9 foco128 ................................................................................................................. ............................ 93 10.5 power control ............................................................................................................. ............................. 94 10.5.1 standard operating mode ................................................................................................. .................. 94 10.5.2 wait mode ............................................................................................................... ........................... 96 10.5.3 stop mode ............................................................................................................... .......................... 100 10.6 oscillation stop detection function ....................................................................................... .............. 104 10.6.1 how to use oscillation stop detection function .......................................................................... ... 104 10.7 notes on clock generation circuit ......................................................................................... .............. 108 10.7.1 stop mode ............................................................................................................... .......................... 108 10.7.2 wait mode ............................................................................................................... ......................... 108 10.7.3 oscillation stop detection function ..................................................................................... ............ 108 10.7.4 oscillation circuit constants ........................................................................................... ................. 108 a - 3 11. protection ................................................................................................................. ................... 109 12. interrupts ................................................................................................................. ..................... 110 12.1 interrupt overview ................................... ..................................................................... ........................ 110 12.1.1 types of interrupts ..................................................................................................... ....................... 110 12.1.2 software interrupts ..................................................................................................... ...................... 111 12.1.3 special interrupts ...................................................................................................... ........................ 112 12.1.4 peripheral function interrup t ........................................................................................... ................. 112 12.1.5 interrupts and interrupt vect ors ........................................................................................ ................ 113 12.1.6 interrupt control ....................................................................................................... ........................ 115 12.2 int interrupt .................................................................................................................... ..................... 124 12.2.1 inti interrupt (i = 0, 1, 3) ...................................................................................................... ........... 124 12.2.2 inti input filter (i = 0, 1, 3) ................................................................................................... .......... 126 12.3 key input interrupt ....................................................................................................... ......................... 127 12.4 address match interrupt ................................................................................................... ..................... 129 12.5 timer rc interrupt, clock synchronous serial i/o with chip select interrupts, and i 2 c bus interface interrupt (interrupts with multiple interrupt request so urces) ............................................................ 131 12.6 notes on interrupts ....................................................................................................... ......................... 133 12.6.1 reading address 00000h ....... .............. .............. .............. .............. .............. ............ ......... ................ 133 12.6.2 sp setting .............................................................................................................. ............................ 133 12.6.3 external interrupt and key input interrupt ..... ......................................................................... ......... 133 12.6.4 changing interrupt sources .............................................................................................. ................ 134 12.6.5 changing interrupt control register contents .. .......................................................................... ..... 135 13. watchdog timer ............................................................................................................. ............. 136 13.1 count source protection mode disabled ..................................................................................... ......... 139 13.2 count source protection mode enabled ...................................................................................... ......... 140 14. timers ..................................................................................................................... .................... 141 14.1 timer ra .................................................................................................................. ............................. 143 14.1.1 timer mode .............................................................................................................. ........................ 146 14.1.2 pulse output mode ....................................................................................................... .................... 148 14.1.3 event counter mode ...................................................................................................... ................... 150 14.1.4 pulse width measurement mode ............................................................................................ .......... 152 14.1.5 pulse period measurement mode ........................................................................................... .......... 155 14.1.6 notes on timer ra ....................................................................................................... .................... 158 14.2 timer rb .................................................................................................................. ............................. 159 14.2.1 timer mode .............................................................................................................. ........................ 163 14.2.2 programmable waveform generation mode ................................................................................... . 166 14.2.3 programmable one-shot generation mode .......... ......................................................................... ... 169 14.2.4 programmable wait one-shot generation mode ............................................................................. 173 14.2.5 notes on timer rb ....................................................................................................... .................... 177 14.3 timer rc .................................................................................................................. ............................. 181 14.3.1 overview ................................................................................................................ ........................... 181 14.3.2 registers associated with ti mer rc ...................................................................................... .......... 183 14.3.3 common items for multiple mo des ......................................................................................... ........ 193 14.3.4 timer mode (input capture function) ..................................................................................... ........ 199 14.3.5 timer mode (output compare f unction) .................................................................................... ..... 204 14.3.6 pwm mode ................................................................................................................ ....................... 210 a - 4 14.3.7 pwm2 mode ............................................................................................................... ...................... 215 14.3.8 timer rc interrupt ...................................................................................................... ..................... 221 14.3.9 notes on timer rc ....................................................................................................... .................... 222 14.4 timer re .................................................................................................................. ............................. 223 14.4.1 real-time clock mode (for n, d version only) ............................................................................ 224 14.4.2 output compare mode ..................................................................................................... ................ 232 14.4.3 notes on timer re ....................................................................................................... .................... 238 15. serial interface ........................................................................................................... ................. 241 15.1 clock synchronous serial i/o mode ................ ......................................................................... ............ 248 15.1.1 polarity select function ................................................................................................ .................... 251 15.1.2 lsb first/msb first select f unction ..................................................................................... .......... 251 15.1.3 continuous receive mode .. .............. .............. .............. ............... .............. .............. .......... ............... 252 15.2 clock asynchronous serial i/o (uart) mode ................................................................................. ... 253 15.2.1 bit rate ................................................................................................................ ............................. 257 15.3 notes on serial interface ................................................................................................. ...................... 258 16. clock synchronous serial interface ............. ............................................................................ ... 259 16.1 mode selection ............................................................................................................ .......................... 259 16.2 clock synchronous serial i/o with chip select (s su) ....................................................................... . 260 16.2.1 transfer clock ................. ......................................................................................... ........................ 270 16.2.2 ss shift register (sstrsr) .............................................................................................. ............... 272 16.2.3 interrupt requests ...................................................................................................... ....................... 273 16.2.4 communication modes and pin f unctions ................................................................................... .... 274 16.2.5 clock synchronous communication mode .................................................................................... .. 275 16.2.6 operation in 4-wire bus communication mode ..... ......................................................................... 282 16.2.7 scs pin control and arbitration .................................................................................................. .... 288 16.2.8 notes on clock synchronous serial i/o with chip select ............................................................... 28 9 16.3 i 2 c bus interface .............. .............. .............. .............. .............. .............. .............. ............. ..................... 290 16.3.1 transfer clock ................. ......................................................................................... ........................ 300 16.3.2 interrupt requests ...................................................................................................... ....................... 301 16.3.3 i 2 c bus interface mode .... .............. .............. ............... .............. ........... ........... ............ ........... ........... 302 16.3.4 clock synchronous serial mode ........................................................................................... ........... 313 16.3.5 noise canceller ......................................................................................................... ........................ 316 16.3.6 bit synchronization circuit ............................................................................................. ................. 317 16.3.7 examples of register settin g ............................................................................................ ................ 318 16.3.8 notes on i 2 c bus interface ........ .............. .............. .............. .............. .............. ............ ........... .......... . 322 17. hardware lin ............................................................................................................... ............... 323 17.1 features .................................................................................................................. ............................... 323 17.2 input/output pins ......................................................................................................... ......................... 324 17.3 register configuration .................................................................................................... ...................... 325 17.4 functional description .................................................................................................... ...................... 327 17.4.1 master mode ............................................................................................................. ........................ 327 17.4.2 slave mode .............................................................................................................. ......................... 330 17.4.3 bus collision detection function ........................................................................................ ............. 334 17.4.4 hardware lin end pr ocessing ............................................................................................. ............ 335 17.5 interrupt requests ........................................................................................................ .......................... 336 17.6 notes on hardware lin ..................................................................................................... ................... 337 a - 5 18. a/d converter .............................................................................................................. ............... 338 18.1 one-shot mode ............................................................................................................. ........................ 342 18.2 repeat mode ............................................................................................................... ........................... 345 18.3 sample and hold ........................................................................................................... ........................ 348 18.4 a/d conversion cycles ..................................................................................................... .................... 348 18.5 internal equivalent circuit of analog input ..... .......................................................................... ........... 349 18.6 output impedance of sensor under a/d conversion ........................................................................... . 350 18.7 notes on a/d converter .................................................................................................... .................... 351 19. flash memory ............................................................................................................... .............. 352 19.1 overview .................................................................................................................. ............................. 352 19.2 memory map ................................................................................................................ ......................... 353 19.3 functions to prevent rewriting of flash memory ............................................................................ .... 355 19.3.1 id code check function .................................................................................................. ................ 355 19.3.2 rom code protect function .......................... ..................................................................... ............. 356 19.4 cpu rewrite mode .......................................................................................................... ..................... 357 19.4.1 ew0 mode ................................................................................................................ ........................ 358 19.4.2 ew1 mode ................................................................................................................ ........................ 358 19.4.3 software commands ....................................................................................................... .................. 367 19.4.4 status registers ........................................................................................................ ......................... 372 19.4.5 full status check ....................................................................................................... ....................... 373 19.5 standard serial i/o mode .................................................................................................. .................... 375 19.5.1 id code check function .................................................................................................. ................ 375 19.6 parallel i/o mode ......................................................................................................... ......................... 378 19.6.1 rom code protect function .......................... ..................................................................... ............. 378 19.7 notes on flash memory ..................................................................................................... ................... 379 19.7.1 cpu rewrite mode ........................................................................................................ ................... 379 20. electrical characteristics ................................................................................................. ........... 382 20.1 n, d version .............................................................................................................. ............................ 382 20.2 j, k version .............................................................................................................. ............................. 407 21. usage notes ................................................................................................................ ............... 427 21.1 notes on clock generation circuit ......................................................................................... .............. 427 21.1.1 stop mode ............................................................................................................... .......................... 427 21.1.2 wait mode ............................................................................................................... ......................... 427 21.1.3 oscillation stop detection function ..................................................................................... ............ 427 21.1.4 oscillation circuit constants ........................................................................................... ................. 427 21.2 notes on interrupts ....................................................................................................... ......................... 428 21.2.1 reading address 00000h ....... .............. .............. .............. .............. .............. ............ ......... ................ 428 21.2.2 sp setting .............................................................................................................. ............................ 428 21.2.3 external interrupt and key input interrupt ..... ......................................................................... ......... 428 21.2.4 changing interrupt sources .............................................................................................. ................ 429 21.2.5 changing interrupt control register contents .. .......................................................................... ..... 430 21.3 notes on timers ........................................................................................................... ......................... 431 21.3.1 notes on timer ra ....................................................................................................... .................... 431 21.3.2 notes on timer rb ....................................................................................................... .................... 432 21.3.3 notes on timer rc ....................................................................................................... .................... 436 21.3.4 notes on timer re ....................................................................................................... .................... 437 a - 6 21.4 notes on serial interface ................................................................................................. ...................... 440 21.5 notes on clock synchr onous serial interface ..... .............. ............... ........... ........... ........... ............ ........ 441 21.5.1 notes on clock synchronous serial i/o with chip select ............................................................... 44 1 21.5.2 notes on i 2 c bus interface ........ .............. .............. .............. .............. .............. ............ ........... .......... . 441 21.6 notes on hardware lin ..................................................................................................... ................... 442 21.7 notes on a/d converter .................................................................................................... .................... 443 21.8 notes on flash memory ..................................................................................................... ................... 444 21.8.1 cpu rewrite mode ........................................................................................................ ................... 444 21.9 notes on noise ............................................................................................................ .......................... 447 21.9.1 inserting a bypass capacitor between vcc and vss pins as a countermeasure against noise and latch-up ...................................................................................................................... ...................... 447 21.9.2 countermeasures against noise error of port contro l registers ..................................................... 447 22. notes for on-chip debugger ................................................................................................. ..... 448 appendix 1. package dimensions ................................................................................................. ....... 449 appendix 2. connection examples between serial wr iter and on-chip debugging emulator ............ 450 appendix 3. example of oscillati on evaluation circuit ......................................................................... 451 index ......................................................................................................................... ............................ 452 b - 1 note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol page 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 77 0005h processor mode register 1 pm1 77 0006h system clock control register 0 cm0 81 0007h system clock control register 1 cm1 82 0008h 0009h 000ah protect register prcr 109 000bh 000ch oscillation stop detection register ocd 83 000dh watchdog timer reset register wdtr 138 000eh watchdog timer start register wdts 138 000fh watchdog timer control register wdc 137 0010h address match interrupt register 0 rmad0 130 0011h 0012h 0013h address match interrupt enable register aier 130 0014h address match interrupt register 1 rmad1 130 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 138 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 84 0024h high-speed on-chip oscillator control register 1 fra1 84 0025h high-speed on-chip oscillator control register 2 fra2 85 0026h 0027h 0028h clock prescaler reset flag cpsrf 86 0029h high-speed on-chip oscillator control register 4 fra4 85 002ah 002bh high-speed on-chip oscillator control register 6 fra6 85 002ch high-speed on-chip oscillator control register 7 fra7 85 0030h 0031h voltage detection register 1 vca1 39 0032h voltage detection register 2 vca2 39, 40, 86, 87 0033h 0034h 0035h 0036h voltage monitor 1 circuit control register vw1c 42, 43 0037h voltage monitor 2 circuit control register vw2c 44 0038h voltage monitor 0 circuit control register vw0c 41 0039h 003ah 003bh 003ch 003dh 003eh 003fh address register symbol page 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h timer rc interrupt control register trcic 116 0048h 0049h 004ah timer re interrupt control register treic 115 004bh 004ch 004dh key input interrupt control register kupic 115 004eh a/d conversion interrupt control register adic 115 004fh ssu/iic bus interrupt control register ssuic/iicic 116 0050h 0051h uart0 transmit interrupt control register s0tic 115 0052h uart0 receive interrupt control register s0ric 115 0053h uart1 transmit interrupt control register s1tic 115 0054h uart1 receive interrupt control register s1ric 115 0055h 0056h timer ra interrupt control register traic 115 0057h 0058h timer rb interrupt control register trbic 115 0059h int1 interrupt control register int1ic 117 005ah int3 interrupt control register int3ic 117 005bh 005ch 005dh int0 interrupt control register int0ic 117 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh sfr page reference b - 2 note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol page 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 244 00a1h uart0 bit rate register u0brg 244 00a2h uart0 transmit buffer register u0tb 243 00a3h 00a4h uart0 transmit/receive control register 0 u0c0 245 00a5h uart0 transmit/receive control register 1 u0c1 246 00a6h uart0 receive buffer register u0rb 243 00a7h 00a8h uart1 transmit/receive mode register u1mr 244 00a9h uart1 bit rate register u1brg 244 00aah uart1 transmit buffer register u1tb 243 00abh 00ach uart1 transmit/receive control register 0 u1c0 245 00adh uart1 transmit/receive control register 1 u1c1 246 00aeh uart1 receive buffer register u1rb 243 00afh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h ss control register h / iic bus control register 1 sscrh / iccr1 262, 293 00b9h ss control register l / iic bus control register 2 sscrl / iccr2 263, 294 00bah ss mode register / iic bus mode register ssmr / icmr 264, 295 00bbh ss enable register / iic bus interrupt enable register sser / icier 265, 296 00bch ss status register / iic bus status register sssr / icsr 266, 297 00bdh ss mode register 2 / slave address register ssmr2 / sar 267, 298 00beh ss transmit data register / iic bus transmit data register sstdr / icdrt 268, 298 00bfh ss receive data register / iic bus receive data register ssrdr / icdrr 268, 298 address register symbol page 00c0h a/d register ad 341 00c1h 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h a/d control register 2 adcon2 341 00d5h 00d6h a/d control register 0 adcon0 340 00d7h a/d control register 1 adcon1 341 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h port p0 register p0 61 00e1h port p1 register p1 61 00e2h port p0 direction register pd0 60 00e3h port p1 direction register pd1 60 00e4h 00e5h port p3 register p3 61 00e6h 00e7h port p3 direction register pd3 60 00e8h port p4 register p4 61 00e9h port p5 register p5 61 00eah port p4 direction register pd4 60 00ebh port p5 direction register pd5 60 00ech 00edh 00eeh 00efh 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h pin select register 1 pinsr1 62, 247 00f6h pin select register 2 pinsr2 62 00f7h pin select register 3 pinsr3 62 00f8h port mode register pmr 63, 247, 269, 299 00f9h external input enable register inten 124 00fah int input filter select register intf 125 00fbh key input enable register kien 128 00fch pull-up control register 0 pur0 64 00fdh pull-up control register 1 pur1 64 00feh port p1 drive capacity control register p1drr 64 00ffh b - 3 note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol page 0100h timer ra control register tracr 144 0101h timer ra i/o control register traioc 144, 146, 149, 151, 153, 156 0102h timer ra mode register tramr 145 0103h timer ra prescaler register trapre 145 0104h timer ra register tra 145 0105h 0106h lin control register lincr 325 0107h lin status register linst 326 0108h timer rb control register trbcr 160 0109h timer rb one-shot control register trbocr 160 010ah timer rb i/o control register trbioc 161, 163, 167, 170, 175 010bh timer rb mode register trbmr 161 010ch timer rb prescaler register trbpre 162 010dh timer rb secondary register trbsc 162 010eh timer rb primary register trbpr 162 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register tresec 226, 234 0119h timer re minute data register / compare data register tremin 226, 234 011ah timer re hour data register trehr 227 011bh timer re day of week data register trewk 227 011ch timer re control register 1 trecr1 228, 235 011dh timer re control register 2 trecr2 229, 235 011eh timer re count source select register trecsr 230, 236 011fh 0120h timer rc mode register trcmr 184 0121h timer rc control register 1 trccr1 185, 208, 212, 217 0122h timer rc interrupt enable register trcier 186 0123h timer rc status register trcsr 187 0124h timer rc i/o control register 0 trcior0 192, 201, 206 0125h timer rc i/o control register 1 trcior1 192, 202, 207 0126h timer rc counter trc 188 0127h 0128h timer rc general register a trcgra 188 0129h 012ah timer rc general register b trcgrb 188 012bh 012ch timer rc general register c trcgrc 188 012dh 012eh timer rc general register d trcgrd 188 012fh address register symbol page 0130h timer rc control register 2 trccr2 189 0131h timer rc digital filter function select register trcdf 190 0132h timer rc output master enable register trcoer 191 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013ah 013bh 013ch 013dh 013eh 013fh 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014ah 014bh 014ch 014dh 014eh 014fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015ah 015bh 015ch 015dh 015eh 015fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh b - 4 note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol page 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018ah 018bh 018ch 018dh 018eh 018fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019ah 019bh 019ch 019dh 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh address register symbol page 01b0h 01b1h 01b2h 01b3h flash memory control register 4 fmr4 363 01b4h 01b5h flash memory control register 1 fmr1 362 01b6h 01b7h flash memory control register 0 fmr0 361 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh ffffh option function select register ofs 27, 137, 356 rev.2.10 sep 26, 2008 page 1 of 453 rej09b0278-0210 r8c/26 group, r8c/27 group single-chip 16-bit cmos mcu 1. overview these mcus are fabricated using a hi gh-performance silicon gate cmos pro cess, embedding the r8c cpu core, and are packaged in a 32-pin mold ed-plastic lqfp. it implements sophisticated instructions for a high level of instruction efficiency. with 1 mbyte of address space, they ar e capable of executing instructions at high speed. furthermore, the r8c/27 group has on-chip data flash (1 kb 2 blocks). the difference between the r8c/26 group and r8c/27 group is only the presence or absence of data flash. their peripheral functions are the same. 1.1 applications electronic household appliances, offi ce equipment, audio equipment, c onsumer products, automotive, etc. rej09b0278-0210 rev.2.10 sep 26, 2008 r8c/26 group, r8c/27 group 1. overview rev.2.10 sep 26, 2008 page 2 of 453 rej09b0278-0210 1.2 performance overview table 1.1 outlines the functions and specifications for r8c/26 group and table 1.2 outlines the functions and specifications for r8c/27 group. notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. specify the d, k version if d, k version functions are to be used. table 1.1 functions and specifications for r8c/26 group item specification cpu number of fundamental instructions 89 instructions minimum instruction execution time 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) (other than k version) 62.5 ns (f(xin) = 16 mhz, vcc = 3.0 to 5.5 v) (k version) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 2.2 to 5.5 v) (n, d version) operating mode single-chip address space 1 mbyte memory capacity refer to table 1.3 product information for r8c/26 group peripheral functions ports i/o ports: 25 pins, input port: 3 pins led drive ports i/o ports: 8 pins (n, d version) timers timer ra: 8 bits 1 channel timer rb: 8 bits 1 channel (each timer equipped with 8-bit prescaler) timer rc: 16 bits 1 channel (input capture and out put compare circuits) timer re: with real-time clock and compare match function (for j, k version, compare match function only.) serial interfaces 2 channels (uart0, uart1) clock synchronous serial i/o, uart clock synchronous serial interface 1 channel i 2 c bus interface (1) clock synchronous serial i/o with chip select lin module hardware lin: 1 channel (timer ra, uart0) a/d converter 10-bit a/d converter: 1 circuit, 12 channels watchdog timer 15 bits 1 channel (with prescaler) start-on-reset selectable interrupts internal: 15 sour ces, external: 4 sources, software: 4 sources, priority levels: 7 levels clock generation circuits 3 circuits ? xin clock generation circuit (with on-chip feedback resistor) ? on-chip oscillator (high speed, low speed) high-speed on-chip oscillator has a frequency adjustment function ? xcin clock generation circuit (32 khz) (n, d version) ? real-time clock (timer re) (n, d version) oscillation-stopped detector xin clock oscillation stop detection function voltage detection circuit on-chip power-on reset circuit on-chip electrical characteristics supply voltage vcc = 3.0 to 5.5 v (f(xin) = 20 mhz) (other than k version) vcc = 3.0 to 5.5 v (f(xin) = 16 mhz) (k version) vcc = 2.7 to 5.5 v (f(xin) = 10 mhz) vcc = 2.2 to 5.5 v (f(xin) = 5 mhz) (n, d version) current consumption (n, d version) typ. 10 ma (vcc = 5.0 v, f(xin) = 20 mhz) typ. 6 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 2.0 r8c/26 group, r8c/27 group 1. overview rev.2.10 sep 26, 2008 page 3 of 453 rej09b0278-0210 notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. specify the d, k version if d, k version functions are to be used. table 1.2 functions and specifications for r8c/27 group item specification cpu number of fundamental instructions 89 instructions minimum instruction execution time 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) (other than k version) 62.5 ns (f(xin) = 16 mhz, vcc = 3.0 to 5.5 v) (k version) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 2.2 to 5.5 v) (n, d version) operating mode single-chip address space 1 mbyte memory capacity refer to table 1.4 product information of r8c/27 group peripheral functions ports i/o ports: 25 pins, input port: 3 pins led drive ports i/o ports: 8 pins (n, d version) timers timer ra: 8 bits 1 channel timer rb: 8 bits 1 channel (each timer equipped with 8-bit prescaler) timer rc: 16 bits 1 channel (input capture and output compare circuits) timer re: with real-time clock and compare match function (for j, k version, compare match function only.) serial interfaces 2 channels (uart0, uart1) clock synchronous serial i/o, uart clock synchronous serial interface 1 channel i 2 c bus interface (1) clock synchronous serial i/o with chip select lin module hardware lin: 1 channel (timer ra, uart0) a/d converter 10-bit a/d conver ter: 1 circuit, 12 channels watchdog timer 15 bits 1 channel (with prescaler) start-on-reset selectable interrupts internal: 15 sources, external: 4 sources, software: 4 sources, pr iority levels: 7 levels clock generation circuits 3 circuits ? xin clock generation circuit (with on-chip feedback resistor) ? on-chip oscillator (high speed, low speed) high-speed on-chip oscillator has a frequency adjustment function ? xcin clock generation circuit (32 khz) (n, d version) ? real-time clock (timer re) (n, d version) oscillation-stopped detector xin clock oscillation stop detection function voltage detection circuit on-chip power-on reset circuit on-chip electrical characteristics supply voltage vcc = 3.0 to 5.5 v (f(xin) = 20 mhz) (other than k version) vcc = 3.0 to 5.5 v (f(xin) = 16 mhz) (k version) vcc = 2.7 to 5.5 v (f(xin) = 10 mhz) vcc = 2.2 to 5.5 v (f(xin) = 5 mhz) (n, d version) current consumption (n, d version) typ. 10 ma (vcc = 5.0 v, f(xin) = 20 mhz) typ. 6 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 2.0 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz) typ. 0.7 a (vcc = 3.0 v, stop mode) flash memory programming and erasure voltage vcc = 2.7 to 5.5 v programming and erasure endurance 10,000 times (data flash) 1,000 times (program rom) operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d, j version) (2) , -40 to 125 c (k version) (2) package 32-pin molded-plastic lqfp r8c/26 group, r8c/27 group 1. overview rev.2.10 sep 26, 2008 page 4 of 453 rej09b0278-0210 1.3 block diagram figure 1.1 shows a block diagram. figure 1.1 block diagram r8c cpu core a/d converter (10 bits 12 channels) uart or clock synchronous serial i/o (8 bits 2 channels) memory watchdog timer (15 bits) rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. 3. xcin, xcout can be used only for n or d version. i 2 c bus interface or clock synchronous serial i/o with chip select (8 bits 1 channel) lin module (1 channel) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout (3) timers timer ra (8 bits) timer rb (8 bits) timer rc (16 bits 1 channel) timer re (8 bits) 8 port p0 8 port p1 6 port p3 1 3 port p4 2 port p5 peripheral functions r8c/26 group, r8c/27 group 1. overview rev.2.10 sep 26, 2008 page 5 of 453 rej09b0278-0210 1.4 product information table 1.3 lists the product information for r8c/26 group and table 1.4 lists the product information for r8c/27 group. note: 1. the user rom is programmed before shipment. table 1.3 product information for r8c/26 group current of sep. 2008 part no. rom capacity ram capacity package type remarks r5f21262snfp 8 kbytes 512 bytes plqp0032gb-a n version r5f21264snfp 16 kbytes 1 kbyte plqp0032gb-a r5f21265snfp 24 kbytes 1.5 kbytes plqp0032gb-a r5f21266snfp 32 kbytes 1.5 kbytes plqp0032gb-a r5f21262sdfp 8 kbytes 512 bytes plqp0032gb-a d version r5f21264sdfp 16 kbytes 1 kbyte plqp0032gb-a r5f21265sdfp 24 kbytes 1.5 kbytes plqp0032gb-a r5f21266sdfp 32 kbytes 1.5 kbytes plqp0032gb-a r5f21264jfp 16 kbytes 1 kbyte plqp0032gb-a j version r5f21266jfp 32 kbytes 1.5 kbytes plqp0032gb-a r5f21264kfp 16 kbytes 1 kbyte plqp0032gb-a k version r5f21266kfp 32 kbytes 1.5 kbytes plqp0032gb-a r5f21262snxxxfp 8 kbytes 512 byte s plqp0032gb-a n version factory programming product (1) r5f21264snxxxfp 16 kbyt es 1 kbyte plqp0032gb-a r5f21265snxxxfp 24 kbytes 1.5 kbytes plqp0032gb-a r5f21266snxxxfp 32 kbytes 1.5 kbytes plqp0032gb-a r5f21262sdxxxfp 8 kbytes 512 bytes plqp0032gb-a d version r5f21264sdxxxfp 16 kbyt es 1 kbyte plqp0032gb-a r5f21265sdxxxfp 24 kbytes 1.5 kbytes plqp0032gb-a r5f21266sdxxxfp 32 kbytes 1.5 kbytes plqp0032gb-a r5f21264jxxxfp 16 kbytes 1 kb yte plqp0032gb-a j version r5f21266jxxxfp 32 kbytes 1.5 kbytes plqp0032gb-a r5f21264kxxxfp 16 kbytes 1 kb yte plqp0032gb-a k version r5f21266kxxxfp 32 kbytes 1.5 kbytes plqp0032gb-a r8c/26 group, r8c/27 group 1. overview rev.2.10 sep 26, 2008 page 6 of 453 rej09b0278-0210 figure 1.2 part number, memory size, and package of r8c/26 group part no. r 5 f 21 26 6 s n xxx fp package type: fp: plqp0032gb-a rom number classification n: operating ambient temperature -20 to 85c (n version) d: operating ambient temperature -40 to 85c (d version) j: operating ambient temperature -40 to 85c (j version) k: operating ambient temperature -40 to 125c (k version) s: low-voltage version (other no symbols) rom capacity 2: 8 kb 4: 16 kb 5: 24 kb 6: 32 kb r8c/26 group r8c/2x series memory type f: flash memory renesas mcu renesas semiconductor r8c/26 group, r8c/27 group 1. overview rev.2.10 sep 26, 2008 page 7 of 453 rej09b0278-0210 note: 1. the user rom is programmed before shipment. table 1.4 product information for r8c/27 group current of sep. 2008 part no. rom capacity ram capacity package type remarks program rom data flash r5f21272snfp 8 kbytes 1 kbyte 2 512 bytes plqp0032gb-a n version r5f21274snfp 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a r5f21275snfp 24 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21276snfp 32 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21272sdfp 8 kbytes 1 kbyte 2 512 bytes plqp0032gb-a d version r5f21274sdfp 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a r5f21275sdfp 24 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21276sdfp 32 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21274jfp 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a j version r5f21276jfp 32 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21274kfp 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a k version r5f21276kfp 32 kbytes 1 kbyte 2 1.5 kbytes plqp0032gb-a r5f21272snxxxfp 8 kbytes 1 kbyte 2 512 bytes plqp0032gb-a n version factory programming product (1) r5f21274snxxxfp 16 kbytes 1 kb yte 2 1 kbyte plqp0032gb-a r5f21275snxxxfp 24 kbytes 1 kbyt e 2 1.5 kbytes plqp0032gb-a r5f21276snxxxfp 32 kbytes 1 kbyt e 2 1.5 kbytes plqp0032gb-a r5f21272sdxxxfp 8 kbytes 1 kbyte 2 512 bytes plqp0032gb-a d version r5f21274sdxxxfp 16 kbytes 1 kb yte 2 1 kbyte plqp0032gb-a r5f21275sdxxxfp 24 kbytes 1 kbyt e 2 1.5 kbytes plqp0032gb-a r5f21276sdxxxfp 32 kbytes 1 kbyt e 2 1.5 kbytes plqp0032gb-a r5f21274jxxxfp 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a j version r5f21276jxxxfp 32 kbytes 1 kbyt e 2 1.5 kbytes plqp0032gb-a r5f21274kxxxfp 16 kbytes 1 kbyte 2 1 kbyte plqp0032gb-a k version r5f21276kxxxfp 32 kbytes 1 kbyt e 2 1.5 kbytes plqp0032gb-a r8c/26 group, r8c/27 group 1. overview rev.2.10 sep 26, 2008 page 8 of 453 rej09b0278-0210 figure 1.3 part number, memory size, and package of r8c/27 group part no. r 5 f 21 27 6 s n xxx fp package type: fp: plqp0032gb-a rom number classification n: operating ambient temperature -20 to 85c (n version) d: operating ambient temperature -40 to 85c (d version) j: operating ambient temperature -40 to 85c (j version) k: operating ambient temperature -40 to 125c (k version) s: low-voltage version (other no symbols) rom capacity 2: 8 kb 4: 16 kb 5: 24 kb 6: 32 kb r8c/27 group r8c/2x series memory type f: flash memory renesas mcu renesas semiconductor r8c/26 group, r8c/27 group 1. overview rev.2.10 sep 26, 2008 page 9 of 453 rej09b0278-0210 1.5 pin assignments figure 1.4 shows pin assignments (top view). figure 1.4 pin assignments (top view) notes: 1. p4_7 is an input-only port. 2. can be assigned to the pin in parentheses by a program. 3. xcin, xcout can be used only for n or d version. 4. confirm the pin 1 position on the package by referring to the package dimensions. r8c/26 group r8c/27 group xin/xcin/p4_6 (3) xout/xcout/p4_7 (1, 3) vss/avss reset vcc/avcc p3_7/trao/sso/rxd1/(txd1) (2) mode p4_5/int0/(rxd1) (2) p1_7/traio/int1 p3_6/(txd1)/(rxd1)/(int1) (2) p3_5/scl/ssck/(trciod) (2) p1_0/ki0/an8 p1_4/txd0 vref/p4_2 p1_3/ki3/an11/(trbo) p3_3/int3/ssi/trcclk p1_1/ki1/an9/trcioa/trctrg p1_2/ki2/an10/trciob p0_3/an4 p0_2/an5 p0_1/an6 p0_0/an7/(txd1) (2) p0_7/an0 p0_6/an1 p0_5/an2/clk1 p1_5/rxd0/(traio)/(int1) (2) p1_6/clk0/(ssi) (2) p5_3/trcioc p5_4/trciod p3_1/trbo p3_4/sda/scs/(trcioc) (2) p0_4/an3/treo 29 28 27 26 25 32 31 30 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 578 1234 6 plqp0032gb-a (32p6u-a) (top view) r8c/26 group, r8c/27 group 1. overview rev.2.10 sep 26, 2008 page 10 of 453 rej09b0278-0210 1.6 pin functions table 1.5 lists pin functions. i: input o: output i/o: input and output table 1.5 pin functions type symbol i/o type description power supply input vcc, vss i apply 2.2 to 5.5 v (j, k version are 2.7 to 5.5 v) to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss i power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xin clock input xin i these pins are provided for xin clock generation circuit i/o. connect a ceramic resonator or a crystal oscillator between the xin and xout pins. to use an exte rnal clock, input it to the xin pin and leave the xout pin open. xin clock output xout o xcin clock input (n, d version) xcin i these pins are provided for xc in clock generation circuit i/o. connect a crystal oscillator between the xcin and xcout pins. to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output (n, d version) xcout o int interrupt input int0 , int1 , int3 iint interrupt input pins key input interrupt ki0 to ki3 i key input interrupt input pins timer ra trao o timer ra output pin traio i/o timer ra i/o pin timer rb trbo o timer rb output pin timer rc trcclk i external clock input pin trctrg i external trigger input pin trcioa, trciob, trcioc, trciod i/o sharing output-compare output / input-capture input / pwm / pwm2 output pins timer re treo o timer re output pin serial interface clk0, clk1 i/o clock i/o pin rxd0, rxd1 i receive data input pin txd0, txd1 o transmit data output pin i 2 c bus interface scl i/o clock i/o pin sda i/o data i/o pin clock synchronous serial i/o with chip select ssi i/o data i/o pin scs i/o chip-select signal i/o pin ssck i/o clock i/o pin sso i/o data i/o pin reference voltage input vref i reference voltage input pin to a/d converter a/d converter an0 to an11 i analog input pins to a/d converter i/o port p0_0 to p0_7, p1_0 to p1_7, p3_1, p3_3 to p3_7, p4_5, p5_3, p5_4 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. p1_0 to p1_7 also function as led drive ports (n, d version). input port p4_2, p4_6, p4_7 i input-only ports r8c/26 group, r8c/27 group 1. overview rev.2.10 sep 26, 2008 page 11 of 453 rej09b0278-0210 notes: 1. this can be assigned to the pin in parentheses by a program. 2. xcin, xcout can be used only for n or d version. 3. for the combination of using pins txd1 and rxd1, refer to figure 15.7 registers pinsr1 and pmr . table 1.6 pin name information by pin number pin number control pin port i/o pin functions for of peripheral modules interrupt timer serial interface clock synchronous serial i/o with chip select i 2 c bus interface a/d converter 1 p3_5 (trciod) (1) ssck scl 2 p3_7 trao rxd1/ (txd1) (1, 3) sso 3 reset 4 xout/xcout (2) p4_7 5 vss/avss 6 xin/xcin (2) p4_6 7vcc/avcc 8mode 9 p4_5 int0 (rxd1) (1, 3) 10 p1_7 int1 traio 11 p3_6 (int1 ) (1) (txd1)/ (rxd1) (1, 3) 12 p3_1 trbo 13 p5_4 trciod 14 p5_3 trcioc 15 p1_6 clk0 (ssi) (1) 16 p1_5 (int1 ) (1) (traio) (1) rxd0 17 p1_4 txd0 18 p1_3 ki3 (trbo) an11 19 p1_2 ki2 trciob an10 20 vrff p4_2 21 p1_1 ki1 trcioa/ trctrg an9 22 p1_0 ki0 an8 23 p3_3 int3 trcclk ssi 24 p3_4 (trcioc) (1) scs sda 25 p0_7 an0 26 p0_6 an1 27 p0_5 clk1 an2 28 p0_4 treo an3 29 p0_3 an4 30 p0_2 an5 31 p0_1 an6 32 p0_0 (txd1) (1, 3) an7 r8c/26 group, r8c/27 group 2. ce ntral processing unit (cpu) rev.2.10 sep 26, 2008 page 12 of 453 rej09b0278-0210 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high order bits of intb are intbh and the 16 low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a regist er bank. there are two register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1) r8c/26 group, r8c/27 group 2. ce ntral processing unit (cpu) rev.2.10 sep 26, 2008 page 13 of 453 rej09b0278-0210 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, ar ithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is analogous to a0. a1 can be combined with a0 to be used as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register th at indicates the start address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp, and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operation results in an overflow; otherwise to 0. r8c/26 group, r8c/27 group 2. ce ntral processing unit (cpu) rev.2.10 sep 26, 2008 page 14 of 453 rej09b0278-0210 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupt are disabled when the i flag is set to 0, and are enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt requ est is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interrupt priority le vels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined. r8c/26 group, r8c/27 group 3. memory rev.2.10 sep 26, 2008 page 15 of 453 rej09b0278-0210 3. memory 3.1 r8c/26 group figure 3.1 is a memory map of r8c/26 group. the r8c/ 26 group has 1 mbyte of addr ess space from addresses 00000h to fffffh. the internal rom is allocated lower addresses, beginning with address 0ffffh. for example, a 16-kbyte internal rom area is allocated addr esses 0c000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal ram is allocated highe r addresses beginning with address 00400h. for example, a 1-kbyte internal ram area is allocated addresses 00400h to 007ffh. the internal ram is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresse s within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.1 memory map of r8c/26 group undefined instruction overflow brk instruction address match single step watchdog timer/oscillation stop detection/voltage monitor (reserved) (reserved) reset 00400h 002ffh 00000h internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch note: 1. the blank regions are reserved. do not access locations in these regions. fffffh 0ffffh 0yyyyh internal rom (program rom) 0xxxh part number internal rom internal ram size size r5f21262snfp, r5f21262sdfp, r5f21262snxxxfp, r5f21262sdxxxfp r5f21264snfp, r5f21264sdfp, r5f21264jfp, r5f21264kfp, r5f21264snxxxfp, r5f21264sdxxxfp, r5f21264jxxxfp, r5f21264kxxxfp r5f21265snfp, r5f21265sdfp r5f21265snxxxfp, r5f21265sdxxxfp r5f21266snfp, r5f21266sdfp, r5f21266jfp, r5f21266kfp, r5f21266snxxxfp, r5f21266sdxxxfp, r5f21266jxxxfp, r5f21266kxxxfp 8 kbytes 16 kbytes 24 kbytes 32 kbytes 0e000h 0c000h 0a000h 08000h 512 bytes 1 kbyte 1.5 kbytes 1.5 kbytes 005ffh 007ffh 009ffh 009ffh address 0yyyyh address 0xxxxh r8c/26 group, r8c/27 group 3. memory rev.2.10 sep 26, 2008 page 16 of 453 rej09b0278-0210 3.2 r8c/27 group figure 3.2 is a memory map of r8c/27 group. the r8c/ 27 group has 1 mbyte of addr ess space from addresses 00000h to fffffh. the internal rom (program rom) is allocated lower ad dresses, beginning with a ddress 0ffffh. for example, a 16-kbyte internal rom area is allocated addresses 0c000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal rom (data flash) is allocated addresses 02400h to 02bffh. the internal ram area is allocated higher addresses, beginning with address 00400h. for example, a 1-kbyte internal ram is allocated addresses 00400h to 007ffh. the internal ram is used not only for storing data but also for calling subroutines and as stacks wh en interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresse s within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.2 memory map of r8c/27 group undefined instruction overflow brk instruction address match single step watchdog timer/oscillation stop detection/voltage monitor (reserved) (reserved) reset fffffh 0ffffh 0yyyyh 00400h 002ffh 00000h internal rom (program rom) internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch internal rom (data flash) (1) notes: 1. data flash block a (1 kbyte) and b (1 kbyte) are shown. 2. the blank regions are reserved. do not access locations in these regions. 0xxxxh 02400h 02bffh part number internal rom internal ram size address 0yyyyh size address 0xxxxh r5f21272snfp, r5f21272sdfp, r5f21272snxxxfp, r5f21272sdxxxfp r5f21274snfp, r5f21274sdfp, r5f21274jfp, r5f21274kfp, r5f21274snxxxfp, r5f21274sdxxxfp, r5f21274jxxxfp, r5f21274kxxxfp r5f21275snfp, r5f21275sdfp, r5f21275snxxxfp, r5f21275sdxxxfp r5f21276snfp, r5f21276sdfp, r5f21276jfp, r5f21276kfp, r5f21276snxxxfp, r5f21276sdxxxfp, r5f21276jxxxfp, r5f21276kxxxfp 8 kbytes 16 kbytes 24 kbytes 32 kbytes 0e000h 0c000h 0a000h 08000h 512 bytes 1 kbyte 1.5 kbytes 1.5 kbytes 005ffh 007ffh 009ffh 009ffh r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.2.10 sep 26, 2008 page 17 of 453 rej09b0278-0210 4. special function registers (sfrs) an sfr (special function register) is a control register fo r a peripheral function. tables 4.1 to 4.7 list the special function registers. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. the csproini bit in the ofs register is set to 0. 3. in j, k version these regions are reserved . do not access locations in these regions. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 01101000b 0007h system clock control register 1 cm1 00100000b 0008h 0009h 000ah protect register prcr 00h 000bh 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00x11111b 0010h address match interrupt register 0 rmad0 00h 0011h 00h 0012h 00h 0013h address match interrupt enable register aier 00h 0014h address match interrupt register 1 rmad1 00h 0015h 00h 0016h 00h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (2) 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator control register 1 fra1 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h 0027h 0028h clock prescaler reset flag cpsrf 00h 0029h high-speed on-chip oscillator control register 4 (3) fra4 when shipping 002ah 002bh high-speed on-chip oscillator control register 6 (3) fra6 when shipping 002ch high-speed on-chip oscillator control register 7 (3) fra7 when shipping 002dh 002eh 002fh r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.2.10 sep 26, 2008 page 18 of 453 rej09b0278-0210 table 4.2 sfr information (2) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. (n, d version) software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this r egister. (j, k version) software reset, watchdog timer reset, or voltage monitor 2 reset do not affect this register. 3. the lvd0on bit in the ofs register is set to 1 and hardware reset. 4. power-on reset, voltage monitor 0 reset or the lvd0on bit in the ofs register is set to 0, and hardware reset. 5. (n, d version) software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3. (j, k version) software reset, watchdog timer reset, or voltage monitor 2 reset do not affect b2 and b3. 6. (n, d version) software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this r egister. (j, k version) these regions are reserved. do not access locations in these regions. 7. the lvd1on bit in the ofs register is set to 1 and hardware reset. 8. power-on reset, voltage monitor 1 reset, or the lvd1on bit in the ofs register is set to 0 and hardware reset. 9. selected by the iicsel bit in the pmr register. address register symbol after reset 0030h 0031h voltage detection register 1 (2) vca1 00001000b 0032h voltage detection register 2 (2) vca2 ?n, d version 00h (3) 00100000b (4) ?j, k version 00h (7) 01000000b (8) 0033h 0034h 0035h 0036h voltage monitor 1 circuit control register (5) vw1c ? n, d version 00001000b ? j, k version 0000x000b (7) 0100x001b (8) 0037h voltage monitor 2 circuit control register (5) vw2c 00h 0038h voltage monitor 0 circuit control register (6) vw0c 0000x000b (3) 0100x001b (4) 0039h 003fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h timer rc interrupt control register trcic xxxxx000b 0048h 0049h 004ah timer re interrupt control register treic xxxxx000b 004bh 004ch 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh ssu/iic bus interrupt control register (9) ssuic/iicic xxxxx000b 0050h 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh 005ch 005dh int0 interrupt control register int0ic xx00x000b 005eh 005fh 0060h 006fh 0070h 007fh r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.2.10 sep 26, 2008 page 19 of 453 rej09b0278-0210 table 4.3 sfr information (3) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. selected by the iicsel bit in the pmr register. address register symbol after reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h uart1 transmit/receive mode register u1mr 00h 00a9h uart1 bit rate register u1brg xxh 00aah uart1 transmit buffer register u1tb xxh 00abh xxh 00ach uart1 transmit/receive control register 0 u1c0 00001000b 00adh uart1 transmit/receive control register 1 u1c1 00000010b 00aeh uart1 receive buffer register u1rb xxh 00afh xxh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h ss control register h / iic bus control register 1 (2) sscrh / iccr1 00h 00b9h ss control register l / iic bus control register 2 (2) sscrl / iccr2 0 1111101b 00bah ss mode register / iic bus mode register (2) ssmr / icmr 00011000b 00bbh ss enable register / iic bus interrupt enable register (2) sser / icier 00h 00bch ss status register / iic bus status register (2) sssr / icsr 00h / 0000x000b 00bdh ss mode register 2 / slave address register (2) ssmr2 / sar 00h 00beh ss transmit data register / iic bus transmit data register (2) sstdr / icdrt ffh 00bfh ss receive data register / iic bus receive data register (2) ssrdr / icdrr ffh r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.2.10 sep 26, 2008 page 20 of 453 rej09b0278-0210 table 4.4 sfr information (4) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. in j, k version these regions are reserved . do not access locations in these regions. address register symbol after reset 00c0h a/d register ad xxh 00c1h xxh 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h a/d control register 2 adcon2 00h 00d5h 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h port p0 register p0 00h 00e1h port p1 register p1 00h 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h 00e5h port p3 register p3 00h 00e6h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 00h 00e9h port p5 register p5 00h 00eah port p4 direction register pd4 00h 00ebh port p5 direction register pd5 00h 00ech 00edh 00eeh 00efh 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h pin select register 1 pinsr1 00h 00f6h pin select register 2 pinsr2 00h 00f7h pin select register 3 pinsr3 00h 00f8h port mode register pmr 00h 00f9h external input enable register inten 00h 00fah int input filter select register intf 00h 00fbh key input enable register kien 00h 00fch pull-up control register 0 pur0 00h 00fdh pull-up control register 1 pur1 00h 00feh port p1 drive capacity control register (2) p1drr 00h 00ffh r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.2.10 sep 26, 2008 page 21 of 453 rej09b0278-0210 table 4.5 sfr information (5) (1) notes: 1. the blank regions are reserved. do not access locations in these regions. 2. in j, k version these regions are reserved . do not access locations in these regions. address register symbol after reset 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h 0106h lin control register lincr 00h 0107h lin status register linst 00h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register tresec 00h 0119h timer re minute data register / compare data register tremin 00h 011ah timer re hour data register (2) trehr 00h 011bh timer re day of week data register (2) trewk 00h 011ch timer re control register 1 trecr1 00h 011dh timer re control register 2 trecr2 00h 011eh timer re count source select register trecsr 00001000b 011fh 0120h timer rc mode register trcmr 01001000b 0121h timer rc control register 1 trccr1 00h 0122h timer rc interrupt enable register trcier 01110000b 0123h timer rc status register trcsr 01110000b 0124h timer rc i/o control register 0 trcior0 10001000b 0125h timer rc i/o control register 1 trcior1 10001000b 0126h timer rc counter trc 00h 0127h 00h 0128h timer rc general register a trcgra ffh 0129h ffh 012ah timer rc general register b trcgrb ffh 012bh ffh 012ch timer rc general register c trcgrc ffh 012dh ffh 012eh timer rc general register d trcgrd ffh 012fh ffh 0130h timer rc control register 2 trccr2 00011111b 0131h timer rc digital filter function select register trcdf 00h 0132h timer rc output master enable register trcoer 0 1111111b 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013ah 013bh 013ch 013dh 013eh 013fh r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.2.10 sep 26, 2008 page 22 of 453 rej09b0278-0210 table 4.6 sfr information (6) (1) note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014ah 014bh 014ch 014dh 014eh 014fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015ah 015bh 015ch 015dh 015eh 015fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh r8c/26 group, r8c/27 group 4. spec ial function registers (sfrs) rev.2.10 sep 26, 2008 page 23 of 453 rej09b0278-0210 table 4.7 sfr information (7) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. the ofs register cannot be changed by a pr ogram. use a flash programmer to write to it. address register symbol after reset 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018ah 018bh 018ch 018dh 018eh 018fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019ah 019bh 019ch 019dh 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h 01b3h flash memory control register 4 fmr4 01000000b 01b4h 01b5h flash memory control register 1 fmr1 1000000xb 01b6h 01b7h flash memory control register 0 fmr0 00000001b 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh ffffh option function select register ofs (note 2) r8c/26 group, r8c/27 group 5. resets rev.2.10 sep 26, 2008 page 24 of 453 rej09b0278-0210 5. resets the following resets are implemented: hardware reset, powe r-on reset, voltage monitor 0 reset (for n, d version only), voltage monitor 1 reset, voltage monitor 2 rese t, watchdog timer reset, and software reset. table 5.1 lists the reset names and sources. figure 5.1 shows the block diagram of reset circuit (n, d version), and figure 5.2 shows the block diagram of reset circuit (j, k version). note: 1. for n, d version only. figure 5.1 block diagram of reset circuit (n, d version) table 5.1 reset names and sources reset name source hardware reset input voltage of reset pin is held ?l? power-on reset vcc rises voltage monitor 0 reset (1) vcc falls (monitor voltage: vdet0) voltage monitor 1 reset vcc falls (monitor voltage: vdet1) voltage monitor 2 reset vcc falls (monitor voltage: vdet2) watchdog timer reset underflow of watchdog timer software reset write 1 to pm03 bit in pm0 register reset power-on reset circuit voltage detection circuit watchdog timer cpu voltage monitor 0 reset sfrs bits vca25, vw0c0, and vw0c6 sfrs bits vca13, vca26, vca27, vw1c2, vw1c3, vw2c2, vw2c3, vw0c1, vw0f0, vw0f1, and vw0c7 pin, cpu, and sfr bits other than those listed above vcc hardware reset power-on reset voltage monitor 1 reset watchdog timer reset software reset vca13: bit in vca1 register vca25, vca26, vca27: bits in vca2 register vw0c0, vw0c1, vw0c6, vw0f0, vw0f1, vw0c7: bits in vw0c register vw1c2, vw1c3: bits in vw1c register vw2c2, vw2c3: bits in vw2c register voltage monitor 2 reset r8c/26 group, r8c/27 group 5. resets rev.2.10 sep 26, 2008 page 25 of 453 rej09b0278-0210 figure 5.2 block diagram of reset circuit (j, k version) reset power-on reset circuit voltage detection circuit watchdog timer cpu voltage monitor 1 reset sfrs bits vca26, vw1c0, and vw1c6 sfr bits vca13, vca27, vw2c2, vw2c3, vw1c1, vw1f0, vw1f1, and vw1c7 pin, cpu, and sfr bits other than those listed above vcc hardware reset power-on reset watchdog timer reset software reset vca13: bit in vca1 register vca26, vca27: bits in vca2 register vw1c0, vw1c1, vw1f0, vw1f1, vw1c6, vw1c7: bits in vw1c register vw2c2, vw2c3: bits in vw2c register voltage monitor 2 reset r8c/26 group, r8c/27 group 5. resets rev.2.10 sep 26, 2008 page 26 of 453 rej09b0278-0210 table 5.2 shows the pin functions while reset pin level is ?l?, figure 5.3 sh ows the cpu register status after reset, figure 5.4 shows the reset sequence, and figure 5.5 shows the ofs register. figure 5.3 cpu register status after reset figure 5.4 reset sequence table 5.2 pin functions while reset pin level is ?l? pin name pin functions p0, p1 input port p3_1, p3_3 to p3_7 input port p4_2, p4_5 to p4_7 input port p5_3, p5_4 input port b19 b0 interrupt table register(intb) program counter(pc) user stack pointer(usp) interrupt stack pointer(isp) static base register(sb) content of addresses 0fffeh to 0fffch flag register(flg) c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 b15 b0 0000h 0000h 0000h 0000h 0000h 0000h 0000h data register(r0) data register(r1) data register(r2) data register(r3) address register(a0) address register(a1) frame base register(fb) 00000h 0000h 0000h 0000h 0000h start time of flash memory (cpu clock 14 cycles) 0fffch 0fffeh 0fffdh content of reset vector cpu clock address (internal address signal) notes: 1. hardware reset. 2. when the ?l? input width to the reset pin is set to foco-s clock 32 cycles or more, setting the reset pin to ?h? also sets the internal reset signal to ?h? at the same. cpu clock 28 cycles foco-s clock 32 cycles (2) foco-s internal reset signal reset pin 10 cycles or more are needed (1) r8c/26 group, r8c/27 group 5. resets rev.2.10 sep 26, 2008 page 27 of 453 rej09b0278-0210 figure 5.5 ofs register option function select register (1) symbol address when shipping ofs 0ffffh ffh (3) bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. csproini count source protect mode after reset select bit 0 : count source protect mode enabled after reset 1 : count source protect mode disabled after reset rw lvd1on voltage detection 1 circuit start bit (5, 6) 0 : voltage monitor 1 reset enabled after hardw are reset 1 : voltage monitor 1 reset disabled after hardw are reset rw romcp1 rom code protect bit 0 : rom code protect enabled 1 : rom code protect disabled rw romcr rom code protect disabled bit 0 : rom code protect disabled 1 : romcp1 enabled rw ? (b1) rw reserved bit set to 1. wdton rw watchdog timer start select bit 0 : starts w atchdog timer automatically after reset 1 : watchdog timer is inactive after reset 1 1 b7 b6 b5 b4 b3 b2 b1 b0 ? (b4) reserved bit set to 1. rw lvd0on voltage detection 0 circuit start bit (2, 4) 0 : voltage monitor 0 reset enabled after hardw are reset 1 : voltage monitor 0 reset disabled after hardw are reset rw for n, d version only. for j, k version, set the lvd0on bit to 1 (voltage monitor 0 reset disabled after hardw are reset). the lvd1on bit setting is valid only by a hardw are reset. when the pow er-on reset function is used, set the lvd1on bit to 0 (voltage monitor 1 reset enabled after hardw are reset). for j, k version only. for n, d version, set the lvd1on bit to 1 (voltage monitor 1 reset disabled after hardw are reset). the ofs register is on the flash memory. write to the ofs register w ith a program. after w riting is completed, do not w rite additions to the ofs register. if the block including the ofs register is erased, ffh is set to the ofs register. the lvd0on bit setting is valid only by a hardw are reset. to use the pow er-on reset, set the lvd0on bit to 0 (voltage monitor 0 reset enabled after hardw are reset). r8c/26 group, r8c/27 group 5. resets rev.2.10 sep 26, 2008 page 28 of 453 rej09b0278-0210 5.1 hardware reset a reset is applied using the reset pin. when an ?l? signal is applied to the reset pin while the supply voltage meets the recommended operating conditions, pins, cpu, and sf rs are all reset (refer to table 5.2 pin functions while reset pin level is ?l? ). when the input level applied to the reset pin changes from ?l? to ?h?, a program is executed beginning with the address indicated by the reset vector. after reset, the low-speed on-chip oscillator clock divided by 8 is automa tically selected as the cpu clock. refer to 4. special function registers (sfrs) for the state of the sfrs after reset. the internal ram is not reset. if the reset pin is pulled ?l? while writing to the internal ram is in progress, the contents of internal ram will be undefined. figure 5.6 shows an example of hardware reset circuit and operation and figure 5.7 shows an example of hardware reset circuit (usage example of external supply voltage detectio n circuit) and operation. 5.1.1 when power supply is stable (1) apply ?l? to the reset pin. (2) wait for 10 s or more. (3) apply ?h? to the reset pin. 5.1.2 power on (1) apply ?l? to the reset pin. (2) let the supply voltage increase until it meets the recommended operating conditions. (3) wait for td(p-r) or more to allow the in ternal power supply to stabilize (refer to 20. electrical characteristics ). (4) wait for 10 s or more. (5) apply ?h? to the reset pin. r8c/26 group, r8c/27 group 5. resets rev.2.10 sep 26, 2008 page 29 of 453 rej09b0278-0210 figure 5.6 example of hardware reset circuit and operation figure 5.7 example of hardware reset circuit (usage example of external supply voltage detection circuit) and operation reset vcc vcc reset 2.2 v (2.7 v for j, k version) 0 v 0.2 vcc or below td(p-r) + 10 s or more 0 v note: 1. refer to 20. electrical characteristics . reset vcc vcc reset 0 v td(p-r) + 10 s or more 0 v 5 v 5 v example when vcc = 5 v supply voltage detection circuit note: 1. refer to 20. electrical characteristics . 2.2 v (2.7 v for j, k version) r8c/26 group, r8c/27 group 5. resets rev.2.10 sep 26, 2008 page 30 of 453 rej09b0278-0210 5.2 power-on reset function when the reset pin is connected to the vcc pin via a pull-up resistor, and the vcc pin voltage level rises while the rise gradient is trth or more, the power-on reset func tion is enabled and the mcu resets its pins, cpu, and sfr. when a capacitor is connected to the reset pin, too, always keep the voltage to the reset pin 0.8vcc or more. when the input voltage to the vcc pin reaches thevdet0 (v det1 for j, k version) level or above, the low-speed on- chip oscillator clock starts counting. when the low-spee d on-chip oscillator clock count reaches 32, the internal reset signal is held ?h? and the mc u enters the reset sequence (refer to figure 5.4 ). the low-speed on-chip oscillator clock divided by 8 is automatically selected as the cpu clock after reset. refer to 4. special function registers (sfrs) for the states of the sfr after power-on reset. the voltage monitor 0 reset is enabled after power-on reset. figure 5.8 and figure 5.9 shows the example of power-on reset circuit and operation. figure 5.8 example of power-on reset circuit and operation (n, d version) reset vcc notes: 1. when using the voltage monitor 0 digital filter, ensure that the voltage is within the mcu operation voltage range (2.2 v or above) during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit for details. 3. vdet0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit for details. 4. refer to 20. electrical characteristics . 5. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvd0on bit in the ofs register to 0, the vw0c0 and vw0c6 bits in the vw0c register to 1 respectively, and the vca25 bit in the vca2 register to 1. v det0 (3) v por1 internal reset signal (?l? valid) t w(por1) sampling time (1, 2) v det0 (3) 1 f oco-s 32 1 f oco-s 32 v por2 2.2 v external power v cc t rth t rth 4.7 k ? (reference) r8c/26 group, r8c/27 group 5. resets rev.2.10 sep 26, 2008 page 31 of 453 rej09b0278-0210 figure 5.9 example of power-on reset circuit and operation (j, k version) reset vcc 4.7 k ? (reference) notes: 1. when using the voltage monitor 1 digital filter, ensure vcc is 2.0 v or higher during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit for details. 3. vdet1 indicates the voltage detection level of the voltage detection 1 circuit. refer to 6. voltage detection circuit for details. 4. refer to 20. electrical characteristics . 5. to use the power-on reset function, enable voltage monitor 1 reset by setting the lvd1on bit in the ofs register to 0, the vw1c0 and vw1c6 bits in the vw1c register to 1 respectively, and the vca26 bit in the vca2 register to 1. v det1 (3) v por1 internal reset signal (?l? valid) t w(por1) v det1 (3) v por2 32 1 f oco-s 32 1 f oco-s 2.0 v t rth t rth external power v cc sampling time (1, 2) t d(vdet1-a) r8c/26 group, r8c/27 group 5. resets rev.2.10 sep 26, 2008 page 32 of 453 rej09b0278-0210 5.3 voltage monitor 0 reset (n, d version) a reset is applied using the on-chip voltage detection 0 ci rcuit. the voltage detection 0 circuit monitors the input voltage to the vcc pin. the voltage to monitor is vdet0. when the input voltage to the vcc pin reaches the vdet0 level or below, the pins, cpu, and sfr are reset. when the input voltage to the vcc pin reaches the vdet0 level or above, th e low-speed on-chip oscillator clock start counting. when the low-speed on-chip osci llator clock count reaches 32, the in ternal reset signal is held ?h? and the mcu enters the reset sequence (refer to figure 5.4 ). the low-speed on-chip oscillator clock divided by 8 is automatically selected as the cpu clock after reset. the lvd0on bit in the ofs register can be used to enable or disable voltage monitor 0 reset after a hardware reset. setting the lvd0on bit is only valid after a hardware reset. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvd0on bit in the ofs register to 0, the vw0c0 and vw0c6 bits in the vw0c register to 1 respectively, and the vca25 bit in the vca2 register to 1. the lvd0on bit cannot be changed by a program. to set the lvd0on bit, write 0 (voltage monitor 0 reset enabled after hardware reset) or 1 (voltage monitor 0 reset disabled after hardware reset) to bit 5 of address 0ffffh using a flash programmer. refer to figure 5.5 ofs register for details of the ofs register. refer to 4. special function registers (sfrs) for the status of the sfr after voltage monitor 0 reset. the internal ram is not reset. when the input voltage to the vcc pin reaches the vdet0 level or below while writing to the internal ram is in progress, the contents of internal ram are undefined. refer to 6. voltage detection circuit for details of voltage monitor 0 reset. 5.4 voltage monitor 1 reset (n, d version) a reset is applied using the on-chip voltage detection 1 ci rcuit. the voltage detection 1 circuit monitors the input voltage to the vcc pin. the voltage to monitor is vdet1. when the input voltage to the vcc pin drops the vdet1 level or below, the pins, cpu, and sfr are reset and a program is executed beginning with the address indicated by the rese t vector. after reset, the low-speed on-chip oscillator clock divided by 8 is automatical ly selected as the cpu clock. the voltage monitor 1 does not reset so me portions of the sfr. refer to 4. special function registers (sfrs) for details. the internal ram is not reset. when the input voltage to the vcc pin reaches the vdet1 level or below while writing to the internal ram is in progress, the contents of internal ram are undefined. refer to 6. voltage detection circuit for details of voltage monitor 1 reset. 5.5 voltage monitor 1 reset (j, k version) a reset is applied using the on-chip voltage detection 1 ci rcuit. the voltage detection 1 circuit monitors the input voltage to the vcc pin. the voltage to monitor is vdet1. when the input voltage to the vcc pin reaches the vdet1 level or below, the pins, cpu, and sfr are reset. when the input voltage to the vcc pin reaches the vdet1 level or above, th e low-speed on-chip oscillator clock start counting. when the low-speed on-chip osci llator clock count reaches 32, the in ternal reset signal is held ?h? and the mcu enters the reset sequence (refer to figure 5.4 ). the low-speed on-chip oscillator clock divided by 8 is automatically selected as the cpu clock after reset. the lvd1on bit in the ofs register can be used to enable or disable voltage monitor 1 reset. setting the lvd1on bit is only valid after a hardware reset. to use the power-on reset function, enable voltage monitor 1 reset by setting the lvd1on bit in the ofs register to 0, the vw1c0 and vw1c6 bits in the vw1c register to 1 respectively, and the vca26 bit in the vca2 register to 1. the lvd1on bit cannot be changed by a program. to set the lvd1on bit, write 0 (voltage monitor 1 reset enabled after hardware reset) or 1 (voltage monitor 1 reset disabled after hardware reset) to bit 6 of address 0ffffh using a flash programmer. refer to figure 5.5 ofs register for details of the ofs register. refer to 4. special function registers (sfrs) for the status of the sfr after voltage monitor 1 reset. the internal ram is not reset. when the input voltage to the vcc pin reaches the vdet1 level or below while writing to the internal ram is in progress, the contents of internal ram are undefined. refer to 6. voltage detection circuit for details of voltage monitor 1 reset. r8c/26 group, r8c/27 group 5. resets rev.2.10 sep 26, 2008 page 33 of 453 rej09b0278-0210 5.6 voltage monitor 2 reset a reset is applied using the on-chip voltage detection 2 ci rcuit. the voltage detection 2 circuit monitors the input voltage to the vcc pin. the voltage monitored is vdet2. when the input voltage to the vcc pin drops the vdet2 le vel or below, the pins, cpu, and sfr are reset and the program beginning with the address indicated by the reset vector is executed. after reset, the low-speed on-chip oscillator clock divided by 8 is automa tically selected as the cpu clock. the voltage monitor 2 does not reset some sfrs. refer to 4. special function registers (sfrs) for details. the internal ram is not reset. when the input voltage to the vcc pin reaches the vdet2 level or below while writing to the internal ram is in progress, the contents of internal ram are undefined. refer to 6. voltage detection circuit for details of voltage monitor 2 reset. 5.7 watchdog timer reset when the pm12 bit in the pm1 register is set to 1 (reset when watchdog timer underflows), the mcu resets its pins, cpu, and sfr if the watchdog timer underflows. then the program beginning with the address indicated by the reset vector is executed. after reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the cpu clock. the watchdog timer reset does not reset some sfrs. refer to 4. special function registers (sfrs) for details. the internal ram is not reset. when the watchdog timer underflows, the contents of internal ram are undefined. refer to 13. watchdog timer for details of the watchdog timer. 5.8 software reset when the pm03 bit in the pm0 register is set to 1 (mcu reset), the mcu resets its pins, cpu, and sfr. the program beginning with the address indicated by the reset vector is executed. after reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the cpu clock. the software reset does not reset some sfrs. refer to 4. special function registers (sfrs) for details. the internal ram is not reset. r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 34 of 453 rej09b0278-0210 6. voltage detection circuit the voltage detection circuit monitors th e input voltage to the vcc pin. this circuit can be used to monitor the vcc input voltage by a program. alternately, voltage monitor 0 re set (for n, d version only), voltage monitor 1 interrupt (for n, d version only), voltage monitor 1 reset, voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used. table 6.1 lists the specifications of vo ltage detection circuit (n, d version) an d table 6.2 lists th e specifications of voltage detection circuit (j, k version). figures 6.1 to 6.6 show the block diagrams. figures 6.7 to 6.12 show the associated registers. table 6.1 specifications of voltage detection circuit (n, d version) item voltage detection 0 voltage detection 1 voltage detection 2 vcc monitor voltage to monitor vdet0 vdet1 vdet2 detection target whether passing through vdet0 by rising or falling passing through vdet1 by rising or falling passing through vdet2 by rising or falling monitor none vw1c3 bit in vw1c register vca13 bit in vca1 register whether vcc is higher or lower than vdet1 whether vcc is higher or lower than vdet2 process when voltage is detected reset voltage monitor 0 reset voltage monitor 1 reset voltage monitor 2 reset reset at vdet0 > vcc; restart cpu operation at vcc > vdet0 reset at vdet1 > vcc; restart cpu operation after a specified time reset at vdet2 > vcc; restart cpu operation after a specified time interrupt none voltage monitor 1 interrupt voltage monitor 2 interrupt interrupt request at vdet1 > vcc and vcc > vdet1 when digital filter is enabled; interrupt request at vdet1 > vcc or vcc > vdet1 when digital filter is disabled interrupt request at vdet2 > vcc and vcc > vdet2 when digital filter is enabled; interrupt request at vdet2 > vcc or vcc > vdet2 when digital filter is disabled digital filter switch enabled/disabled available available available sampling time (divide-by-n of foco-s) 4 n: 1, 2, 4, and 8 (divide-by-n of foco-s) 4 n: 1, 2, 4, and 8 (divide-by-n of foco-s) 4 n: 1, 2, 4, and 8 r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 35 of 453 rej09b0278-0210 figure 6.1 block diagram of voltage detection circuit (n, d version) table 6.2 specifications of voltage detection circuit (j, k version) item voltage detection 1 voltage detection 2 vcc monitor voltage to monitor vdet1 vdet2 detection target whether passing through vdet1 by rising or falling passing through vdet2 by rising or falling monitor none vca13 bit in vca1 register whether vcc is higher or lower than vdet2 process when voltage is detected reset voltage monitor 1 rese t voltage monitor 2 reset reset at vdet1 > vcc; restart cpu operation at vcc > vdet1 reset at vdet2 > vcc; restart cpu operation after a specified time interrupt none voltage monitor 2 interrupt interrupt request at vdet2 > vcc and vcc > vdet2 when digital filter is enabled; interrupt request at vdet2 > vcc or vcc > vdet2 when digital filter is disabled digital filter switch enabled/disabled available available sampling time (divide-by-n of foco-s) 4 n: 1, 2, 4, and 8 (divide-by-n of foco-s) 4 n: 1, 2, 4, and 8 vdet2 vca27 + - vcc b3 vca13 bit vca1 register voltage detection 2 signal voltage detection 1 signal internal reference voltage vca26 + - vdet1 vca25 + - vdet0 voltage detection 0 signal b3 vw1c3 bit vw1c register noise filter noise filter r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 36 of 453 rej09b0278-0210 figure 6.2 block diagram of voltage detection circuit (j, k version) figure 6.3 block diagram of voltage monitor 0 re set generation circuit (for n, d version only) vdet2 vca27 + - vcc b3 vca13 bit vca1 register voltage detection 2 signal voltage detection 1 signal internal reference voltage vca26 + - vdet1 noise filter noise filter + - 1/2 1/2 1/2 voltage detection 0 circuit vca25 vcc internal reference voltage voltage detection 0 signal is held ?h? when vca25 bit is set to 0 (disabled) voltage detection 0 signal foco-s vw0f1 to vw0f0 = 00b = 01b = 10b = 11b vw0c7 voltage monitor 0 reset signal voltage monitor 0 reset generation circuit vw0c0 to vw0c1, vw0f0 to vw0f1, vw0c6, vw0c7: bits in vw0c register vca25: bit in vca2 register vw0c0 vw0c6 vw0c1 vw0c1 digital filter r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 37 of 453 rej09b0278-0210 figure 6.4 block diagram of voltage monitor 1 in terrupt/reset generation circuit (n, d version) figure 6.5 block diagram of voltage monitor 1 reset generation circuit (j, k version) + - 1/2 1/2 1/2 voltage detection 1 circuit vca26 vcc internal reference voltage vw1c3 noise filter (filter width: 200 ns) voltage detection 1 signal is held ?h? when vca26 bit is set to 0 (disabled) voltage detection 1 signal digital filter foco-s vw1f1 to vw1f0 = 00b = 01b = 10b = 11b vw1c2 bit is set to 0 (not detected) by writing 0 by a program. when vca26 bit is set to 0 (voltage detection 1 circuit disabled), vw1c2 bit is set to 0 voltage monitor 1 interrup t/reset generation circuit vw1c0 to vw1c3, vw1f0, vw1f1, vw1c6, vw1c7: bits in vw1c register vca26: bit in vca2 register vw1c1 vw1c1 vw1c2 vw1c7 vw1c0 vw1c6 non-maskable interrupt signal voltage monitor 1 interrupt signal watchdog timer interrupt signal oscillation stop detection interrupt signal voltage monitor 1 reset signal + - 1/2 1/2 1/2 voltage detection 1 circuit vca26 vcc internal reference voltage vw1c3 noise filter (filter width: 200 ns) voltage detection 1 signal is held ?h? when vca26 bit is set to 0 (disabled) voltage detection 1 signal digital filter foco-s vw1f1 to vw1f0 = 00b = 01b = 10b = 11b vw1c2 bit is set to 0 (not detected) by writing 0 by a program. when vca26 bit is set to 0 (voltage detection 1 circuit disabled), vw1c2 bit is set to 0 voltage monitor 1 interrupt/reset generation circuit vw1c0 to vw1c3, vw1f0, vw1f1, vw1c6, vw1c7: bits in vw1c register vca26: bit in vca2 register vw1c1 vw1c1 vw1c2 vw1c7 vw1c0 vw1c6 voltage monitor 1 reset signal r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 38 of 453 rej09b0278-0210 figure 6.6 block diagram of voltage monitor 2 interrupt/reset generation circuit + - 1/2 1/2 1/2 voltage detection 2 circuit vca27 vcc internal reference voltage vca13 noise filter (filter width: 200 ns) voltage detection 2 signal is held ?h? when vca27 bit is set to 0 (disabled) voltage detection 2 signal digital filter foco-s vw2f1 to vw2f0 = 00b = 01b = 10b = 11b vw2c2 bit is set to 0 (not detected) by writing 0 by a program. when vca27 bit is set to 0 (voltage detection 2 circuit disabled), vw2c2 bit is set to 0 vw2c3 watchdog timer block watchdog timer underflow signal this bit is set to 0 (not detected) by writing 0 by a program. voltage monitor 2 interrupt/reset generation circuit vw2c0 to vw2c3, vw2f0, vw2f1, vw2c6, vw2c7: bits in vw2c register vca13: bit in vca1 register vca27: bit in vca2 register vw2c1 vw2c1 vw2c2 vw2c7 vw2c0 vw2c6 non-maskable interrupt signal voltage monitor 2 interrupt signal watchdog timer interrupt signal oscillation stop detection interrupt signal voltage monitor 2 reset signal r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 39 of 453 rej09b0278-0210 figure 6.7 registers vca1 and vca2 (n, d version) voltage detection register 1 symbol address after reset (2) vca1 0031h 00001000b bit symbol bit name function rw notes: 1. 2. the vca13 bit is enabled w hen the vca27 bit in the vca2 register is set to 1 (voltage detection 2 circuit enabled). the vca13 bit is set to 1 (vcc vdet 2) w hen the vca27 bit in the vca2 register is set to 0 (voltage detection 2 circuit disabled). ? (b7-b4) reserved bits set to 0. rw set to 0. 0 b7 b6 b5 b4 b3 b2 b1 b0 0000 the softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. vca13 voltage detection 2 signal monitor flag (1) 00 ? (b2-b0) rw 0 : vcc < vdet2 1 : vcc vdet2 or voltage detection 2 circuit disabled ro reserved bits voltage detection register 2 (1) (n, d version) symbol address after reset (5) vca2 0032h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. use the vca20 bit only w hen entering to w ait mode. to set the vca20 bit, follow the procedure show n in figu r e 10.10 procedure for enabling reduced internal pow er consum ption using vca20 bit . vca20 internal pow er low consumption enable bit (6) 0 : disables low consumption 1 : enables low consumption rw set the prc3 bit in the prcr register to 1 (w rite enable) before w riting to the vca2 register. to use the voltage monitor 1 interrupt/reset or the vw1c3 bit in the vw1c register, set the vca26 bit to 1. after the vca26 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. to use the voltage monitor 2 interrupt/reset or the vca13 bit in the vca1 register, set the vca27 bit to 1. after the vca27 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. to use the voltage monitor 0 reset, set the vca25 bit to 1. after the vca25 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. vca27 voltage detection 2 enable bit (4) 0 : voltage detection 2 circuit disabled 1 : voltage detection 2 circuit enabled rw vca26 voltage detection 1 enable bit (3) 0 : voltage detection 1 circuit disabled 1 : voltage detection 1 circuit enabled rw 000 0 b3 b2 b1 b0 b7 b6 b5 b4 the lvd0on bit in the ofs register is set to 1 and hardw are reset : 00h pow er-on reset, voltage monitor 0 reset or lvd0on bit in the ofs register is set to 0, and hardw are reset : 00100000b vca25 voltage detection 0 enable bit (2) 0 : voltage detection 0 circuit disabled 1 : voltage detection 0 circuit enabled rw ? (b4-b1) reserved bits set to 0. rw r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 40 of 453 rej09b0278-0210 figure 6.8 vca2 register (j, k version) voltage detection register 2 (1) (j, k version) symbol address after reset (4) vca2 0032h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. the lvd1on bit in the ofs register is set to 1 and hardw are reset : 00h pow er-on reset, voltage monitor 1 reset or lvd1on bit in the ofs register is set to 0, and hardw are reset : 0100000b ? (b5-b1) reserved bits set to 0. rw b7 b6 b5 b4 b3 b2 b1 b0 00000 voltage detection 2 enable bit (3) 0 : voltage detection 2 circuit disabled 1 : voltage detection 2 circuit enabled rw vca26 voltage detection 1 enable bit (2) 0 : voltage detection 1 circuit disabled 1 : voltage detection 1 circuit enabled rw use the vca20 bit only w hen entering to w ait mode. to set the vca20 bit, follow the procedure show n in figu r e 10.10 procedure for enabling reduced internal pow er consum ption using vca20 bit . vca20 internal pow er low consumption enable bit (5) 0 : disables low consumption 1 : enables low consumption rw set the prc3 bit in the prcr register to 1 (w rite enable) before w riting to the vca2 register. to use the voltage monitor 1 reset, set the vca26 bit to 1. after the vca26 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. to use the voltage monitor 2 interrupt/reset or the vca13 bit in the vca1 register, set the vca27 bit to 1. after the vca27 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. softw are reset, w atchdog timer reset, or voltage monitor 2 reset do not affect this register. vca27 r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 41 of 453 rej09b0278-0210 figure 6.9 vw0c register (for n, d version only) voltage monitor 0 circuit control register (1) symbol address vw0c 0038h bit symbol bit name function rw notes: 1. 2. 3. 4. the vw0c7 bit is enabled w hen the vw0c1 bit set to 1 (digital filter disabled mode). b3 b2 set to 0. rw b1 b0 0 b7 b6 b5 b4 vw0c0 rw voltage monitor 0 reset enable bit (3) 0 : disable 1 : enable vw0c2 res er v ed bit vw0c1 voltage monitor 0 digital filter disable mode select bit when read, the content is undefined. ro 0 : digital filter enabled mode (digital filter circuit enabled) 1 : digital filter disabled mode (digital filter circuit disabled) rw vw0f1 rw sampling clock select bits b5 b4 0 0 : foco-s divided by 1 0 1 : foco-s divided by 2 1 0 : foco-s divided by 4 1 1 : foco-s divided by 8 vw0f0 rw the vw0c0 bit is enabled w hen the vca25 bit in the vca2 register is set to 1 (voltage detection 0 circuit enabled). set the vw0c0 bit to 0 (disable), w hen the vca25 bit is set to 0 (voltage detection 0 circuit disabled). vw0c7 voltage monitor 0 reset generation condition select bit (4) when the vw0c1 bit is set to 1 (digital filter disabled mode), set to 1. rw the lvd0on bit in the ofs register is set to 1 and hardw are reset : 0000x000b pow er-on reset, voltage monitor 0 reset or lvd0on bit in the ofs register is set to 0, and hardw are reset : 0100x001b after reset (2) set the prc3 bit in the prcr register to 1 (w rite enable) before w riting to the vw0c register. the value remains unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset. vw0c6 voltage monitor 0 circuit mode select bit when the vw0c0 bit is set to 1 (voltage monitor 0 reset enabled), set to 1. rw ? (b3) res er v ed bit r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 42 of 453 rej09b0278-0210 figure 6.10 vw1c register (n, d version) volta g e monitor 1 circuit control re g iste r (1) ( n, d version ) symbol address after reset (8) vw1c 0036h 00001000b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. b2 0 : not detected 1 : vdet1 pass detected rw b1 b0 b3 b7 b6 b5 b4 vw1c0 rw voltage monitor 1 interrupt/reset enable bit (6) 0 : disable 1 : enable 0 : digital filter enabled mode (digital filter circuit enabled) 1 : digital filter disabled mode (digital filter circuit disabled) rw vw1c2 voltage change detection flag (3, 4, 8) vw1c1 voltage monitor 1 digital filter disable mode select bit (2) vw1c3 voltage detection 1 signal monitor flag (3, 8) vw1f1 rw sampling clock select bits b5 b4 0 0 : foco-s divided by 1 0 1 : foco-s divided by 2 1 0 : foco-s divided by 4 1 1 : foco-s divided by 8 vw1f0 rw 0 : v cc < v det1 1 : v cc vdet1 or voltage detection 1 circuit disabled ro vw1c6 voltage monitor 1 circuit mode select bit (5) 0 : voltage monitor 1 interrupt mode 1 : voltage monitor 1 reset mode rw vw1c7 voltage monitor 1 interrupt/reset generation condition select bit (7,9) 0 : when vcc reaches vdet1 or above 1 : when vcc reaches vdet1 or below rw when the vw1c6 bit is set to 1 (voltage monitor 1 reset mode), set the vw1c7 bit to 1 (w hen vcc reaches vdet1 or below ). (do not set to 0.) set the prc3 bit in the prcr register to 1 (rew rite enable) before w riting to the vw1c register. to use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the vw1c1 bit before w riting 1. bits vw1c2 and vw1c3 are enabled w hen the vca26 bit in the vca2 register is set to 1 (voltage detection 1 circuit enabled). set this bit to 0 by a program. when 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is w ritten to it). the vw1c6 bit is enabled w hen the vw1c0 bit is set to 1 (voltage monitor 1 interrupt/enabled reset). the vw1c0 bit is enabled w hen the vca26 bit in the vca2 register is set to 1 (voltage detection 1 circuit enabled). set the vw1c0 bit to 0 (disable) w hen the vca26 bit is set to 0 (voltage detection 1 circuit disabled). the vw1c7 bit is enabled w hen the vw1c1 bit is set to 1 (digital filter disabled mode). bits vw1c2 and vw1c3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset. r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 43 of 453 rej09b0278-0210 figure 6.11 vw1c register (j, k version) voltage monitor 1 circuit control register (1) (j, k version) symbol address after reset (6) vw1c 0036h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. the lvd1on bit in the ofs register is set to 1 and hardw are reset : 0000x000b pow er-on reset, voltage monitor 1 reset or lvd1on bit in the ofs register is set to 0, and hardw are reset : 0100x001b b2 set to 0. rw b1 b0 0 b3 b7 b6 b5 b4 vw1c0 rw voltage monitor 1 reset enable bit (4) 0 : disable 1 : enable 0 : digital filter enabled mode (digital filter circuit enabled) 1 : digital filter disabled mode (digital filter circuit disabled) rw ? (b2) reserved bit vw1c1 voltage monitor 1 digital filter disable mode select bit (2) ? (b3) reserved bit vw1f1 rw sampling clock select bits b5 b4 0 0 : foco-s divided by 1 0 1 : foco-s divided by 2 1 0 : foco-s divided by 4 1 1 : foco-s divided by 8 vw1f0 rw when read, the content is undefined. ro vw1c6 voltage monitor 1 circuit mode select bit (3) when the vw1c0 bit is 1(voltage monitor 1 reset enabled), set to 1. rw vw1c7 voltage monitor 1 reset generation condition select bit (5, 7) when the vw1c1 bit is 1(digital filter disabled mode), set to 1. rw when the vw1c6 bit is set to 1 (voltage monitor 1 reset mode), set the vw1c7 bit to 1 (w hen vcc reaches vdet1 or below ). (do not set to 0.) set the prc3 bit in the prcr register to 1 (rew rite enable) before w riting to the vw1c register. to use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the vw1c1 bit before w riting 1. the vw1c6 bit is enabled w hen the vw1c0 bit is set to 1 (voltage monitor 1 reset enabled). the vw1c0 bit is enabled w hen the vca26 bit in the vca2 register is set to 1 (voltage detection 1 circuit enabled). set the vw1c0 bit to 0 (disable) w hen the vca26 bit is set to 0 (voltage detection 1 circuit disabled). the vw1c7 bit is enabled w hen the vw1c1 bit is set to 1 (digital filter disabled mode). softw are reset, w atchdog timer reset, or voltage monitor 2 reset do not affect this register. r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 44 of 453 rej09b0278-0210 figure 6.12 vw2c register volta g e monitor 2 circuit control re g iste r (1) symbol address after reset (8) vw2c 0037h 00h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. b3 b2 0 : not detected 1 : vcc has crossed vdet2 rw b1 b0 b7 b6 b5 b4 vw2c0 rw voltage monitor 2 interrupt/reset enable bit (6) 0 : disable 1 : enable 0 : digital filter enabled mode (digital filter circuit enabled) 1 : digital filter disabled mode (digital filter circuit disabled) rw vw2c2 voltage change detection flag (3,4,8) vw2c1 voltage monitor 2 digital filter disable mode select bit (2) vw2c3 wdt detection flag (4,8) vw2f1 rw sampling clock select bits b5 b4 0 0 : foco-s divided by 1 0 1 : foco-s divided by 2 1 0 : foco-s divided by 4 1 1 : foco-s divided by 8 vw2f0 rw 0 : not detected 1 : detected rw vw2c6 voltage monitor 2 circuit mode select bit (5) 0 : voltage monitor 2 interrupt mode 1 : voltage monitor 2 reset mode rw vw2c7 voltage monitor 2 interrupt/reset generation condition select bit (7,9) 0 : when vcc reaches vdet2 or above 1 : when vcc reaches vdet2 or below rw when the vw2c6 bit is set to 1 (voltage monitor 2 reset mode), set the vw2c7 bit to 1 (w hen vcc reaches vdet2 or below ). (do not set to 0.) set the prc3 bit in the prcr register to 1 (w rite enable) before w riting to the vw2c register. to use the voltage monitor 2 interrupt to exit stop mode and to return again, w rite 0 to the vw2c1 bit before w riting 1. the vw2c2 bit is enabled w hen the vca27 bit in the vca2 register is set to 1 (voltage detection 2 circuit enabled). set this bit to 0 by a program. when 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is w ritten to it). the vw2c6 bit is enabled w hen the vw2c0 bit is set to 1 (voltage monitor 2 interrupt/enables reset). the vw2c0 bit is enabled w hen the vca27 bit in the vca2 register is set to 1 (voltage detection 2 circuit enabled). set the vw2c0 bit to 0 (disable) w hen the vca27 bit is set to 0 (voltage detection 2 circuit disabled). the vw2c7 bit is enabled w hen the vw2c1 bit is set to 1 (digital filter disabled mode). bits vw2c2 and vw2c3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset (for n, d version only), or voltage monitor 2 reset. r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 45 of 453 rej09b0278-0210 6.1 vcc input voltage 6.1.1 monitoring vdet0 vdet0 cannot be monitored. 6.1.2 monitoring vdet1 set the vca26 bit in the vca2 register to 1 (voltage detection 1 circuit enabled). after td(e-a) has elapsed (refer to 20. electrical characteristics ), vdet1 can be monitored by the vw1c3 bit in the vw1c register. 6.1.3 monitoring vdet2 set the vca27 bit in the vca2 register to 1 (voltage detection 2 circuit enabled). after td(e-a) has elapsed (refer to 20. electrical characteristics ), vdet2 can be monitored by the vca13 bit in the vca1 register. r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 46 of 453 rej09b0278-0210 6.2 voltage monitor 0 reset (for n, d version only) table 6.3 lists the procedure for sett ing bits associated with voltage mo nitor reset and figure 6.13 shows an example of voltage monitor 0 reset operation. to use th e voltage monitor 0 reset to exit stop mode, set the vw0c1 bit in the vw0c register to 1 (digital filter disabled). note: 1. when the vw0c0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction). figure 6.13 example of voltage monitor 0 reset operation table 6.3 procedure for setting bits associated with voltage monitor reset step when using digital filter when not using digital filter 1 set the vca25 bit in the vca2 register to 1 (voltage detection 0 circuit enabled) 2 wait for td(e-a) 3 select the sampling clock of the digital filter by the vw0f0 to vw0f1 bits in the vw0c register set the vw0c7 bit in the vw0c register to 1 4 (1) set the vw0c1 bit in the vw0c register to 0 (digital filter enabled) set the vw0c1 bit in the vw0c register to 1 (digital filter disabled) 5 (1) set the vw0c6 bit in the vw0c register to 1 (voltage monitor 0 reset mode) 6 set the vw0c2 bit in the vw0c register to 0 7 set the cm14 bit in the cm1 register to 0 (low-speed on-chip oscillator on) ? 8 wait for 4 cycles of the sampling clock of the digital filter ? (no wait time required) 9 set the vw0c0 bit in the vw0c register to 1 (voltage monitor 0 reset enabled) vdet0 internal reset signal vcc the above applies under the following conditions. ? vca25 bit in vca2 register = 1 (voltage detection 0 circuit enabled) ? vw0c0 bit in vw0c register = 1 (voltage monitor 0 reset enabled) ? vw0c6 bit in vw0c register = 1 (voltage monitor 0 reset mode) when the internal reset signal is held ?l?, the pins, cpu and sfr are reset. the internal reset signal level changes from ?l? to ?h?, and a program is executed beginning with the address indicated by the reset vector. refer to 4. special function registers (sfrs) for the sfr status after reset. 1 foco-s 32 sampling clock of digital filter 4 cycles when the vw0c1 bit is set to 0 (digital filter enabled) internal reset signal when the vw0c1 bit is set to 1 (digital filter disabled) and the vw0c7 bit is set to 1 1 foco-s 32 vw0c1 and vw0c7: bits in vw0c register r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 47 of 453 rej09b0278-0210 6.3 voltage monitor 1 interrupt and vo ltage monitor 1 reset (n, d version) table 6.4 lists the procedure for setting bits associated with voltage monitor 1 interrupt and reset. figure 6.14 shows an example of voltage monitor 1 interrupt and vo ltage monitor 1 reset operation (n, d version). to use the voltage monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the vw1c1 bit in the vw1c register to 1 (digital filter disabled). notes: 1. set the vw1c7 bit to 1 (when vcc reaches vdet1 or below) for the voltage monitor 1 reset. 2. when the vw1c0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction). table 6.4 procedure for setting bits associated with voltage monitor 1 interrupt and reset step when using digital filter when not using digital filter voltage monitor 1 interrupt voltage monitor 1 reset voltage monitor 1 interrupt voltage monitor 1 reset 1 set the vca26 bit in the vca2 register to 1 (voltage detection 1 circuit enabled) 2 wait for td(e-a) 3 select the sampling clock of the digital filter by the vw1f0 to vw1f1 bits in the vw1c register select the timing of the interrupt and reset request by the vw1c7 bit in the vw1c register (1) 4 (2) set the vw1c1 bit in the vw1c register to 0 (digital filter enabled) set the vw1c1 bit in the vw1c register to 1 (digital filter disabled) 5 (2) set the vw1c6 bit in the vw1c register to 0 (voltage monitor 1 interrupt mode) set the vw1c6 bit in the vw1c register to 1 (voltage monitor 1 reset mode) set the vw1c6 bit in the vw1c register to 0 (voltage monitor 1 interrupt mode) set the vw1c6 bit in the vw1c register to 1 (voltage monitor 1 reset mode) 6 set the vw1c2 bit in the vw1c register to 0 (passing of vdet1 is not detected) 7 set the cm14 bit in the cm1 register to 0 (low-speed on-chip oscillator on) ? 8 wait for 4 cycles of the sampling clock of the digital filter ? (no wait time required) 9 set the vw1c0 bit in the vw1c register to 1 (voltage monitor 1 interrupt/reset enabled) r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 48 of 453 rej09b0278-0210 figure 6.14 example of voltage monitor 1 interrupt and voltage monitor 1 reset operation (n, d version) vdet1 vw1c3 bit internal reset signal (vw1c6 = 1) vcc the above applies under the following conditions. ? vca26 bit in vca2 register = 1 (voltage detection 1 circuit enabled) ? vw1c0 bit in vw1c register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled) note: 1. if voltage monitor 0 reset is not used, set the power supply to vcc 2.2. 2.2 v (1) 0 1 vw1c2 bit 0 1 when the vw1c1 bit is set to 0 (digital filter enabled) vw1c2 bit 0 1 when the vw1c1 bit is set to 1 (digital filter disabled) and the vw1c7 bit is set to 0 (vdet1 or above) vw1c1, vw1c2, vw1c3, vw1c6, vw1c7: bit in vw1c register set to 0 by interrupt request acknowledgement set to 0 by a program voltage monitor 1 interrupt request (vw1c6 = 0) voltage monitor 1 interrupt request (vw1c6 = 0) vw1c2 bit 0 1 when the vw1c1 bit is set to 1 (digital filter disabled) and the vw1c7 bit is set to 1 (vdet1 or below) voltage monitor 1 interrupt request (vw1c6 = 0) internal reset signal (vw1c6 = 1) set to 0 by a program set to 0 by interrupt request acknowledgement set to 0 by a program set to 0 by interrupt request acknowledgement 4 cycles of sampling clock of digital filter 4 cycles of sampling clock of digital filter r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 49 of 453 rej09b0278-0210 6.4 voltage monitor 1 reset (j, k version) table 6.5 lists the procedure for setting bits associated with voltage monitor 1 reset. figure 6.15 shows an example of voltage monitor 1 reset operation (j, k version). to use the voltage monitor 1 reset to exit stop mode, set the vw1c1 bit in the vw1c register to 1 (digital filter disabled). note: 1. when the vw1c0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction). figure 6.15 example of voltage monitor 1 reset operation (j, k version) table 6.5 procedure for setting bits associated with voltage monitor 1 reset step when using digital filter when not using digital filter 1 set the vca26 bit in the vca2 register to 1 (voltage detection 1 circuit enabled) 2 wait for td(e-a) 3 select the sampling clock of the digital filter by the vw1f0 to vw1f1 bits in the vw1c register set the vw1c7 bit in the vw1c register to 1 4 (1) set the vw1c1 bit in the vw1c register to 0 (digital filter enabled) set the vw1c1 bit in the vw1c register to 1 (digital filter disabled) 5 (1) set the vw1c6 bit in the vw1c register to 1 (voltage monitor 1 reset mode) 6 set the vw1c2 bit in the vw1c register to 0 7 set the cm14 bit in the cm1 register to 0 (low-speed on-chip oscillator on) ? 8 wait for 4 cycles of the sampling clock of the digital filter ? (no wait time required) 9 set the vw1c0 bit in the vw1c register to 1 (voltage monitor 1 reset enabled) vdet1 internal reset signal vcc the above applies under the following conditions. ? vca26 bit in vca2 register = 1 (voltage detection 1 circuit enabled) ? vw1c0 bit in vw1c register = 1 (voltage monitor 1 reset enabled) ? vw1c6 bit in vw1c register = 1 (voltage monitor 1 reset mode) when the internal reset signal is held ?l?, the pins, cpu and sfr are reset. the internal reset signal level changes from ?l? to ?h?, and a program is executed beginning with the address indicated by the reset vector. refer to 4. special function registers (sfrs) for the sfr status after reset. 1 foco-s 32 when the vw1c1 bit is set to 0 (digital filter enabled) internal reset signal when the vw1c1 bit is set to 1 (digital filter disabled) and the vw1c7 bit is set to 1 1 foco-s 32 vw1c1 and vw1c7: bits in vw1c register sampling clock of digital filter 4 cycles r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 50 of 453 rej09b0278-0210 6.5 voltage monitor 2 interrupt and voltage monitor 2 reset table 6.6 lists the procedure for setting bits associated with voltage monitor 2 interrupt and reset. figure 6.16 shows an example of voltage monitor 2 interrupt and voltage monitor 2 reset operation. to use the voltage monitor 2 interrupt or voltage monitor 2 reset to exit st op mode, set the vw2c1 bit in the vw2c register to 1 (digital filter disabled). notes: 1. set the vw2c7 bit to 1 (when vcc reaches vdet2 or below) for the voltage monitor 2 reset. 2. when the vw2c0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction). table 6.6 procedure for setting bits associated with voltage monitor 2 interrupt and reset step when using digital filter when not using digital filter voltage monitor 2 interrupt voltage monitor 2 reset voltage monitor 2 interrupt voltage monitor 2 reset 1 set the vca27 bit in the vca2 register to 1 (voltage detection 2 circuit enabled) 2 wait for td(e-a) 3 select the sampling clock of the digital filter by the vw2f0 to vw2f1 bits in the vw2c register select the timing of the interrupt and reset request by the vw2c7 bit in the vw2c register (1) 4 set the vw2c1 bit in the vw2c register to 0 (digital filter enabled) set the vw2c1 bit in the vw2c register to 1 (digital filter disabled) 5 (2) set the vw2c6 bit in the vw2c register to 0 (voltage monitor 2 interrupt mode) set the vw2c6 bit in the vw2c register to 1 (voltage monitor 2 reset mode) set the vw2c6 bit in the vw2c register to 0 (voltage monitor 2 interrupt mode) set the vw2c6 bit in the vw2c register to 1 (voltage monitor 2 reset mode) 6 set the vw2c2 bit in the vw2c register to 0 (passing of vdet2 is not detected) 7 set the cm14 bit in the cm1 register to 0 (low-speed on-chip oscillator on) ? 8 wait for 4 cycles of the sampling clock of the digital filter ? (no wait time required) 9 set the vw2c0 bit in the vw2c register to 1 (voltage monitor 2 interrupt/reset enabled) r8c/26 group, r8c/27 group 6 . voltage detection circuit rev.2.10 sep 26, 2008 page 51 of 453 rej09b0278-0210 figure 6.16 example of voltage monitor 2 interrupt and voltage monitor 2 reset operation vdet2 vca13 bit internal reset signal (vw2c6 = 1) vcc the above applies under the following conditions. ? vca27 bit in vca2 register = 1 (voltage detection 2 circuit enabled) ? vw2c0 bit in vw2c register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled) note: 1. when voltage monitor 0 reset is not used, set the power supply to vcc 2.2. 2.2 v (1) 0 1 vw2c2 bit 0 1 when the vw2c1 bit is set to 0 (digital filter enabled) vw2c2 bit 0 1 when the vw2c1 bit is set to 1 (digital filter disabled) and the vw2c7 bit is set to 0 (vdet2 or above) vca13: bit in vca1 register vw2c1, vw2c2, vw2c6, vw2c 7: bits in vw2c register set to 0 by interrupt request acknowledgement set to 0 by a program voltage monitor 2 interrupt request (vw2c6 = 0) voltage monitor 2 interrupt request (vw2c6 = 0) vw2c2 bit 0 1 when the vw2c1 bit is set to 1 (digital filter disabled) and the vw2c7 bit is set to 1 (vdet2 or below) voltage monitor 2 interrupt request (vw2c6 = 0) internal reset signal (vw2c6 = 1) set to 0 by a program set to 0 by interrupt request acknowledgement set to 0 by a program set to 0 by interrupt request acknowledgement 4 cycles of sampling clock of digital filter 4 cycles of sampling clock of digital filter r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 52 of 453 rej09b0278-0210 7. programmable i/o ports there are 25 programmable input/output ports (i/o ports) p0, p1, p3_1, p3_3 to p3_7, p4_5, p5_3, and p5_4. also, p4_6 and p4_7 can be used as input-onl y ports if the xin clock oscillation circuit and xcin clock oscillation circuit (1) is not used, and the p4_2 can be used as an input-only port if the a/d converter is not used. table 7.1 lists an overview of programmable i/o ports. note: 1. the xcin clock oscillation circuit cannot be used for j, k version. notes: 1. in input mode, whether an internal pull-up resistor is connected or not can be selected by registers pur0 and pur1. 2. when the a/d converter is not used, this port can be used as the input-only port. 3. when the xin clock oscillation circuit and xcin clock oscillation circuit (for n, d version only) is not used, these ports can be used as the input-only ports. 7.1 functions of progr ammable i/o ports the pdi_j (j = 0 to 7) bit in the pdi (i = 0, 1, 3 to 5) re gister controls i/o of the ports p0, p1, p3_1, p3_3 to p3_7, p4_5, p5_3, and p5_4. the pi register co nsists of a port latch to hold output data and a circuit to read pin states. figures 7.1 to 7.6 show the configurations of progr ammable i/o ports. table 7.2 lists the functions of programmable i/o ports. also, figure 7.8 shows the pdi (i = 0, 1, and 3 to 5) register. figure 7.9 shows the pi (i = 0, 1, and 3 to 5) register, figure 7.10 shows register s pinsr1, pinsr2, and pinsr3, figure 7.11 shows the pmr register, figure 7.12 shows registers pur0 and pur1, and figure 7.13 shows the p1drr register. i = 0, 1, 3 to 5, j = 0 to 7 note: 1. nothing is assigned to bits pd3_0, pd 3_2, pd4_0 to pd4_4, pd4_6, and pd4_7. table 7.1 overview of programmable i/o ports ports i/o type of output i/o se tting internal pull-up resister p0, p1 i/o cmos3 state set per bit set every 4 bits (1) p3_1, p3_3 to p3_7 i/o cmos3 state set per bit set every 2 bits, 4 bits (1) p4_5 i/o cmos3 state set per bit set every bit (1) p5_3, p5_4 i/o cmos3 state set per bit set every bit (1) p4_2 (2) p4_6, p4_7 (3) i (no output function) none none table 7.2 functions of programmable i/o ports operation when accessing pi register value of pdi_j bit in pdi register (1) when pdi_j bit is set to 0 (input mode) w hen pdi_j bit is set to 1 (output mode) reading read pin input level read the port latch writing write to the port latch write to the port latch. the value written to the port latch is output from the pin. r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 53 of 453 rej09b0278-0210 7.2 effect on peripheral functions programmable i/o ports function as i/o po rts for peripheral functions (refer to table 1.6 pin name information by pin number ). table 7.3 lists the setting of pdi_j bit when functioning as i/ o ports for peripheral functions (i = 0, 1, 3 to 5, j = 0 to 7). refer to the description of each function for information on how to set peripheral functions. 7.3 pins other than programmable i/o ports figure 7.7 shows the configuration of i/o pins. table 7.3 setting of pdi_j bit when functioning as i/o ports for peripheral functions (i = 0, 1, 3 to 5, j = 0 to 7) i/o of peripheral functions pdi_j bit settings for shared pin functions input set this bit to 0 (input mode). output this bit can be set to either 0 or 1 (output regardless of the port setting) r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 54 of 453 rej09b0278-0210 figure 7.1 configuration of programmable i/o ports (1) p1_0 to p1_3 1 output from individual peripheral function analog input port latch data bus pull-up selection input to individual peripheral function p1_4 1 port latch data bus pull-up selection output from individual peripheral function p0 direction register direction register port latch data bus pull-up selection analog input direction register note: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) drive capacity select (for n, d version only) drive capacity select (for n, d version only) drive capacity select (for n, d version only) drive capacity select (for n, d version only) r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 55 of 453 rej09b0278-0210 figure 7.2 configuration of programmable i/o ports (2) p1_6 direction register data bus pull-up selection input to individual peripheral function 1 output from individual peripheral function p1_5 and p1_7 direction register data bus pull-up selection input to individual peripheral function 1 input to external interrupt digital filter output from individual peripheral function port latch port latch note: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. (note 1) (note 1) (note 1) (note 1) drive capacity select (for n, d version only) drive capacity select (for n, d version only) drive capacity select (for n, d version only) drive capacity select (for n, d version only) r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 56 of 453 rej09b0278-0210 figure 7.3 configuration of programmable i/o ports (3) p3_4, p3_5, and p3_7 1 direction register data bus pull-up selection input to individual peripheral function output from individual peripheral function p3_1 direction register data bus pull-up selection 1 output from individual peripheral function p3_3 and p3_6 direction register data bus pull-up selection input to individual peripheral function 1 output from individual peripheral function input to external interrupt digital filter note: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) port latch port latch port latch r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 57 of 453 rej09b0278-0210 figure 7.4 configuration of programmable i/o ports (4) p4_2/vref data bus (note 1) (note 1) p4_5 direction register data bus pull-up selection input to individual peripheral function 1 output from individual peripheral function input to external interrupt digital filter (note 1) (note 1) note: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. port latch r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 58 of 453 rej09b0278-0210 figure 7.5 configuration of programmable i/o ports (5) p4_6/xin data bus p4_7/xout data bus (note 2) (note 1) (note 1) (note 1) (note 1) cm05 cm11 cm13 01 cm01 01 cm01 rfxin xin oscillation circuit cm12 rfxcin xcin oscillation circuit cm04 p4_6/xin data bus p4_7/xout data bus (note 2) (note 1) (note 1) (note 1) (note 1) cm05 cm11 cm13 rfxin xin oscillation circuit 2. this pin is pulled up in one of the following conditions: ? cm01 = cm05 = cm13 = 1 ? cm01 = cm04 = 1 ? cm01 = cm10 = cm13 = 1 ? cm01 = cm10 = cm04 = 1 cm01, cm04, cm05: bits in cm0 register cm10, cm13: bits in cm1 register notes: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. (n, d version) (j, k version) r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 59 of 453 rej09b0278-0210 figure 7.6 configuration of programmable i/o ports (5) figure 7.7 configuration of i/o pins p5_3 and p5_4 direction register data bus pull-up selection input to individual peripheral function 1 output from individual peripheral function note: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. port latch (note 1) (note 1) mode mode signal input reset reset signal input note: 1. symbolizes a parasitic diode. ensure the input voltage to each port does not exceed vcc. (note 1) (note 1) r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 60 of 453 rej09b0278-0210 figure 7.8 pdi (i = 0, 1, and 3 to 5) register port pi direction register (i = 0, 1, 3 to 5) (1, 2, 3, 4) symbol address after reset pd0 00e2h 00h pd1 00e3h 00h pd3 00e7h 00h pd4 00eah 00h pd5 00ebh 00h bit symbol bit name function rw notes: 1. 2. 3. 4. bits pd4_0 to pd4_4, pd4_6, and pd4_7 in the pd4 register are unavailable on this mcu. if it is necessary to set bits pd4_0 to pd4_4, pd4_6, and pd4_7, set to 0 (input mode). when read, the content is 0. bits pd5_0 to pd5_2 and pd5_5 to pd5_7 in the pd5 register are unavailable on this mcu. if it is necessary to set bits pd5_0 to pd5_2 and pd5_5 to pd5_7, set to 0 (input mode). when read, the content is 0. bits pd3_0 and pd3_2 in the pd3 register are unavailable on this mcu. if it is necessary to set bits pd3_0 and pd3_2, set to 0 (input mode). when read, the content is 0. pdi_3 port pi_3 direction bit po r t pi_ 1 d ir e c t io n b it po r t pi_ 4 d ir e c t io n b it po r t pi_ 2 d ir e c t io n b it pdi_ 4 rw rw po r t pi_ 5 d ir e c t io n b it rw 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) rw rw po r t pi_ 6 d ir e c t io n b it rw po r t pi_ 0 d ir e c t io n b it b7 b6 b5 b4 b3 b2 pdi_ 2 b1 b0 pdi_ 1 pdi_ 0 set the pd0 register by using the next instruction after setting the prc2 bit in the prcr register to 1 (w rite enable). pdi_ 6 rw pdi_7 port pi_7 direction bit rw pdi_ 5 r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 61 of 453 rej09b0278-0210 figure 7.9 pi (i = 0, 1, and 3 to 5) register port pi register (i = 0, 1, 3 to 5) (1, 2, 3) symbol address after reset p0 00e0h 00h p1 00e1h 00h p3 00e5h 00h p4 00e8h 00h p5 00e9h 00h bit symbol bit name function rw notes: 1. 2. 3. bits p4_0, p4_1, p4_3, and p4_4, in the p4 register are unavailable on this mcu. if it is necessary to set bits p4_0, p4_1, p4_3, and p4_4, set to 0 (?l? level). when read, the content is 0. bits p5_0 to p5_2, p5_5 to p5_7 in the p5 register are unavailable on this mcu. if it is necessary to set bits p5_0 to p5_2, p5_5 to p5_7, set to 0 (?l? level). when read, the content is 0. pi_ 7 pi_ 6 rw bits p3_0 and p3_2 in the p3 register are unavailable on this mcu. if it is necessary to set bits p3_0 and p3_2, set to 0 (?l? level). when read, the content is 0. b3 b2 b1 b0 pi_ 1 pi_ 5 pi_ 0 pi_ 2 pi_ 4 pi_ 3 b7 b6 b5 b4 po r t pi_ 0 b it po r t pi_ 1 b it po r t pi_ 7 b it po r t pi_ 5 b it po r t pi_ 4 b it po r t pi_ 3 b it rw po r t pi_ 6 b it rw po r t pi_ 2 b it rw the pin level of any i/o port w hich is set to input mode can be read by reading the corresponding bit in this register. the pin level of any i/o port w hich is set to output mode can be controlled by w riting to the corresponding bit in this register. 0 : ?l? level 1 : ?h? level rw rw rw rw r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 62 of 453 rej09b0278-0210 figure 7.10 registers pinsr1, pinsr2, and pinsr3 pin select register 1 symbol address after reset pinsr1 00f5h 00h bit symbol bit name function rw note: 1. b0 b1 b0 0 0 : p3_7(txd1/rxd1) 0 1 : p3_7(txd1), p4_5(rxd1) 1 0 : p3_6(txd1/rxd1) 1 1 : do not set. txd1/rxd1 pin select bit (1) b3 b2 1 b1 0 b7 b6 b5 b4 rw ua rt1sel1 ua rt1sel0 0000 the uart1 pins can be selected by using bits u1pinsel, txd1sel and txd1en in the pmr register. refer to figur e 7.11 pm r re g is t e r . rw rw rw ? (b2) ? (b7-b3) set to 1. when read, the content is 0. set to 0. when read, the content is 0. reserved bits reserved bit pin select register 2 symbol address after reset pinsr2 00f6h 00h bit symbol bit name function rw ? (b7) ? (b5-b0) b3 b2 0 b1 0 0 b0 0 b7 b6 b5 b4 trbosel 000 0 : p3_1 1 : p1_3 trbo pin select bit rw rw rw set to 0. when read, the content is 0. set to 0. when read, the content is 0. reserved bits reserved bit pin select register 3 symbol address after reset pinsr3 00f7h 00h bit symbol bit name function rw b0 1 0 : p5_3 1 : p3_4 b3 b2 1 b1 1 b7 b6 b5 b4 rw trciocsel ? (b2-b0) 1 reserved bits set to 1. when read, the content is 0. trcioc pin select bit rw rw rw ? nothing is assigned. if necessary, set to 0. when read, the content is 0. trciodsel trciod pin select bit 0 : p5_4 1 : p3_5 ? (b5) ? (b7-b6) set to 1. when read, the content is 0. reserved bit r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 63 of 453 rej09b0278-0210 figure 7.11 pmr register port mode registe r symbol address after reset pmr 00f8h 00h bit symbol bit name function rw int1 _ ____ pin select bit note: 1. the uart1 pins can be selected by using bits u1pinsel, txd1sel and txd1en, and bits uart1sel1 and uart1sel0 in the pinsr1 register. iicsel ssu / i 2 c bus pin sw itch bit 0 : selects ssu function 1 : selects i 2 c bus function rw txd1en txd1/rxd1 select bit (1) 0 : rxd1 1 : txd1 rw txd1sel port/txd1 pin sw itch bit (1) 0 : programmable i/o port 1 : txd1 rw u1pinsel txd1 pin sw itch bit (1) 0 : p0_0 1 : p3_6, p3_7 rw ssisel ssi pin select bit 0 : p3_3 1 : p1_6 rw int1sel 0 : p1_5, p1_7 1 : p3_6 rw ? (b2-b1) ? nothing is assigned. if necessary, set to 0. when read, the content is 0. b0 b3 b2 b1 b7 b6 b5 b4 pinsr1 regis ter ua rt1sel1, ua rt1sel0 bit u1pinsel bit txd1sel bit txd1en bit p3_7(txd1) 1 p3_7(rxd1) 0 p0_0(txd1) 0 1 p3_7(txd1) 1 p4_5(rxd1) p3_6(txd1) 1 p3_6(rxd1) 0 p0_0(txd1) 0 1 : 0 or 1 10b pmr register pin function 00b 01b 1 r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 64 of 453 rej09b0278-0210 figure 7.12 registers pur0 and pur1 figure 7.13 p1drr register pull-up control register 0 symbol address after reset pur0 00fch 00h bit symbol bit name function rw note: 1. ? (b5-b4) pu0 2 set to 0. when read, the content is 0. 0 : not pulled up 1 : pulled up reserved bits 0 : not pulled up 1 : pulled up when this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up. pu0 7 rw p3_4 to p3_7 pull-up (1) pu06 p3_1 and p3_3 pull-up (1) rw b3 b2 b1 b0 pu0 0 b7 b6 b5 b4 00 rw p0_4 to p0_7 pull-up (1) p0_0 to p0_3 pull-up (1) pu03 p1_4 to p1_7 pull-up (1) p1_0 to p1_3 pull-up (1) pu0 1 rw rw rw rw pull-up control register 1 symbol address after reset pur1 00fdh 00h bit symbol bit name function rw note: 1. pu13 p5_4 pull-up (1) 0 : not pulled up 1 : pulled up rw ? (b5-b4) reserved bits rw pu11 p4_5 pull-up (1) rw pu1 2 rw rw set to 0. when read, the content is 0. ? (b7-b6) nothing is assigned. if necessary, set to 0. when read, the content is 0. 00 ? (b0) reserved bit set to 0. when read, the content is 0. p5_3 pull-up (1) b7 b6 b5 b4 b0 0 ? when this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up. b3 b2 b1 port p1 drive capacity control register (for n, d version only) symbol address after reset p1 drr 00feh 00h bit symbol bit name function rw note: 1. p1drr4 rw p1_4 drive capacity rw p1_5 drive capacity rw rw p1_1 drive capacity p1_0 drive capacity p1drr3 p1_2 drive capacity p1drr1 rw rw rw b0 p1drr0 b7 b6 b5 b4 b3 b2 b1 both ?h? and ?l? output are set to high drive capacity. p1drr7 p1drr5 rw set p1 output transistor drive capacity 0 : low 1 : high (1) p1drr2 p1_7 drive capacity p1_3 drive capacity p1drr6 p1_6 drive capacity r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 65 of 453 rej09b0278-0210 7.4 port setting table 7.4 to table 7.40 list the port setting. x: 0 or 1 notes: 1. when the u1pinsel bit is set to 0 (p0_0) and txd1sel bit is set to 1 (txd1) in the pmr register, set bits smd2 to smd0 in the u1mr register to 000b (serial interface disabled). 2. pulled up by setting the pu00 bit in the pur0 register to 1. 3. this is enabled when bits uart1sel1 and uart1sel0 in the pi nsr1 register are set to 00b or 10b, and the u1pinsel bit is set to 0 (p0_0) and txd1sel bit is set to 1 (txd1) in the pmr register. 4. n-channel open drain output by setting the nch bit in the u1c0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu00 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu00 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu00 bit in the pur0 register to 1. table 7.4 port p0_0/an7/(txd1) register pd0 u1mr adcon0 function bit pd0_0 smd2 smd1 smd0 ch2 ch1 ch0 adgsel0 setting value 0xxxxxx x input port (1, 2) 1xxxxxx x output port (1) 0xxx1 1 1 0 a/d converter input (an7) (1) x 0 0 1 xxx x txd1 output (3, 4) 1 0 1 10 table 7.5 port p0_1/an6 register pd0 adcon0 function bit pd0_1 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 1 1 0 0 a/d converter input (an6) table 7.6 port p0_2/an5 register pd0 adcon0 function bit pd0_2 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 1 0 1 0 a/d converter input (an5) table 7.7 port p0_3/an4 register pd0 adcon0 function bit pd0_3 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 1 0 0 0 a/d converter input (an4) r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 66 of 453 rej09b0278-0210 x: 0 or 1 note: 1. pulled up by setting the pu01 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu01 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu01 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu01 bit in the pur0 register to 1. x: 0 or 1 note: 1. pulled up by setting the pu02 bit in the pur0 register to 1. table 7.8 port p0_4/an3/treo register pd0 trecr1 adcon0 function bit pd0_4 toena ch2 ch1 ch0 adgsel0 setting value 0 0xxxx input port (1) 1 0 x x x x output port 000110a/d converter i nput (an3) x1xxxxtreo output table 7.9 port p0_5/an2/clk1 register pd0 u1mr adcon0 function bit pd0_5 smd2 smd1 smd0 ckdir ch2 ch1 ch0 adgsel0 setting value 0 other than 001b x x x x x input port (1) x x x 1 xxx x 1 other than 001b x x x x x output port 0 other than 001b x 0 1 0 0 a/d converter input (an2) x 0 0 1 0 x x x x clk1 output 0 x x x 1 xxx x clk1 input (1) table 7.10 port p0_6/an1 register pd0 adcon0 function bit pd0_6 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 0 0 1 0 a/d converter input (an1) table 7.11 port p0_7/an0 register pd0 adcon0 function bit pd0_7 ch2 ch1 ch0 adgsel0 setting value 0xxxx input port (1) 1 x x x x output port 0 0 0 0 0 a/d converter input (an0) table 7.12 port p1_0/ki0 /an8 register pd1 kien adcon0 function bit pd1_0 ki0en ch2 ch1 ch0 adgsel0 setting value 00xxxx input port (1) 1 0 x x x x output port 01xxxx ki 0 input (1) 0 0 1 0 0 1 a/d converter input (an8) r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 67 of 453 rej09b0278-0210 x: 0 or 1 note: 1. pulled up by setting the pu02 bit in the pur0 register to 1. x: 0 or 1 x: 0 or 1 note: 1. pulled up by setting the pu02 bit in the pur0 register to 1. x: 0 or 1 table 7.13 port p1_1/ki1 /an9/trcioa/trctrg register pd1 kien timer rc setting adcon0 function bit pd1_1 ki1en ? ch2 ch1 ch0 adgsel0 setting value 0 0 other than trcioa usage conditions x x x x input port (1) 1 0 other than trcioa usage conditions x x x x output port 0 0 other than trcioa usage conditions 1 0 1 1 a/d converter input (an9) 0 1 other than trcioa usage conditions x x x x ki 1 input (1) x0 refer to table 7.14 trcioa pin setting xxx x trcioa output 00 refer to table 7.14 trcioa pin setting xxx x trcioa input (1) table 7.14 trcioa pin setting register trcoer trcmr trcior0 trccr2 function bit ea pwm2 ioa2 ioa1 ioa0 tceg1 tceg0 setting value 01 001xx timer waveform output (output compare function) 01xxx 0 11xx xx timer mode (input capture function) 1xx 1 0xxx 01 pwm2 mode trctrg input 1x other than above other than trcioa usage conditions table 7.15 port p1_2/ki2 /an10/trciob register pd1 kien timer rc setting adcon0 function bit pd1_2 ki2en ? ch2 ch1 ch0 adgsel0 setting value 0 0 other than trciob usage conditions x x x x input port (1) 1 0 other than trciob usage conditions x x x x output port 0 0 other than trciob usage conditions 1 1 0 1 a/d converter input (an10) 0 1 other than trciob usage conditions x x x x ki 2 input (1) x0 refer to table 7.16 trciob pin setting xxx x trciob output 00 refer to table 7.16 trciob pin setting xxx x trciob input (1) table 7.16 trciob pin setting register trcoer trcmr trcior0 function bit eb pwm2 pwmb iob2 iob1 iob0 setting value 0 0xxxxpwm2 mode waveform output 0 1 1 x x x pwm mode waveform output 010 001 timer waveform output (output compare function) 01x 0 1 0 1 x x timer mode (input capture function) 1 other than above other than trciob usage conditions r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 68 of 453 rej09b0278-0210 x: 0 or 1 note: 1. pulled up by setting the pu02 bit in the pur0 register to 1. note: 1. set the tocnt bit in the trbioc register to 0 in modes except for programmable waveform generation mode. x: 0 or 1 notes: 1. pulled up by setting the pu03 bit in the pur0 register to 1. 2. n-channel open drain output by setting the nch bit in the u0c0 register to 1. table 7.17 port p1_3/ki3 /an11/(trbo) register pd1 kien timer rb setting adcon0 function bit pd1_3 ki3en ? ch2 ch1 ch0 adgsel0 setting value 0 0 other than trbo usage conditions x x x x input port (1) 1 0 other than trbo usage conditions x x x x output port 0 0 other than trbo usage conditions 1 1 1 1 a/d converter input (an11) 0 1 other than trbo usage conditions x x x x ki3 input x0 refer to table 7.18 trbo pin setting x x x x trbo output table 7.18 trbo pin setting register pinsr2 trbioc trbmr function bit trbosel tocnt (1) tmod1 tmod0 setting value 1 0 0 1 programmable waveform generation mode 1 0 1 0 programmable one-shot generation mode 1 0 1 1 programmable wait one-shot generation mode 1 1 0 1 p1_3 output port other than above other than trbo usage conditions table 7.19 port p1_4/txd0 register pd1 u0mr function bit pd1_4 smd2 smd1 smd0 setting value 0000 input port (1) 1000output port x 001 txd0 output (2) 100 101 110 r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 69 of 453 rej09b0278-0210 x: 0 or 1 notes: 1. pulled up by setting the pu03 bit in the pur0 register to 1. 2. set the int1sel bit in the pmr register to 0 (p1_5, p1_7). 3. set the topcr bit in the traioc register to 0 in modes except for pulse output mode. x: 0 or 1 notes: 1. pulled up by setting the pu03 bit in the pur0 register to 1. 2. set the ssisel bit in the pmr register to 1 (p1_6). 3. when the soos bit is set to 1 (n-channel open drain output) and bide bit is set to 0 (standard mode) in the ssmr2 register, this pin is set to n-channel open drain output. x: 0 or 1 notes: 1. pulled up by setting the pu03 bit in the pur0 register to 1. 2. set the int1sel bit in the pmr register to 0 (p1_5, p1_7). table 7.20 port p1_5/rxd0/(traio)/(int1 ) register pd1 traioc tramr inten function bit pd1_5 tiosel topcr (3 ) tmod2 tmod1 tmod0 int1en setting value 0 0xxxxx input port (1) 110010 100000 1 0xxxxx output port 10000x 0 0xxxxx rxd0 input (1) 1 0 other than 001b 0 1 0 other than 000b, 001b 0 traio input (1) 100001 int1 (2) 110011 1 0 other than 000b, 001b 1 traio input/int1 (1, 2) x10001xtraio pulse output table 7.21 port p1_6/clk0/(ssi) register pd1 u0mr pmr clock synchronous serial i/o with chip select (refer to table 16.4 association between communication modes and i/o pins .) function (3) bit pd1_6 ckdir smd2 smd1 smd0 iicsel ssi output control ssi input control setting value 0xxxxx 0 0 input port (1) 1 x other than 001b x 0 0 output port x 0 0 0 1 x 0 0 clk0 output 01xxxx 0 0 clk0 input (1) xxxxx 0 1 0 ssi output (2) xxxxx 0 0 1 ssi input (1, 2) table 7.22 port p1_7/traio/int1 register pd1 traioc tramr inten function bit pd1_7 tiosel topcr (3) tmod2 tmod1 tmod0 int1en setting value 0 1 x xxxx input port (1) 010010 000000 1 1 x xxxx output port 00000x 0 0 0 other than 000b, 001b 0 traio input (1) 000001 int1 (2) 010011 0 0 other than 000b, 001b 1 traio input/int1 (1, 2) x 0 0 0 0 1 x traio pulse output r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 70 of 453 rej09b0278-0210 3. set the topcr bit in the traioc register to 0 in modes except for pulse output mode. x: 0 or 1 note: 1. pulled up by setting the pu06 bit in the pur0 register to 1. note: 1. set the tocnt bit in the trbioc register to 0 in modes except for programmable waveform generation mode. x: 0 or 1 notes: 1. pulled up by setting the pu06 bit in the pur0 register to 1. 2. set the ssisel bit in the pmr register to 0 (p3_3). 3. when the soos bit is set to 1 (n-channel open drain output) and bide bit is set to 0 (standard mode) in the ssmr2 register, this pin is set to n-channel open drain output. x: 0 or 1 notes: 1. pulled up by setting the pu07 bit in the pur0 register to 1. 2. n-channel open drain output by setting the csos bit in the ssmr2 register to 1 (n-channel open drain output). table 7.23 port p3_1/trbo register pd3 timer rb setting function bit pd3_1 ? setting value 0 other than trbo usage conditions input port (1) 1 other than trbo usage conditions output port x refer to table 7.24 trbo pin setting trbo output table 7.24 trbo pin setting register pinsr2 trbioc trbmr function bit trbosel tocnt (1) tmod1 tmod0 setting value 0 0 0 1 programmable waveform generation mode 0 0 1 0 programmable one-shot generation mode 0 0 1 1 programmable wait one-shot generation mode 0101 p3_1 output port other than above other than trbo usage conditions table 7.25 port p3_3/int3 /ssi/trcclk register pd3 pmr clock synchronous seri al i/o with chip select (refer to table 16.4 association between communication modes and i/o pins .) trccr1 inten function (3) bit pd3_3 iicsel ssi output control ssi input control tck2 tck1 tck0 int3en setting value 0 x 0 0 other than 101b 0 input port (1) 1 x 0 0 other than 101b 0 output port 0 x 0 0 other than 101b 1 int3 input (1) 0 x 0 0 101 0 trcclk input (1) x 0 1 0 other than 101b 0 ssi output (2) x 0 0 1 other than 101b 0 ssi input (2) table 7.26 port p3_4/sda/scs /(trcioc) register pd3 pmr iccr1 ssmr2 timer rc setting function (2) bit pd3_4 iicsel ice css1 css0 ? setting value 0 0 x 0 0 other than trcioc usage conditions input port (1) 1 0 0 0 other than trcioc usage conditions 1 0 x 0 0 other than trcioc usage conditions output port 1 0 0 0 other than trcioc usage conditions x x 0 0 0 refer to table 7.27 trcioc pin setting trcioc output 0 x 0 0 0 refer to table 7.27 trcioc pin setting trcioc input (1) x 0 x 1 0 other than trcioc usage conditions scs output x 0 x 1 1 other than trcioc usage conditions scs input (1) x 1 1 x x other than trcioc usage conditions sda input/output r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 71 of 453 rej09b0278-0210 x: 0 or 1 x: 0 or 1 notes: 1. pulled up by setting the pu07 bit in the pur0 register to 1. 2. n-channel open drain output by setting the sckos bit in the ssmr2 register to 1 (n-channel open drain output). x: 0 or 1 table 7.27 trcioc pin setting register pinsr3 trcoer trcmr trcior1 function bit trciocsel ec pwm2 pwmc ioc2 ioc1 ioc0 setting value 1 0 1 1 x x x pwm mode waveform output 1 010 001 timer waveform output (output compare function) 101x 10 1 0 1 x x timer mode (input capture function) 11 other than above other than trcioc usage conditions table 7.28 port p3_5/scl/ssck/(trciod) register pd3 pmr iccr1 clock synchronous serial i/o with chip select (refer to table 16.4 association between communication modes and i/o pins .) timer rc setting function (2) bit pd3_5 iicsel ice ssck output control ssck input control ? setting value 0 0x 0 0 other than trciod usage conditions input port (1) 10 0 0 other than trciod usage conditions 1 0x 0 0 other than trciod usage conditions output port 10 0 0 other than trciod usage conditions xx0 0 0 refer to table 7.29 trciod pin setting trciod output 0x0 0 0 refer to table 7.29 trciod pin setting trciod input (1) x0x 1 0 other than trciod usage conditions ssck output (2) x0x 0 1 other than trciod usage conditions ssck input (1) x11 x x other than trciod usage conditions scl input/output table 7.29 trciod pin setting register pinsr3 trcoer trcmr trcior1 function bit trciodsel ec pwm2 pwmd iod2 iod1 iod0 setting value 1 0 1 1 x x x pwm mode waveform output 1 010 001 timer waveform output (output compare function) 101x 10 1 0 1 x x timer mode (input capture function) 11 other than above other than trciod usage conditions r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 72 of 453 rej09b0278-0210 x: 0 or 1 notes: 1. pulled up by setting the pu07 bit in the pur0 register to 1. 2. set the int1sel bit in the pmr register to 1 (p3_6). 3. set bits uart1sel1 and uart1sel0 in the pinsr1 register to 10b. 4. n-channel open drain output by setting the nch bit in the u1c0 register to 1. x: 0 or 1 notes: 1. pulled up by setting the pu07 bit in the pur0 register to 1. 2. set the ssisel bit in the pmr register to 0 (p3_3). 3. n-channel open drain output by setting the soos bit in the ssmr2 register to 1 (n-channel open drain output). 4. n-channel open drain output by setting the nch bit in the u1c0 register to 1. table 7.30 port p3_6/(txd1)/(rxd1)/(int1 ) register pd3 pmr u1mr inten function bit pd3_6 txd1en smd2 smd1 smd0 int1en setting value 0 0xxx0 input port (1) x0000 1 0xxx0 output port x0000 0 0xxx1 int1 input (1, 2) x0001 x1 0010 txd1 output (3, 4) 1000 1010 1100 00xxx0 rxd1 input (1) table 7.31 port p3_7/trao/sso/rxd1/(txd1) register pd3 pmr clock synchronous serial i/o with chip select (refer to table 16.4 association between communication modes and i/o pins .) tramr uart1 setting function (3) bit pd3_7 iicsel sso output control sso input control toena ? setting value 0x 0 0 0 other than txd1, rxd1 usage conditions input port (1) 1x 0 0 0 other than txd1, rxd1 usage conditions output port xx 0 0 x refer to table 7.32 port p3_7 uart1 setting condition txd1 output (4) 0x 0 0 0 refer to table 7.32 port p3_7 uart1 setting condition rxd1 input (1) xx 0 0 1 other than txd1, rxd1 usage conditions trao output x0 1 0 x other than txd1, rxd1 usage conditions sso output (2) x0 0 1 x other than txd1, rxd1 usage conditions sso input (2) r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 73 of 453 rej09b0278-0210 x: 0 or 1 note: 1. pulled up by setting the pu11 bit in the pur1 register to 1. table 7.32 port p3_7 uart1 setting condition register pinsr1 pmr u1mr function bit uart1sel1 uart1sel0 u1pinsel txd1sel txd1en smd2 smd1 smd0 setting value 0 0xx1 001 txd1 output 100 101 110 111x 001 100 101 110 0 x x 0 xxxrxd1 input other than above other than txd1, rxd1 usage conditions table 7.33 port p4_2/vref register adcon1 function bit vcut setting value 0 input port 1 input port/vref input table 7.34 port p4_5/int0 /(rxd1) register pd4 inten pinsr1 pmr function bit pd4_5 int0en uart1sel1 uart1sel0 u1pinsel setting value 0 0 other than 011b input port (1) 1 0 other than 011b output port 0 1 other than 011b int0 input (1) 00011 rxd1 (1) r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 74 of 453 rej09b0278-0210 x: 0 or 1 note: 1. for n, d version only. x: 0 or 1 notes: 1. since the xcin-xcout oscillation buffe r operates with internal step-down power, the xcout output level cannot be used as the cmos level signal directly. 2. for n, d version only. table 7.35 port p4_6/xin/xcin register cm0 cm1 circuit specifications function bit cm01 cm04 cm05 cm13 cm12 cm11 cm10 oscillation buffer feedback resistor setting value x010xx0 off ? input port 0x 0 1x 0 0 on on xin clock oscillation (on-chip feedback resistor enabled) 1onoff xin clock oscillation (on-chip feedback resistor disabled) 1 0 off on external clock input 0offon xin clock oscillation stop (on-chip feedback resistor enabled) 1offoff xin clock oscillation stop (on-chip feedback resistor disabled) 11 off off xin clock oscillation stop (stop mode) 1 1 xx 0 x 0 on on xcin clock oscillation (on-chip feedback resistor enabled) (1) 1onoff xcin clock oscillation (on-chip feedback resistor disabled) (1) 0 0offon external xcin clock input (1) 0offon xcin clock oscillation stop (on- chip feedback resistor enabled) (1) 1offoff xcin clock oscillation stop (on- chip feedback resistor disabled) (1) 11offoff xcin clock oscillation stop (stop mode) (1) table 7.36 port p4_7/xout/xcout register cm0 cm1 circuit specifications function bit cm01 cm04 cm05 cm13 cm12 cm11 cm10 oscillation buffer feedback resistor setting value x010xx0 off ? input port 0x 0 1x 0 0 on on xin clock oscillation (on-chip feedback resistor enabled) 1onoff xin clock oscillation (on-chip feedback resistor disabled) 1 0 off on external clock input 0offon xin clock oscillation stop (on-chip feedback resistor enabled) 1offoff xin clock oscillation stop (on-chip feedback resistor disabled) 11 off off xout pulled up (2) 1 1 xx 0 x 0 on on xcin clock oscillation (on-chip feedback resistor enabled) (1, 2) 1onoff xcin clock oscillation (on-chip feedback resistor disabled) (1, 2) 0 0offon external xcin clock input (2) 0offon xcin clock oscillation stop (on- chip feedback resistor enabled) (2) 1offoff xcin clock oscillation stop (on- chip feedback resistor disabled) (2) 11offoff xcout pulled up (2) r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 75 of 453 rej09b0278-0210 x: 0 or 1 note: 1. pulled up by setting the pu12 bit in the pur1 register to 1. x: 0 or 1 x: 0 or 1 note: 1. pulled up by setting the pu13 bit in the pur1 register to 1. x: 0 or 1 table 7.37 port p5_3/trcioc register pd5 timer rc setting function bit pd5_3 ? setting value 0 other than trcioc usage conditions input port (1) 1 other than trcioc usage conditions output port x refer to table 7.38 trcioc pin setting trcioc output 0 refer to table 7.38 trcioc pin setting trcioc input (1) table 7.38 trcioc pin setting register pinsr3 trcoer trcmr trcior1 function bit trciocsel ec pwm2 pwmc ioc2 ioc1 ioc0 setting value 0 0 1 1 x x x pwm mode waveform output 0 010 001 timer waveform output (output compare function) 001x 00 1 0 1 x x timer mode (input capture function) 01 other than above other than trcioc usage conditions table 7.39 port p5_4/trciod register pd5 timer rc setting function bit pd5_4 ? setting value 0 other than trciod usage conditions input port (1) 1 other than trciod usage conditions output port x refer to table 7.40 trciod pin setting trciod output 0 refer to table 7.40 trciod pin setting trciod input (1) table 7.40 trciod pin setting register pinsr3 trcoer trcmr trcior1 function bit trciodsel ed pwm2 pwmd iod2 iod1 iod0 setting value 0 0 1 1 x x x pwm mode waveform output 0 010 001 timer waveform output (output compare function) 001x 00 1 0 1 x x timer mode (input capture function) 01 other than above other than trciod usage conditions r8c/26 group, r8c/27 group 7. programmable i/o ports rev.2.10 sep 26, 2008 page 76 of 453 rej09b0278-0210 7.5 unassigned pin handling table 7.41 lists the unassigned pin handling. notes: 1. if these ports are set to output mode and left open, they remain in input mode until they are switched to output mode by a program. the voltage level of these pins may be undefined and the power current may increase while the ports remain in input mode. the content of the direction regi sters may change due to noise or program runaway caused by noise. in order to enhance progra m reliability, the program should periodically repeat the setting of the direction registers. 2. connect these unassigned pins to the mcu using th e shortest wire length (2 cm or less) possible. 3. when the power-on reset function is in use. figure 7.14 unassigned pin handling table 7.41 unassigned pin handling pin name connection ports p0, p1, p3_1, p3_3 to p3_7, p4_3 to p4_5, p5_3, p5_4 ? after setting to inpu t mode, connect each pin to vss via a resistor (pull-down) or connect each pin to vcc via a resistor (pull-up). (2) ? after setting to output mode, leave these pins open. (1, 2) ports p4_6, p4_7 connect to vcc via a pull-up resistor (2) port p4_2, vref connect to vcc reset (3) connect to vcc via a pull-up resistor (2) note: 1. when the power-on reset function is in use. mcu port p0, p1, p3_1, p3_3 to p3_7, p4_3 to p4_5, p5_3, p5_4 (input mode ) : : (input mode) (output mode) port p4_6, p4_7 reset (1) port p4_2/vref : : open r8c/26 group, r8c/27 group 8. processor mode rev.2.10 sep 26, 2008 page 77 of 453 rej09b0278-0210 8. processor mode 8.1 processor modes single-chip mode can be sel ected as the processor mode. table 8.1 lists features of processor mode. figure 8. 1 shows the pm0 register and figure 8.2 shows the pm1 register. figure 8.1 pm0 register figure 8.2 pm1 register table 8.1 features of processor mode processor mode accessible areas pin s assignable as i/o port pins single-chip mode sfr, internal ram, intern al rom all pins are i/o ports or peripheral function i/o pins processor mode register 0 (1) symbol address after reset pm0 0004h 00h bit symbol bit name function rw note: 1. rw reserved bits set to 0. set the prc1 bit in the prcr register to 1 (w rite enable) before rew riting the pm0 register. the mcu is reset w hen this bit is set to 1. when read, the content is 0. rw ? (b7-b4) pm0 3 softw are reset bit nothing is assigned. if necessary, set to 0. when read, the content is 0. b7 b6 b5 b4 b3 b2 ? b1 b0 00 0 ? (b2-b0) processor mode register 1 (1) symbol address after reset pm1 0005h 00h bit symbol bit name function rw notes: 1. 2. ? (b6-b3) pm1 2 wdt interrupt/reset sw itch bit nothing is assigned. if necessary, set to 0. when read, the content is 0. the pm12 bit is set to 1 by a program (it remains unchanged even if 0 is w ritten to it). when the cspro bit in the cspr register is set to 1 (count source protect mode enabled), the pm12 bit is automaticall y set to 1. reserved bit set to 0. set the prc1 bit in the prcr register to 1 (w rite enable) before rew riting the pm1 register. ? (b7) rw b3 b2 ? b1 b0 00 0 : watchdog timer interrupt 1 : watchdog timer reset (2) rw b7 b6 b5 b4 0 ? (b1-b0) rw reserved bits set to 0. r8c/26 group, r8c/27 group 9. bus rev.2.10 sep 26, 2008 page 78 of 453 rej09b0278-0210 9. bus the bus cycles differ when accessing rom/ram, and when accessing sfr. table 9.1 lists bus cycles by access sp ace of the r8c/26 group and table 9.2 li sts bus cycles by access space of the r8c/27 group. rom/ram and sfr are connected to the cp u by an 8-bit bus. when accessing in word (16-bit) units, these areas are accessed twice in 8-bit units. table 9.3 lists access un its and bus operations. table 9.3 access units and bus operations however, only following sfrs are connected with the 16-bit bus: timer rc: registers trc, trcgra, trcgrb, trcgrc, and trcgrd therefore, when accessing in word (16-bit) unit, 16-bit data is accessed at a time. the bus operation is the same as ?area: sfr, data flash, even address byte access? in ta ble 9.3 access units and bus operations, and 16-bit data is accessed at a time. table 9.1 bus cycles by access space of the r8c/26 group access area bus cycle sfr 2 cycles of cpu clock rom/ram 1 cycle of cpu clock table 9.2 bus cycles by access space of the r8c/27 group access area bus cycle sfr/data flash 2 cycles of cpu clock program rom/ram 1 cycle of cpu clock area sfr, data flash even address byte access rom (program rom), ram odd address byte access even address word access odd address word access cpu clock data data data data data data data data data even even odd odd even+1 even odd+1 odd address even+1 odd+1 odd data data even data cpu clock data address cpu clock data address cpu clock data address data cpu clock address data cpu clock address data cpu clock address data cpu clock address data r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 79 of 453 rej09b0278-0210 10. clock generation circuit the clock generation circuit has: ? xin clock oscillation circuit ? xcin clock oscillation circuit (for n, d version only) ? low-speed on-chip oscillator ? high-speed on-chip oscillator however, use one of the xin clock osci llation circuit or the xcin clock osci llation circuit becau se they share the xin/xcin pin and the xout/xcout pin. (for j, k vers ion, the xcin clock oscillation circuit cannot be used.) table 10.1 lists the specifications of clock generation circ uit. figure 10.1 shows a clock generation circuit. figures 10.2 to 10.9 show clock asso ciated registers. figure 10.10 shows a pro cedure for enabling re duced internal power consumption using vca20 bit. notes: 1. these pins can be used as p4_6 or p4_7 when using th e on-chip oscillator clock as the cpu clock while the xin clock oscillation circuit and xcin clock oscillation circuit is not used. 2. set the cm01 bit in the cm0 register to 0 (xin clock), the cm05 bit in the cm0 register to 1 (xin clock stopped), and the cm13 bit in the cm1 regi ster to 1 (xin-xout pin) when an external clock is input. 3. when 32.768 khz is used as an external clock, set the cm01 bit in the cm0 register to 1 (xcin clock). in other cases, set the cm01 bi t in the cm0 register to 0 (xin clock). 4. set the cm01 bit in the cm0 register to 1 (xcin clock) and the cm04 bit in the cm0 register to 1 (xcin clock oscillator) when an external clock is input. 5. the clock frequency is automatically set to up to 20 mhz by a divider when using the high-speed on-chip oscillator as the cpu clock source. table 10.1 specifications of clock generation circuit item xin clock oscillation circuit xcin clock oscillation circuit (for n, d version only) on-chip oscillator high-speed on-chip oscillator low-speed on-chip oscillator applications ? cpu clock source ? peripheral function clock source ? cpu clock source ? peripheral function clock source ? cpu clock source ? peripheral function clock source ? cpu and peripheral function clock sources when xin clock stops oscillating ? cpu clock source ? peripheral function clock source ? cpu and peripheral function clock sources when xin clock stops oscillating clock frequency 0 to 20 mhz 32.768 khz approx. 40 mhz (5) approx. 125 khz connectable oscillator ? ceramic resonator ? crystal oscillator ? crystal oscillator ?? oscillator connect pins xin, xout (1) xcin, xcout (1) ? (1) ? (1) oscillation stop, restart function usable usable usable usable oscillator status after reset stop stop stop oscillate others ? externally generated clock can be input (2, 3) ? on-chip feedback resistor rfxin (connected/ not connected, selectable) ? externally generated clock can be input (4) ? on-chip feedback resistor rfxcin (connected/ not connected, selectable) ?? r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 80 of 453 rej09b0278-0210 figure 10.1 clock generation circuit oscillation stop detection divider s q r 1/2 1/2 1/2 1/2 1/2 pulse generation circuit for clock edge detection and charge, discharge control circuit charge, discharge circuit oscillation stop detection interrupt generation circuit detection s q r fra00 high-speed on-chip oscillator fra01 = 1 fra01 = 0 cm14 cpu clock a b c d e ocd2 = 0 ocd2 = 1 xin clock cm02 wait instruction reset cm10 = 1 (stop mode) a d c h b cm06 = 0 cm17 to cm16 = 11b cm06 = 1 cm06 = 0 cm17 to cm16 = 10b cm06 = 0 cm17 to cm16 = 01b cm06 = 0 cm17 to cm16 = 00b detail of divider oscillation stop detection circuit xin clock forcible discharge when ocd0 = 0 ocd1 oscillation stop detection, watchdog timer, voltage monitor 1 interrupt, voltage monitor 2 interrupt e g uart0 a/d converter timer rc timer rb timer ra fra2 register foco foco-s g f1 f2 f4 f8 f32 int0 ssu / i 2 c bus watchdog timer system clock fra1 register frequency adjustable uart1 divider foco40m on-chip oscillator clock timer re foco-f xout/xcout (1) xin/xcin (1) power-on reset circuit voltage detection circuit divider foco128 power-on reset software reset interrupt request cm04 cm01 = 0 cm01 = 1 xcin clock cm01 = 0 cm13 cm05 cm01 low-speed on-chip oscillator cm01, cm02, cm04, cm05, cm06: bits in cm0 register cm10, cm13, cm14, cm16, cm17: bits in cm1 register ocd0, ocd1, ocd2: bits in ocd register fra00, fra01: bits in fra0 register watchdog timer interrupt ocd2 bit switch signal cm14 bit switch signal voltage monitor 2 interrupt voltage monitor 1 interrupt stop signal fc4 fc32 fc 1/8 1/4 note: 1. for j, k version, the xcin clock oscillation circuit cannot be used. clock prescaler r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 81 of 453 rej09b0278-0210 figure 10.2 cm0 register system clock control register 0 (1) symbol address after reset cm0 0006h 01101000b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. b7 b6 b5 b4 b3 b2 b1 b0 00 ? (b0) reserved bit set to 0. rw cm02 wait peripheral function clock stop bit 0 : peripheral function clock does not stop in w ait mode 1 : peripheral function clock stops in w ait mode rw cm03 xcin-xcout drive capacity select bit (2) 0 : low 1 : high rw cm04 xcin clock (xcin-xcout) oscillate bit (3, 4, 5, 12) 0 : xcin clock stops 1 : xcin clock oscillates (6, 7) rw cm05 xin clock (xin-xout) stop bit (3, 8) 0 : xin clock oscillates (9) 1 : xin clock stops (10) rw cm06 system clock division select bit 0 (11) 0 : cm16, cm17 enabled 1 : divide-by-8 mode rw ? (b7) reserved bit set to 0. rw during external clock input, only the clock oscillation buf f er is tur ned off and clock input is acknow ledged. when entering stop mode, the cm06 bit is set to 1 (divide-by-8 mode). p4_6 and p4_7 can be used as input ports w hen the cm04 bit is set to 0 (xcin clock stops), the cm05 bit is set to 1 (xin clock stops) and the cm13 bit in the cm1 register is set to 0 (p4_6, p4_7). to use the xcin clock, set the cm04 bit to 1. also, set ports p4_6 and p4_7 as input ports w ithout pull-up. set the cm01 bit to 1 (xcin clock). the cm05 bit stops the xin clock w hen the high-speed on-chip oscillator m ode, low -speed on-chip oscillator mode is selected. do not use this bit to detect w hether the xin clock is stopped. to stop the xin clock, set the bits in the follow ing order: (a) set bits ocd1 to ocd0 in the ocd register to 00b. (b) set the ocd2 bit to 1 (selects on-chip oscillator clock). for j, k version, the xcin clock oscillation circuit c annot be used. do not set to 1. cm01 xin-xcin sw itch bit (12) 0 : xin clock 1 : xcin clock rw set the prc0 bit in the prcr register to 1 (w rite enable) before rew riting the cm0 register. set the cm01 bit to 0 (xin clock). the mcu enters stop mode, the cm03 bit is set to 1 (high). rew rite the cm03 bit w hile the xcin clock oscillation stabilizes. the cm04 bit can be set to 1 by a program but cannot be set to 0. when the cm10 bit is set to 1 (stop mode) and the cm04 bit is set to 1 (xcin clock osc illates), the xcout (p4_7) pin goes ?h?. when the cm04 bit is set to 0 (xcin clock stops), p4_7 (xcout) enters input mode. r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 82 of 453 rej09b0278-0210 figure 10.3 cm1 register system clock control register 1 (1) symbol address after reset cm1 0007h 00100000b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. when entering stop mode, the cm15 bit is set to 1 (drive capacity high). set the prc0 bit in the prcr register to 1 (w rite enable) before rew riting the cm1 register. b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (4, 7, 8) 0 : clock operates 1 : stops all clocks (stop mode) rw cm11 xin-xout on-chip feedback resistor select bit 0 : on-chip feedback resistor enabled 1 : on-chip feedback resistor disabled rw cm12 xcin-xcout on-chip feedback resistor select bit (10) 0 : on-chip feedback resistor enabled 1 : on-chip feedback resistor disabled rw cm13 por t xin- xout s w itc h bit (7, 9) 0 : input ports p4_6, p4_7 1 : xin-xout pin rw cm14 low -speed on-chip osc illation stop bit (5, 6, 8) 0 : low -speed on-chip oscillator on 1 : low -speed on-chip oscillator of f rw cm15 xin-xout drive capacity select bit (2) 0 : low 1 : high rw cm17 rw b7 b6 0 0 : no division mode 0 1 : divide-by-2 mode 1 0 : divide-by-4 mode 1 1 : divide-by-16 mode system clock division select bits 1 (3) cm16 rw for j, k version, the xcin clock oscillation circuit cannot be used. set to 0. when the cm10 bit is set to 1 (stop mode) and the cm13 bit is set to 1 (xin-xout pin), the xout (p4_7) pin goes ?h?. when the cm13 bit is set to 0 (input ports, p4_6, p4_7), p4_7 (xout) enters input mode. in count source protect mode (refer to 13.2 count source protection mode enabled ), the value remains unchanged even if bits cm10 and cm14 are set. when the cm06 bit is set to 0 (bits cm16, cm17 enabled), bits cm16 to cm17 are enabled. if the cm10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled. when the ocd2 bit is set to 0 (xin clock selected), the cm14 bit is set to 1 (low -speed on-chip osc illator st opped). when the ocd2 bit is set to 1 (on-chip osc illator clock selected), the cm14 bit is set to 0 (low -speed on-chip oscillator on). it remains uncha nged even if 1 is w ritten to it. when using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the cm14 bit to 0 (low -speed on-chip osc illator on). once the cm13 bit is set to 1 by a program, it cannot be set to 0. r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 83 of 453 rej09b0278-0210 figure 10.4 ocd register oscillation stop detection register (1) symbol address after reset ocd 000ch 00000100b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. the ocd3 bit remains 0 (xin clock oscillates) if bits ocd1 to ocd0 are set to 00b. the cm14 bit is set to 0 (low -speed on-chip osc illator on) if the ocd2 bit is set to 1 (on-chip oscillator clock selected). ref er to figure 10.18 procedure for sw itching clock source from low -speed on-chip oscillator to xin clock for the sw itching procedure w hen the xin clock re-oscillates after detecting an osc illation stop. set the prc0 bit in the prcr register to 1 (w rite enable) before rew riting to the ocd register. the ocd2 bit is automatically set to 1 (on-chip oscillator clock selected) if a xin clock oscillation stop is detected w hile bits ocd1 to ocd0 are set to 11b. if the ocd3 bit is set to 1 (xin clock stopped), the ocd2 bit remains unchanged even w hen set to 0 (xin clock selected). the ocd3 bit is enabled w hen the ocd0 bit is set to 1 (osc illation stop detection f unction enabled). set bits ocd1 to ocd0 to 00b before entering stop mode, high-speed on-chip osc illator mode, or low -s peed on-chip oscillator m ode (xin clock stops). ? (b7-b4) reserved bits set to 0. rw ocd3 clock monitor bit (5, 6) 0 : xin clock oscillates 1 : xin clock stops ro ocd2 system clock select bit (4) 0 : selects xin clock (7) 1 : selects on-chip oscillator clock (3) rw ocd1 rw ocd0 rw oscillation stop detection enable bit (7) oscillation stop detection interrupt enable bit 0 : oscillation stop detection f unction disabled (2) 1 : oscillation stop detection f unction enabled 0 : disabled (2) 1 : enabled 0000 b3 b2 b1 b0 b7 b6 b5 b4 r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 84 of 453 rej09b0278-0210 figure 10.5 registers fra0 and fra1 high-speed on-chip oscillator control register 0 (1) symbol address after reset fra 0 0023h 00h bit symbol bit name function rw notes: 1. 2. 3. b7 b6 b5 b4 b3 b2 b1 b0 000000 fra 00 rw fra 01 rw high-speed on-chip oscillator enable bit 0 : high-speed on-chip oscillator of f 1 : high-speed on-chip oscillator on high-speed on-chip oscillator select bit (2) 0 : selects low -speed on-chip osc illator (3) 1 : selects high-speed on-chip osc illator when setting the fra01 bit to 0 (low -speed on-chip osc illator selected), do not set the fra 00 bit to 0 (high-s peed on-chip oscillator of f ) at the same time. set the fra 00 bit to 0 af ter setting the fra 01 bit to 0. change the fra01 bit under the follow ing conditions. ? fra 00 = 1 (high-speed on-chip oscillation) ? the cm14 bit in the cm1 register = 0 (low -speed on-chip oscillator on) ? bits fra22 to fra20 in the fra2 register: all divide ratio mode settings are supported w hen vcc = 3.0 to 5.5 v 000b to 111b (other than k version) divide ratio of 4 or more w hen vcc = 2.7 to 5.5 v or k version 010b to 111b divide ratio of 8 or more w hen vcc = 2.2 to 5.5 v (for n, d version only) 110b to 111b ? (b7-b2) reserved bits set to 0. rw set the prc0 bit in the prcr register to 1 (w rite enable) before rew riting the fra0 register. high-speed on-chip oscillator control register 1 (1) symbol address after reset fra 1 0024h when shipping rw notes: 1. 2. when changing the values of the fra1 register, adjust the fra1 register so that the frequency of the high-speed on-chip oscillator clock w ill be 40 mhz or less. b7 b6 b5 b4 b3 b2 b1 b0 set the prc0 bit in the prcr register to 1 (w rite enable) before rew riting the fra1 register. rw function the frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7. high-speed on-chip osc illator f r equency = 40 mhz (fra1 register = value w hen shipping) setting the fra1 register to a low er value results in a higher frequency. setting the fra1 register to a higher value results in a low er frequency. (2) r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 85 of 453 rej09b0278-0210 figure 10.6 registers fra2, fra4, fra6, and fra7 high-speed on-chip oscillator control register 2 (1) symbol address after reset fra 2 0025h 00h bit symbol bit name function rw notes: 1. 2. set the prc0 bit in the prcr register to 1 (w rite enable) before rew riting the fra2 register. b7 b6 b5 b4 b3 b2 b1 b0 00000 rw selects the dividing ratio for the high- speed on-chip osc illator clock. b2 b1 b0 0 0 0: divide-by-2 mode (2) 0 0 1: divide-by-3 mode (2) 0 1 0: divide-by-4 mode 0 1 1: divide-by-5 mode 1 0 0: divide-by-6 mode 1 0 1: divide-by-7 mode 1 1 0: divide-by-8 mode 1 1 1: divide-by-9 mode fra 20 do not set in k version. fra 22 rw ? (b7-b3) rw reserved bits set to 0. high-speed on-chip oscillator frequency sw itching bits rw fra 21 high-speed on-chip oscillator control register 4 (for n, d version only) symbol address after reset fra 4 0029h when shipping rw ro function stores data for frequency correction w hen vcc = 2.7 to 5.5 v. (the value is the same as that of the fra1 register after a reset.) optimal frequency correction to match the voltage conditions can be achieved by transferring this value to the fra1 register. b3 b2 b1 b0 b7 b6 b5 b4 high-speed on-chip oscillator control register 6 (for n, d version only) symbol address after reset fra 6 002bh when shipping rw ro function stores data for frequency correction w hen vcc = 2.2 to 5.5 v. optimal frequency correction to match the voltage conditions can be achieved by transferring this value to the fra1 register. b3 b2 b1 b0 b7 b6 b5 b4 high-speed on-chip oscillator control register 7 (for n, d version only) symbol address after reset fra 7 002ch when shipping rw ro function 36.864 mhz frequency correction data is stored. the oscillation frequency of the high-speed on-chip oscillator can be adjusted to 36.864 mhz by transferring this value to the fra1 register. b3 b2 b1 b0 b7 b6 b5 b4 r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 86 of 453 rej09b0278-0210 figure 10.7 cpsrf register figure 10.8 vca2 register (n, d version) clock prescaler reset flag (for n, d version only) symbol address after reset cpsrf 0028h 00h bit symbol bit name function rw note: 1. b7 b6 b5 b4 b3 b2 b1 b0 0000000 ? (b6-b0) reserved bits set to 0. rw only w rite 1 to this bit w hen selecting the xcin clock as the cpu clock, . cpsr clock prescaler reset flag (1) setting this bit to 1 initializes the clock prescaler. (when read, the content is 0) rw voltage detection register 2 (1) (n, d version) symbol address after reset (5) vca2 0032h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. use the vca20 bit only w hen entering to w ait mode. to set the vca20 bit, follow the procedure show n in figu r e 10.10 procedure for enabling reduced internal pow er consum ption using vca20 bit . vca20 internal pow er low consumption enable bit (6) 0 : disables low consumption 1 : enables low consumption rw set the prc3 bit in the prcr register to 1 (w rite enable) before w riting to the vca2 register. to use the voltage monitor 1 interrupt/reset or the vw1c3 bit in the vw1c register, set the vca26 bit to 1. after the vca26 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. to use the voltage monitor 2 interrupt/reset or the vca13 bit in the vca1 register, set the vca27 bit to 1. after the vca27 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. to use the voltage monitor 0 reset, set the vca25 bit to 1. after the vca25 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. vca27 voltage detection 2 enable bit (4) 0 : voltage detection 2 circuit disabled 1 : voltage detection 2 circuit enabled rw vca26 voltage detection 1 enable bit (3) 0 : voltage detection 1 circuit disabled 1 : voltage detection 1 circuit enabled rw 000 0 b3 b2 b1 b0 b7 b6 b5 b4 the lvd0on bit in the ofs register is set to 1 and hardw are reset : 00h pow er-on reset, voltage monitor 0 reset or lvd0on bit in the ofs register is set to 0, and hardw are reset : 00100000b vca25 voltage detection 0 enable bit (2) 0 : voltage detection 0 circuit disabled 1 : voltage detection 0 circuit enabled rw ? (b4-b1) reserved bits set to 0. rw r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 87 of 453 rej09b0278-0210 figure 10.9 vca2 register (j, k version) voltage detection register 2 (1) (j, k version) symbol address after reset (4) vca2 0032h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. the lvd1on bit in the ofs register is set to 1 and hardw are reset : 00h pow er-on reset, voltage monitor 1 reset or lvd1on bit in the ofs register is set to 0, and hardw are reset : 0100000b ? (b5-b1) reserved bits set to 0. rw b7 b6 b5 b4 b3 b2 b1 b0 00000 voltage detection 2 enable bit (3) 0 : voltage detection 2 circuit disabled 1 : voltage detection 2 circuit enabled rw vca26 voltage detection 1 enable bit (2) 0 : voltage detection 1 circuit disabled 1 : voltage detection 1 circuit enabled rw use the vca20 bit only w hen entering to w ait mode. to set the vca20 bit, follow the procedure show n in figu r e 10.10 procedure for enabling reduced internal pow er consum ption using vca20 bit . vca20 internal pow er low consumption enable bit (5) 0 : disables low consumption 1 : enables low consumption rw set the prc3 bit in the prcr register to 1 (w rite enable) before w riting to the vca2 register. to use the voltage monitor 1 reset, set the vca26 bit to 1. after the vca26 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. to use the voltage monitor 2 interrupt/reset or the vca13 bit in the vca1 register, set the vca27 bit to 1. after the vca27 bit is set to 1 from 0, the voltage detection circuit w aits for td(e-a) to elapse before starting operation. softw are reset, w atchdog timer reset, or voltage monitor 2 reset do not affect this register. vca27 r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 88 of 453 rej09b0278-0210 figure 10.10 procedure for enabling reduced internal power consumption using vca20 bit notes: 1. execute this routine to handle all interrupts generated in wait mode. however, this does not apply if it is not necessary to star t the high-speed clock or high-speed on-chip oscillator during the i nterrupt routine. 2. do not set the vca20 bit to 0 with the instruction immediately after setting the vca20 bit to 1. also, do not do the opposit e. 3. when the vca20 bit is set to 1, do not set the cm10 bit to 1 (stop mode). 4. when entering wait mode, follow 10.7.2 wait mode . handling procedure of internal power low consumption enabled by vca20 bit enter low-speed clock mode or low-speed on-chip oscillator mode stop xin clock and high-speed on-chip oscillator clock vca20 1 (internal power low consumption enabled) (2, 3) enter wait mode (4) vca20 0 (internal power low consumption disabled) (2) start xin clock or high-speed on-chip oscillator clock (wait until xin clock oscillation stabilizes) enter high-speed clock mode or high-speed on-chip oscillator mode in interrupt routine vca20 0 (internal power low consumption disabled) (2) start xin clock or high-speed on-chip oscillator clock enter high-speed clock mode or high-speed on-chip oscillator mode enter low-speed clock mode or low-speed on-chip oscillator mode exit wait mode by interrupt stop xin clock and high-speed on-chip oscillator clock vca20 1 (internal power low consumption enabled) (2, 3) interrupt handling completed step (1) step (2) step (3) step (4) step (5) step (6) step (7) step (8) step (5) step (6) step (7) step (8) (wait until xin clock oscillation stabilizes) step (1) step (2) step (3) if it is necessary to start the high-speed clock or the high-speed on-chip oscillator in the interrupt routine, execute steps (5) to (7) in the interrupt routine. if the high-speed clock or high-speed on-chip oscillator is started in the interrupt routine, execute steps (1) to (3) at the last of the interrupt routine. (note 1) interrupt handling vca20: bit in vca2 register r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 89 of 453 rej09b0278-0210 the clocks generated by the clock generation circuits are described below. 10.1 xin clock this clock is supplied by the xin clock oscillation circuit. this clock is used as the clock source for the cpu and peripheral function clocks. the xin cloc k oscillation circuit is configured by connecting a resonator between the xin and xout pins. the xin clock oscillation circu it includes an on-chip feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the chip. the xin clock oscillation circuit may also be configur ed by feeding an externally generated clock to the xin pin. figure 10.11 shows examples of xin clock connection circuit. in reset and after reset, the xin clock stops. the xin clock starts oscillat ing when the cm05 bit in the cm0 register is set to 0 (xin clock oscillates) after setting the cm01 bit in the cm0 register to 1 (xin cloc k) and the cm13 bit in the cm1 register to 1 (xin- xout pin). to use the xin clock for the cpu clock source, set the ocd2 bit in the ocd register to 0 (select xin clock) after the xin clock is oscillating stably. the power consumption can be reduced by setting the cm05 bit in the cm0 register to 1 (xin clock stops) if the ocd2 bit is set to 1 (select on-chip oscillator clock). when an external clock is input to the xin pin are input, the xin clock does not stop if the cm05 bit is set to 1. if necessary, use an external circuit to stop the clock. this mcu has an on-chip feedback resistor and on-chip re sistor disable/enable switching is possible by the cm11 bit in the cm1 register. in stop mode, all clocks including the xin clock stop. refer to 10.5 power control for details. figure 10.11 examples of xi n clock connection circuit xin xout mcu (on-chip feedback resistor) rd (1) cout cin xin xout mcu (on-chip feedback resistor) externally derived clock vcc vss note: 1. insert a damping resistor if requi red. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the manufacturer of the oscillator. use high drive when oscillation starts and, if it is necessary to switch the oscillation drive capacity, do so after oscillation stabilizes. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between xin and xout following the instructions. to use this mcu of n, d version with supply voltage below vcc = 2.7 v, it is recommended to set the cm11 bit in the cm1 register to 1 (on-chip feedback resistor disabled), the cm15 bit to 1 (high drive capacity), and connect the feedback resistor to the chip externally. open ceramic resonator external circuit external clock input circuit rf (1) r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 90 of 453 rej09b0278-0210 10.2 on-chip oscillator clocks these clocks are supplied by the on -chip oscillators (high-speed on-chi p oscillator and a low-speed on-chip oscillator). the on-chip oscillator clock is sel ected by the fra01 bit in the fra0 register. 10.2.1 low-speed on-chi p oscillator clock the clock generated by the low-speed on-chip oscilla tor is used as the clock source for the cpu clock, peripheral function clock, foco, and foco-s. after reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as the cpu clock. if the xin clock stops oscillating when bits ocd1 to ocd0 in the ocd register ar e set to 11b, the low-speed on-chip oscillator automatically starts operatin g, supplying the necessary clock for the mcu. the frequency of the low-speed on-chip oscillator vari es depending on the supply voltage and the operating ambient temperature. application products must be de signed with sufficient margin to allow for frequency changes. 10.2.2 high-speed on-chip oscillator clock the clock generated by the high-speed on-chip oscillato r is used as the clock source for the cpu clock, peripheral function clock, foco, foco-f, and foco40m. to use the high-speed on-chip oscillator clock as the cl ock source for the cpu clock, peripheral clock, foco, and foco-f, set bits fra20 to fra22 in the fra2 register as follows: ? all divide ratio mode settings are supported when vcc = 3.0 to 5.5 v 000b to 111b (other than k version) ? divide ratio of 4 or more when vcc = 2.7 to 5.5 v or k version 010b to 111b ? divide ratio of 8 or more when vcc = 2.2 to 5.5 v (for n, d version only) 110b to 111b after reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. oscillation is started by setting the fra00 bit in the fra0 register to 1 (high-speed on-chip oscillator on). the frequency can be adjusted by registers fra1 and fra2. the frequency correction data (the value is the same as th at of the fra1 register af ter a reset) corresponding to the supply voltage ranges vcc = 2.7 to 5.5 v is stored in fra4 register. furthermore, the frequency correction data corresponding to the supply voltage ranges vcc = 2.2 to 5.5 v is stored in fra6 register (for n, d version only). to use separate correction values to match thes e voltage ranges, transfer them from fra4 or fra6 register to the fra1 register. the frequency correction data of 36.864 mhz is stored in the fra7 register (for n, d version only). to set the frequency of the high-speed on-chip oscillator to 36. 864 mhz, transfer the co rrection value in the fra7 register to the fra1 register before use. this enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interf ace is used in uart mode (refer to table 15.7 bit rate setting example in uart mode (internal clock selected) ). since there are differences in the amount of frequency adjustment among the bits in the fra1 register, make adjustments by changing the settings of individual bits. ad just the fra1 register so that the frequency of the high-speed on-chip oscillator clock will be 40 mhz or less. r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 91 of 453 rej09b0278-0210 10.3 xcin clock (for n, d version only) this clock is supplied by the xcin clock oscillation circuit. this clock is used as the clock source for the cpu clock, peripheral function clock. the xcin clock osc illation circuit is configured by connecting a resonator between the xcin and xcout pins. the xcin clock oscilla tion circuit includes an on-chip a feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed in the chip. the xcin clock oscillation circuit may also be co nfigured by feeding an extern ally generated clock to the xcin pin. figure 10.12 shows examples of xcin clock connection circuits. during and after reset, the xcin clock stops. the xcin clock starts oscillating when the cm01 bit in the cm0 register is set to 1 (xcin clock) and the cm04 bit in the cm0 register is set to 1 (xcin-xcout pin). to use the xcin clock for the cpu clock source, set the ocd2 bit in the ocd register to 0 (selects xin clock) after the xcin clock is oscillating stably. this mcu has an on-chip feedback resistor and on-chip re sistor disable/enable switching is possible by the cm12 bit in the cm1 register. in stop mode, all clocks including the xcin clock stop. refer to 10.5 power control for details. figure 10.12 examples of xcin clock connection circuits xcin xcout mcu (on-chip feedback resistor) rd (1) cout cin xcin xcout mcu (on-chip feedback resistor) externally derived clock vcc vss note: 1. insert a damping resistor and feedback resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by t he manufacturer of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between xcin and xcout following the instructions. open external crystal oscillator circuit external clock input circuit rf (1) r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 92 of 453 rej09b0278-0210 10.4 cpu clock and peri pheral function clock there are a cpu clock to operate the cpu and a peripheral function clock to operate the peripheral functions. refer to figure 10.1 clock generation circuit . 10.4.1 system clock the system clock is the clock source for the cpu and peripheral function clocks . either the xin clock and xcin clock or the on-chip oscillator clock can be se lected. (for j, k version, the xcin clock cannot be selected.) 10.4.2 cpu clock the cpu clock is an operating cl ock for the cpu and watchdog timer. the system clock can be divided by 1 (no division), 2, 4, 8, or 16 to produce the cpu clock. use the cm06 bit in the cm0 register and bits cm16 to cm17 in the cm1 register to select the value of the division. use the xcin clock while the xcin clock oscillation stabilizes. after reset, the low-speed on-chip oscillator clock divided by 8 provides the cpu clock. when entering stop mode from high-speed clock mode , the cm06 bit is set to 1 (divide-by-8 mode). (for j, k version, the xcin clock cannot be selected.) 10.4.3 peripheral function clo ck (f1, f2, f4, f8, and f32) the peripheral function clock is the operating clock for the peripheral functions. the clock fi (i = 1, 2, 4, 8, and 32) is generated by th e system clock divided by i. the clock fi is used for timers ra, rb, rc, and re, the serial interface and the a/d converter. when the wait instruction is execute d after setting the cm02 bit in the cm0 register to 1 (peripheral function clock stops in wait mode), the clock fi stop. 10.4.4 foco foco is an operating clock for the peripheral functions. foco runs at the same frequency as the on-chip oscill ator clock and can be used as the source for timer ra. when the wait instructio n is executed, the clocks foco does not stop. 10.4.5 foco40m foco40m is used as the count source for timer rc. foco40m is generated by the high-speed on-chip oscillator and supplied by setting the fra00 bit to 1. when the wait instructio n is executed, the clock foco40m does not stop. foco40m can be used with supply voltage vcc = 3.0 to 5.5 v. 10.4.6 foco-f foco-f is used as the count source for the a/d conv erter. foco-f is generated by the high-speed on-chip oscillator and supplied by setting the fra00 bit to 1. when the wait instructio n is executed, the clock foco-f does not stop. 10.4.7 foco-s foco-s is an operating clock for the watchdog timer a nd voltage detection circuit. foco-s is supplied by setting the cm14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed on- chip oscillator. when the wait instruction is executed or in count source protect mode of the watchdog timer, foco-s does not stop. r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 93 of 453 rej09b0278-0210 10.4.8 fc4 and fc32 the clock fc4 is used for timer re and the clock fc32 is used for timer ra. use fc4 and fc32 while the xcin clock oscillation stabilizes. (for j, k version, fc4 and fc32 cannot be used.) 10.4.9 foco128 foco128 is generated by foco divided by 128. the clock foco128 is used for capture signal of timer rc?s trcgra register. r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 94 of 453 rej09b0278-0210 10.5 power control there are three power control modes. al l modes other than wait mode and stop mode are referred to as standard operating mode. 10.5.1 standard operating mode standard operating mode is furt her separated into four modes. in standard operating mode, the cpu clock and the peri pheral function clock are supplied to operate the cpu and the peripheral function clocks. power consump tion control is enabled by controlling the cpu clock frequency. the higher the cpu clock frequency, the mo re processing power increases. the lower the cpu clock frequency, the more power consumption decrease s. when unnecessary oscillator circuits stop, power consumption is further reduced. before the clock sources for the cpu clock can be switch ed over, the new clock source needs to be oscillating and stable. if the new clock source is the xin clock or xcin clock, allow suffic ient wait time in a program until oscillation is stabilized before exiting. ? : can be 0 or 1, no change in outcome note: 1. for n, d version only. table 10.2 settings and modes of clock associated bits modes ocd register cm1 register cm0 register fra0 register ocd2 cm17, cm16 cm14 cm13 cm06 cm05 cm04 cm01 fra01 fra00 high-speed clock mode no division 0 00b ? 100 ? 0 ?? divide-by-2 0 01b ? 100 ? 0 ?? divide-by-4 0 10b ? 100 ? 0 ?? divide-by-8 0 ?? 110 ? 0 ?? divide-by-16 0 11b ? 100 ? 0 ?? low-speed clock mode (1) no division 0 00b ?? 0 ? 11 ?? divide-by-2 0 01b ?? 0 ? 11 ?? divide-by-4 0 10b ?? 0 ? 11 ?? divide-by-8 0 ??? 1 ? 11 ?? divide-by-16 0 11b ?? 0 ? 11 ?? high-speed on-chip oscillator mode no division 1 00b ?? 0 ??? 11 divide-by-2 1 01b ?? 0 ??? 11 divide-by-4 1 10b ?? 0 ??? 11 divide-by-8 1 ??? 1 ??? 11 divide-by-16 1 11b ?? 0 ??? 11 low-speed on-chip oscillator mode no division 1 00b 0 ? 0 ??? 0 ? divide-by-2 1 01b 0 ? 0 ??? 0 ? divide-by-4 1 10b 0 ? 0 ??? 0 ? divide-by-8 1 ? 0 ? 1 ??? 0 ? divide-by-16 1 11b 0 ? 0 ??? 0 ? r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 95 of 453 rej09b0278-0210 10.5.1.1 high-speed clock mode the xin clock divided by 1 (no division) , 2, 4, 8, or 16 provides the cpu clock. set the cm06 bit to 1 (divide- by-8 mode) when transiting to high-speed on-chip oscill ator mode, low-speed on-chip oscillator mode. if the cm14 bit is set to 0 (low-speed on-c hip oscillator on) or the fra00 bit in the fra0 register is set to 1 (high- speed on-chip oscillator on), foco can be used as timer ra. when the fra00 bit is set to 1, foco40m can be used as timer rc. when the cm14 bit is set to 0 (low-speed on-chip oscill ator on), foco-s can be used as the watchdog timer and voltage detection circuit. 10.5.1.2 low-speed clock mode (for n, d version only) the xcin clock divided by 1 (no division), 2, 4, 8, or 16 provides the cpu clock. set the cm06 bit to 1 (divide by-8 mode) when transiting to high-speed on-chip oscill ator mode, low-speed on-chip oscillator mode. if the cm14 bit is set to 0 (low-speed on-chip oscillator on) or the fra00 bit in the fra0 register is set to 1 (high speed on-chip oscillator on), foco can be used as timer ra. when the fra00 bit is set to 1, foco40m can be used as timer rc. when the cm14 bit is set to 0 (low-speed on-chip oscill ator on), foco-s can be used as the watchdog timer and voltage detection circuit. in this mode, stopping the xin clock and high-speed on-chip oscillator, and setting the fmr47 bit in the fmr4 register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation. to enter wait mode from low-speed clock mode, setting th e vca20 bit in the vca2 register to 1 (internal power low consumption enabled) enables lower consumption current in wait mode. when enabling reduced internal power consumption using the vca20 bit, follow figure 10.14 procedure for enabling reduced internal pow er consumption using vca20 bit . 10.5.1.3 high-speed on -chip oscillator mode the high-speed on-chip oscillator is used as the on-chip oscillator clock when the fra00 bit in the fra0 register is set to 1 (high-speed on-chip oscillator on) and the fra01 bit in the fra0 register is set to 1. the on- chip oscillator divided by 1 (no division), 2, 4, 8, or 16 provides the cpu clock. set the cm06 bit to 1 (divide- by-8 mode) when transiting to high-speed clock mode. if the fra00 bit is set to 1, foco40m can be used as timer rc. when the cm14 bit is set to 0 (low-speed on-chip oscill ator on), foco-s can be used as the watchdog timer and voltage detection circuit. 10.5.1.4 low-speed on-chip oscillator mode if the cm14 bit in the cm1 register is set to 0 (low-speed on-chip oscillator on) or the fra01bit in the fra0 register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock. the on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the cpu clock. the on-chip oscillator clock is also the clock source for the peri pheral function clocks. set the cm06 bit to 1 (divide-by-8 mode) when transiting to high-speed clock mode. when the fra00 bit is set to 1, foco40m can be used as timer rc. when the cm14 bit is set to 0 (low-speed on-chip oscill ator on), foco-s can be used as the watchdog timer and voltage detection circuit. in this mode, stopping the xin clock and high-speed on-chip oscillator, and setting the fmr47 bit in the fmr4 register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation. to enter wait mode from low-speed on-chip oscillator m ode, setting the vca20 bit in the vca2 register to 1 (internal power low consumption enabled) enables lower consumption current in wait mode. when enabling reduced internal power consumption using the vca20 bit, follow figure 10.14 procedure for enabling reduced internal pow er consumption using vca20 bit . r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 96 of 453 rej09b0278-0210 10.5.2 wait mode since the cpu clock stops in wait mode, the cpu, which operates using the cp u clock, and the watchdog timer, when count source protection mode is disabled, st op. the xin clock, xcin clock, and on-chip oscillator clock do not stop and the peripheral functions using these clocks continue operating. 10.5.2.1 peripheral functi on clock stop function if the cm02 bit is set to 1 (peripheral function clock stops in wait mode), the f1, f2, f4, f8, and f32 clocks stop in wait mode. this reduces power consumption. 10.5.2.2 entering wait mode the mcu enters wait mode when the wait instruction is executed. when the ocd2 bit in the ocd register is set to 1 (on- chip oscillator selected as system clock), set the ocd1 bit in the ocd register to 0 (oscillation stop det ection interrupt disabled) before executing the wait instruction. if the mcu enters wait mode while the ocd1 bit is set to 1 (oscillation stop detection interrupt enabled), current consumption is not reduced because the cpu clock does not stop. 10.5.2.3 pin status in wait mode the i/o port is the status before wait mode was entered is maintained. r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 97 of 453 rej09b0278-0210 10.5.2.4 exiting wait mode the mcu exits wait mode by a reset or a peripheral function interrupt. the peripheral function interrupts are affected by the cm02 bit. when the cm02 bit is set to 0 (peripheral function clock does not stop in wait mode), all periphera l function interrupts can be used to exit wait mode. when the cm02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip oscillator clock can be used to exit wait mode. table 10.3 lists interrupts to exit wait mode and usage conditions. note: 1. for n, d version only. table 10.3 interrupts to exit wait mode and usage conditions interrupt cm02 = 0 cm02 = 1 serial interface interrupt us able when operating with internal or external clock usable when operating with external clock clock synchronous serial i/o with chip select interrupt / i 2 c bus interface interrupt usable in all modes (do not use) key input interrupt usable usable a/d conversion interrupt usable in one-shot mode (do not use) timer ra interrupt usable in all modes can be used if there is no filter in event counter mode. usable by selecting foco or fc32 (1) as count source. timer rb interrupt usable in all modes (do not use) timer rc interrupt usable in all modes (do not use) timer re interrupt usable in all modes usable when operating in real time clock mode (1) int interrupt usable usable (int0 , int1 , int3 can be used if there is no filter.) voltage monitor 1 interrupt usable usable voltage monitor 2 interrupt usable usable oscillation stop detection interrupt usable (do not use) r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 98 of 453 rej09b0278-0210 figure 10.13 shows the time from wait mode to interrupt routine execution. when using a peripheral function interrupt to exit wait mode, set up the following before executing the wait instruction. (1) set the interrupt priority level in bits ilvl2 to il vl0 in the interrupt control registers of the peripheral function interrupts to be used for exiting wait mode. set bits ilvl2 to ilvl0 of the peripheral function interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled). (2) set the i flag to 1. (3) operate the peripheral function to be used for exiting wait mode. when exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request generation and interrupt routine execution is determined by the settings of the fmstp bit in the fmr0 register, as described in figure 10.13. the cpu clock, when exiting wait mode by a peripheral func tion interrupt, is the same clock as the cpu clock when the wait instru ction is executed. figure 10.13 time from wait mode to interrupt routine execution wait mode flash memory activation sequence t1 cpu clock restart sequence t2 interrupt sequence t3 interrupt request generated time for interrupt sequence (t3) remarks time until flash memory is activated (t1) time until cpu clock is supplied (t2) period of cpu clock 20 cycles same as above following total time is the time from wait mode until an interrupt routine is executed. period of system clock 12 cycles + 30 s (max.) period of system clock 12 cycles period of cpu clock 6 cycles same as above fmstp bit fmr0 register 0 (flash memory operates) 1 (flash memory stops) r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 99 of 453 rej09b0278-0210 10.5.2.5 reducing intern al power consumption internal power consumption can be reduced by using lo w-speed clock mode (for n, d version only) or low- speed on-chip oscillator mode. figure 10.14 shows th e procedure for enabling reduced internal power consumption using vca20 bit. when enabling reduced internal power consumption using the vca20 bit, follow figure 10.14 procedure for enabling reduced internal pow er consumption using vca20 bit . figure 10.14 procedure for enabling reduced internal power consumption using vca20 bit notes: 1. execute this routine to handle all interrupts generated in wait mode. however, this does not apply if it is not necessary to star t the high-speed clock or high-speed on-chip oscillator during the i nterrupt routine. 2. do not set the vca20 bit to 0 with the instruction immediately after setting the vca20 bit to 1. also, do not do the opposit e. 3. when the vca20 bit is set to 1, do not set the cm10 bit to 1 (stop mode). 4. when entering wait mode, follow 10.7.2 wait mode . handling procedure of internal power low consumption enabled by vca20 bit enter low-speed clock mode or low-speed on-chip oscillator mode stop xin clock and high-speed on-chip oscillator clock vca20 1 (internal power low consumption enabled) (2, 3) enter wait mode (4) vca20 0 (internal power low consumption disabled) (2) start xin clock or high-speed on-chip oscillator clock (wait until xin clock oscillation stabilizes) enter high-speed clock mode or high-speed on-chip oscillator mode in interrupt routine vca20 0 (internal power low consumption disabled) (2) start xin clock or high-speed on-chip oscillator clock enter high-speed clock mode or high-speed on-chip oscillator mode enter low-speed clock mode or low-speed on-chip oscillator mode exit wait mode by interrupt stop xin clock and high-speed on-chip oscillator clock vca20 1 (internal power low consumption enabled) (2, 3) interrupt handling completed step (1) step (2) step (3) step (4) step (5) step (6) step (7) step (8) step (5) step (6) step (7) step (8) (wait until xin clock oscillation stabilizes) step (1) step (2) step (3) if it is necessary to start the high-speed clock or the high-speed on-chip oscillator in the interrupt routine, execute steps (5) to (7) in the interrupt routine. if the high-speed clock or high-speed on-chip oscillator is started in the interrupt routine, execute steps (1) to (3) at the last of the interrupt routine. (note 1) interrupt handling vca20: bit in vca2 register r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 100 of 453 rej09b0278-0210 10.5.3 stop mode since the oscillator circuits stop in stop mode, the cp u clock and peripheral function clock stop and the cpu and peripheral functions that use these clocks stop operat ing. the least power required to operate the mcu is in stop mode. if the voltage applied to the vcc pin is vram or more, the contents of internal ram is maintained. the peripheral functions clocked by external signals continue operating. table 10.4 lists interrupts to exit stop mode and usage conditions. note: 1. for n, d version only. 10.5.3.1 entering stop mode the mcu enters stop mode when the cm10 bit in the cm1 register is set to 1 (all clocks stop). at the same time, the cm06 bit in the cm0 register is set to 1 (divid e-by-8 mode), the cm03 bit in the cm0 register is set to 1 (xcin clock oscillator circuit drive capacity high), an d the cm15 bit in the cm1 register is set to 1 (xin clock oscillator circuit drive capacity high). when using stop mode, set bits ocd1 to ocd0 to 00b before entering stop mode. 10.5.3.2 pin status in stop mode the status before wait mode was entered is maintained. however, when the cm01 bit in the cm0 register is set to 0 (xin clock) and the cm13 bit in the cm1 register is set to 1 (xin-xout pins), the xout(p4_7) pin is held ?h?. when the cm13 bit is set to 0 (input ports p4_6 and p4_7), the p4_7(xout pin) is held in input status. when the cm01 bit in the cm0 register is set to 1 (xci n clock) and the cm04 bit in the cm0 register is set to 1 (xcin clock oscillates), the xcout(p4_7) pin is held ?h?. when the cm04 bit is set to 0 (xin clock stops), the p4_7(xout pin) is held in input status. table 10.4 interrupts to exit stop mode and usage conditions interrupt usage conditions key input interrupt ? int0 , int1 , int3 interrupt can be used if there is no filter timer ra interrupt when there is no filter and external pulse is counted in event counter mode serial interface interrupt when external clock is selected voltage monitor 1 interrupt (1) usable in digital filter disabled mode (vw1c1 bit in vw1c register is set to 1) voltage monitor 2 interrupt usable in digital filter disabled mode (vw2c1 bit in vw2c register is set to 1) r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 101 of 453 rej09b0278-0210 10.5.3.3 exiting stop mode the mcu exits stop mode by a reset or peripheral function interrupt. figure 10.15 shows the time from stop mode to interrupt routine execution. when using a peripheral function interrupt to exit stop mode, set up the following before setting the cm10 bit to 1. (1) set the interrupt priority level in bits ilvl2 to ilvl 0 of the peripheral function interrupts to be used for exiting stop mode. set bits ilvl2 to ilvl0 of the peri pheral function interrupts that are not to be used for exiting stop mode to 000b (interrupt disabled). (2) set the i flag to 1. (3) operates the peripheral function to be used for exiting stop mode. when exiting by a peripheral function interrupt, the in terrupt sequence is executed when an interrupt request is generated and the cpu clock supply is started. if the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral function interrupt, the cpu clock becomes the previous system clock divided by 8. figure 10.15 time from stop mode to interrupt routine execution t2 following total time of t0 to t4 is the time from stop mode until an interrupt handling is executed. flash memory activation sequence cpu clock restart sequence interrupt sequence oscillation time of cpu clock source used immediately before stop mode stop mode t3 t4 internal power stability time t1 t0 interrupt request generated 150 s (max.) time until flash memory is activated (t2) time until cpu clock is supplied (t3) time for interrupt sequence (t4) remarks fmstp bit fmr0 register period of cpu clock 6 cycles period of cpu clock 20 cycles period of system clock 12 cycles + 30 s (max.) period of system clock 12 cycles same as above same as above 0 (flash memory operates) 1 (flash memory stops) r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 102 of 453 rej09b0278-0210 figure 10.16 shows the state transitions in power control mode (when the cm01 bit in the cm0 register is set to 0 (xin clock)). figure 10.17 shows the state transitions in power control mode (when the cm01 bit in the cm0 register is set to 1 (xcin clock)). figure 10.16 state transitions in power control mode (when the cm01 bit in the cm0 register is set to 0 (xin clock)) cm10 = 1 cpu operation stops stop mode state transitions in power control mode (when the cm01 bit in the cm0 register is set to 0 (xin clock)) reset wait mode low-speed on-chip oscillator mode cm14 = 0 ocd2 = 1 fra01 = 0 high-speed on-chi p oscillator mode ocd2 = 1 fra00 = 1 fra01 = 1 high-speed clock mode cm05 = 0 cm13 = 1 ocd2 = 0 standard operating mode cm14 = 0 ocd2 = 1 fra01 = 0 cm05 = 0 cm13 = 1 ocd2 = 0 cm05 = 0 cm13 = 1 ocd2 = 0 ocd2 = 1 fra00 = 1 fra01 = 1 fra00 = 1 fra01 = 1 cm14 = 0 fra01 = 0 all oscillators stop interrupt wait instruction interrupt cm05: bit in cm0 register cm13, cm14: bits in cm1 register ocd2: bit in ocd register fra00, fra01: bits in fra0 register r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 103 of 453 rej09b0278-0210 figure 10.17 state transitions in power control mode (when the cm01 bit in the cm0 register is set to 1 (xcin clock)) cm10 = 1 cpu operation stops stop mode reset wait mode low-speed on-chip oscillator mode cm14 = 0 ocd2 = 1 fra01 = 0 high-speed on-chip oscillator mode ocd2 = 1 fra00 = 1 fra01 = 1 standard operating mode fra00 = 1 fra01 = 1 cm14 = 0 fra01 = 0 all oscillators stop interrupt wait instruction interrupt cm04: bit in cm0 register cm14: bit in cm1 register ocd2: bit in ocd register fra00, fra01: bits in fra0 register low-speed clock mode cm04 = 1 ocd2 = 0 cm14 = 0 ocd2 = 1 fra01 = 0 cm04 = 1 ocd2 = 0 ocd2 = 1 fra00 = 1 fra01 = 1 cm04 = 1 ocd2 = 0 state transitions in power control mode (when the cm01 bit in the cm0 register is se t to 1 (xcin clock)) (for n, d version only) r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 104 of 453 rej09b0278-0210 10.6 oscillation stop detection function the oscillation stop detection function detects the stop of the xin clock oscillating circuit. the oscillation stop detection function can be enabled and disabl ed by the ocd0 bit in the ocd register. table 10.5 lists the specifications of oscillation stop detection function. when the xin clock is the cpu clock sour ce and bits ocd1 to ocd0 are set to 11b, the system is placed in the following state if the xin clock stops. ? ocd2 bit in ocd register = 1 (on-chip oscillator clock selected) ? ocd3 bit in ocd register = 1 (xin clock stops) ? cm14 bit in cm1 register = 0 (low-speed on-chip oscillator oscillates) ? oscillation stop detection interrupt request is generated. 10.6.1 how to use oscillat ion stop detection function ? the oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage monitor 2 interrupt, and the watchdog timer interrupt. wh en using the oscillation stop detection interrupt and watchdog timer interrupt, the interrupt source needs to be determined. table 10.6 lists the determining interrupt source for oscillation stop detection, watchdog timer, voltage monitor 1, and voltage monitor 2 interrupts. figure 10.19 shows the example of determining interrupt source for oscillation stop detection, watchdog timer, voltage monitor 1, or voltage monitor 2 interrupt (n, d version). figure 10.20 shows the example of determining interrupt source for oscillation stop detection, watchdog timer, voltage monitor 1, or voltage monitor 2 interrupt (j, k version). ? when the xin clock restarts after oscillation stop, switch the xin clock to the clock source of the cpu clock and peripheral functions by a program. figure 10.18 shows the procedure for switching cl ock source from low-speed on-chip oscillator to xin clock. ? to enter wait mode while using the oscillation stop detection function, set the cm02 bit to 0 (peripheral function clock does not stop in wait mode). ? since the oscillation stop detection function is a function for cases where the xin clock is stopped by an external cause, set bits ocd1 to ocd0 to 00b when the xin clock stops or is started by a program, (stop mode is selected or the cm05 bit is changed). ? this function cannot be used when the xin clock freque ncy is 2 mhz or below. in this case, set bits ocd1 to ocd0 to 00b. ? to use the low-speed on-chip oscill ator clock for the cpu clock and clock sources of peripheral functions after detecting the oscillation stop, set the fra01 bit in the fra0 register to 0 (low-speed on-chip oscillator selected) and bits ocd1 to ocd0 to 11b. to use the high-speed on-chip oscillator clock for th e cpu clock and clock sources of peripheral functions after detecting the oscillation stop, set the fra00 bit to 1 (high-speed on-chip oscillator on) and the fra01 bit to 1 (high-speed on-chip oscillator select ed) and then set bits ocd1 to ocd0 to 11b. table 10.5 specifications of oscillation stop detection function item specification oscillation stop detection clock and frequency bandwidth f(xin) 2 mhz enabled condition for oscillation stop detection function set bits ocd1 to ocd0 to 11b operation at oscillation stop detection osc illation stop detection interrupt is generated r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 105 of 453 rej09b0278-0210 note: 1. for n, d version only. figure 10.18 procedure for switching clock sour ce from low-speed on-chip oscillator to xin clock table 10.6 determining interrupt source for oscillation stop detection, watchdog timer, voltage monitor 1, and voltage monitor 2 interrupts generated inte rrupt source bit showing interrupt cause oscillation stop detection ((a) or (b)) (a) ocd3 bit in ocd register = 1 (b) ocd1 to ocd0 bits in ocd register = 11b and ocd2 bit = 1 watchdog timer vw2c3 bit in vw2c register = 1 voltage monitor 1 (1) vw1c2 bit in vw1c register = 1 voltage monitor 2 vw2c2 bit in vw2c register = 1 ocd3 to ocd0: bits in ocd register switch to xin clock multiple confirmations that ocd3 bit is set to 0 (xin clock oscillates) ? set ocd1 to ocd0 bits to 00b set ocd2 bit to 0 (select xin clock) end yes no r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 106 of 453 rej09b0278-0210 figure 10.19 example of determining interrupt source for oscillation stop detection, watchdog timer, voltage monitor 1, or voltage monitor 2 interrupt (n, d version) interrupt sources judgement ocd3 = 1 ? (xin clock stopped) ocd1 = 1 (oscillation stop detection interrupt enabled) and ocd2 = 1 (on-chip oscillator clock selected as system clock) ? vw2c3 = 1 ? (watchdog timer underflow) vw2c2 = 1 ? (passing vdet2) to oscillation stop detection interrupt routine to voltage monitor 1 interrupt routine to voltage monitor 2 interrupt routine to watchdog timer interrupt routine no yes no yes no yes no yes note: 1. this disables multiple osc illation stop detec tion interrupts. ocd1 to ocd3: bits in ocd register vw2c2, vw2c3: bits in vw2c register set ocd1 bit to 0 (oscillation stop detection interrupt disabled). (1) r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 107 of 453 rej09b0278-0210 figure 10.20 example of determining interrupt source for oscillation stop detection, watchdog timer, voltage monitor 1, or voltage monitor 2 interrupt (j, k version) interrupt sources judgement ocd3 = 1 ? (xin clock stopped) ocd1 = 1 (oscillation stop detection interrupt enabled) and ocd2 = 1 (on-chip oscillator clock selected as system clock) ? vw2c3 = 1 ? (watchdog timer underflow) to oscillation stop detection interrupt routine to voltage monitor 2 interrupt routine to watchdog timer interrupt routine no yes no yes no yes note: 1. this disables multiple oscillation stop detection interrupts. ocd1 to ocd3: bits in ocd register vw2c3: bit in vw2c register set ocd1 bit to 0 (oscillation stop detection interrupt disabled). (1) r8c/26 group, r8c/27 group 10. clock generation circuit rev.2.10 sep 26, 2008 page 108 of 453 rej09b0278-0210 10.7 notes on clock generation circuit 10.7.1 stop mode when entering stop mode, set the fmr01 bit in the fmr0 register to 0 (cpu rewrite mode disabled) and the cm10 bit in the cm1 register to 1 (stop mode). an instruction queue pre-reads 4 bytes from the instruction which sets the cm10 bit to 1 (stop mode) and the program stops. insert at least 4 nop instructions following the jmp.b instruction after the instruction which sets the cm10 bit to 1. ? program example to enter stop mode bclr 1,fmr0 ; cpu rewrite mode disabled bset 0,prcr ; protect disabled fset i ; enable interrupt bset 0,cm1 ; stop mode jmp.b label_001 label_001 : nop nop nop nop 10.7.2 wait mode when entering wait mode, set the fmr01 bit in the fm r0 register to 0 (cpu re write mode disabled) and execute the wait instruction. an instruction queue pre-reads 4 bytes from the wait instruction and the program stops. insert at least 4 nop instructions after the wait instruction. ? program example to execute the wait instruction bclr 1,fmr0 ; cpu rewrite mode disabled fset i ; enable interrupt wait ; wait mode nop nop nop nop 10.7.3 oscillation stop detection function since the oscillation stop detection function cannot be used if the xin clock frequency is 2 mhz or below, set bits ocd1 to ocd0 to 00b. 10.7.4 oscillation circuit constants ask the manufacturer of the oscillator to specify th e best oscillation circuit constants for your system. to use this mcu with supply voltage below vcc = 2.7 v, it is recommended to set the cm11 bit in the cm1 register to 1 (on-chip feedback resistor disabled), the cm15 bit to 1 (high drive capacity), and connect the feedback resistor to the chip externally. r8c/26 group, r8c/27 group 11. protection rev.2.10 sep 26, 2008 page 109 of 453 rej09b0278-0210 11. protection the protection function protects important registers from be ing easily overwritten when a program runs out of control. figure 11.1 shows the prcr register. the register s protected by the prcr register are listed below. ? registers protected by prc0 bit: regist ers cm0, cm1, ocd, fra0, fra1, and fra2 ? registers protected by prc1 bit: registers pm0 and pm1 ? registers protected by prc2 bit: pd0 register ? registers protected by prc3 bit: registers vca2, vw0c, vw1c, and vw2c figure 11.1 prcr register protect registe r symbol address after reset prcr 000ah 00h bit symbol bit name function rw note: 1. this bit is set to 0 after w riting 1 to the prc2 bit and executing a w rite to any address. since the other bits are not set to 0, set them to 0 by a program. prc2 protect bit 2 writing to the pd0 register is enabled. 0 : disables w riting 1 : enables w riting (1) rw rw ? (b5-b4) reserved bits set to 0. rw prc0 rw prc1 rw protect bit 0 writing to registers cm0, cm1, ocd, fra0, fra1, and fra2 is enabled. 0 : disables w riting 1 : enables w riting protect bit 1 writing to registers pm0 and pm1 is enabled. 0 : disables w riting 1 : enables w riting 00 b3 b2 b1 b0 b7 b6 b5 b4 ro prc3 protect bit 3 writing to registers vca2, vw0c, vw1c, and vw2c is enabled. 0 : disables w riting 1 : enables w riting ? (b7-b6) reserved bits when read, the content is 0. r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 110 of 453 rej09b0278-0210 12. interrupts 12.1 interrupt overview 12.1.1 types of interrupts figure 12.1 shows the types of interrupts. figure 12.1 types of interrupts ? maskable interrupts: the interrupt enable flag (i flag) enables or disables these interrupts. the interrupt priority order can be changed based on the interrupt priority level. ? non-maskable interrupts: the interr upt enable flag (i flag) does not enable or disabl e these interrupts. the interrupt priority order cannot be changed based on interrupt priority level. interrupts (non-maskable interrupts) hardware software (non-maskable interrupts) (maskable interrupts) special peripheral functions (1) undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction watchdog timer oscillation stop detection voltage monitor 1 voltage monitor 2 single step (2) address break (2) address match notes: 1. peripheral function interrupts in the mcu are used to generate peripheral interrupts. 2. do not use this interrupt. this is for use with development tools only. r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 111 of 453 rej09b0278-0210 12.1.2 software interrupts a software interrupt is generated when an instruc tion is executed. software interrupts are non-maskable. 12.1.2.1 undefined instruction interrupt the undefined instruction interrupt is generated when the und instruction is executed. 12.1.2.2 overflow interrupt the overflow interrupt is generated when the o flag is set to 1 (arithmetic operation overflow) and the into instruction is executed. inst ructions that set the o flag are: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, and sub. 12.1.2.3 brk interrupt a brk interrupt is generated when the brk instruction is executed. 12.1.2.4 int instruction interrupt an int instruction interrupt is generated when the int instruction is executed. th e int instruction can select software interrupt numbers 0 to 63. so ftware interrupt numbers 3 to 31 are assigned to the peripheral function interrupt. therefore, the mcu executes the same interrupt routine when the int instruction is executed as when a peripheral function interrupt is generated. for so ftware interrupt numbers 0 to 31, the u flag is saved to the stack during instruction execution and the u flag is set to 0 (isp selected) befo re the interrupt sequence is executed. the u flag is restor ed from the stack when retu rning from the interrupt routine. for software interrupt numbers 32 to 63, the u flag does not change state du ring instruction execution, a nd the selected sp is used. r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 112 of 453 rej09b0278-0210 12.1.3 special interrupts special interrupts are non-maskable. 12.1.3.1 watchdog timer interrupt the watchdog timer interrupt is generated by the watch dog timer. for details of the watchdog timer, refer to 13. watchdog timer . 12.1.3.2 oscillation stop detection interrupt the oscillation stop detection interrupt is generated by th e oscillation stop detection function. for details of the oscillation stop detection function, refer to 10. clock generation circuit . 12.1.3.3 voltage monitor 1 interrupt (for n, d version only) the voltage monitor 1 interrupt is generated by the voltage detection circuit. for details of the voltage detection circuit, refer to 6. voltage detection circuit . 12.1.3.4 voltage monitor 2 interrupt the voltage monitor 2 interrupt is generated by the voltage detection circuit. for details of the voltage detection circuit, refer to 6. voltage detection circuit . 12.1.3.5 single-step interrupt, and address break interrupt do not use these interrupts. they are for use by development tools only. 12.1.3.6 address match interrupt the address match interrupt is generated immediately be fore executing an instruction that is stored at an address indicated by registers rmad0 to rmad1 when the aier0 or aier1 bit in the aier register is set to 1 (address match interrupt enable). for details of the address match interrupt, refer to 12.4 address match interrupt . 12.1.4 peripheral function interrupt the peripheral function interrupt is generated by the in ternal peripheral function of the mcu and is a maskable interrupt. refer to table 12.2 relocatable vector tables for sources of the peripheral function interrupt. for details of peripheral functions, refer to the de scriptions of individual peripheral functions. r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 113 of 453 rej09b0278-0210 12.1.5 interrupts and interrupt vectors there are 4 bytes in each vector. set the starting addre ss of an interrupt routine in each interrupt vector. when an interrupt request is acknowledged, the cpu branches to the address set in the co rresponding interrupt vector. figure 12.2 shows an interrupt vector. figure 12.2 interrupt vector 12.1.5.1 fixed vector tables the fixed vector tables are allocated addresses 0ffdch to 0ffffh. table 12.1 lists the fixed vector ta bles. the vector addresses (h) of fi xed vectors are used by the id code check function. for details, refer to 19.3 functions to prevent rewriting of flash memory . notes: 1. do not use these interrupts. they are for use by development tools only. 2. for n, d version only. table 12.1 fixed vector tables interrupt source vector addresses address (l) to (h) remarks reference undefined instruction 0ffdch to 0ffdfh interrupt on und instruction r8c/tiny series software manual overflow 0ffe0h to 0ffe3h interrupt on into instruction brk instruction 0ffe4h to 0ffe7h if the content of address 0ffe7h is ffh, program execution starts from the address shown by the vector in the relocatable vector table. address match 0ffe8h to 0ffebh 12.4 address match interrupt single step (1) 0ffech to 0ffefh watchdog timer, oscillation stop detection, voltage monitor 1 (2) , voltage monitor 2 0fff0h to 0fff3h 13. watchdog timer 10. clock generation circuit 6. voltage detection circuit address break (1) 0fff4h to 0fff7h (reserved) 0fff8h to 0fffbh reset 0fffch to 0ffffh 5. resets vector address (l) vector address (h) msb lsb low address mid address high address 0 0 0 0 0 0 0 0 0 0 0 0 r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 114 of 453 rej09b0278-0210 12.1.5.2 relocatable vector tables the relocatable vector tables occupy 256 bytes beginning from the starting address set in the intb register. table 12.2 lists the relocatable vector tables. notes: 1. these addresses are relative to those in the intb register. 2. the iicsel bit in the pmr register switches functions. 3. the i flag does not disable these interrupts. table 12.2 relocatable vector tables interrupt source vector addresses (1) address (l) to address (h) software interrupt number interrupt control register reference brk instruction (3) +0 to +3 (0000h to 0003h) 0 ? r8c/tiny series software manual (reserved) 1 to 2 ?? (reserved) 3 to 6 ?? timer rc +28 to +31 (001ch to 001fh) 7 trcic 14.3 timer rc (reserved) 8 to 9 ?? timer re +40 to +43 (0028h to 002bh) 10 treic 14.4 timer re (reserved) 11 to 12 ?? key input +52 to +55 (0034h to 0037h) 13 kupic 12.3 key input interrupt a/d +56 to +59 (0038h to 003bh) 14 adic 18. a/d converter clock synchronous serial i/o with chip select / i 2 c bus interface (2) +60 to +63 (003ch to 003fh) 15 ssuic/iicic 16.2 clock synchronous serial i/o with chip select (ssu), 16.3 i 2 c bus interface (reserved) 16 ?? uart0 transmit +68 to +71 (0044h to 0047h) 17 s0tic 15. serial interface uart0 receive +72 to +75 (0048h to 004bh) 18 s0ric uart1 transmit +76 to +79 (004ch to 004fh) 19 s1tic uart1 receive +80 to +83 (0050h to 0053h) 20 s1ric (reserved) 21 ?? timer ra +88 to +91 (0058h to 005bh) 22 traic 14.1 timer ra (reserved) 23 ?? timer rb +96 to +99 (0060h to 0063h) 24 trbic 14.2 timer rb int1 +100 to +103 (0064h to 0067h) 25 int1ic 12.2 int interrupt int3 +104 to +107 (0068h to 006bh) 26 int3ic (reserved) 27 ?? (reserved) 28 ?? int0 +116 to +119 (0074h to 0077h) 29 int0ic 12.2 int interrupt (reserved) 30 ?? (reserved) 31 ?? software interrupt (3) +128 to +131 (0080h to 0083h) to +252 to +255 (00fch to 00ffh) 32 to 63 ? r8c/tiny series software manual r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 115 of 453 rej09b0278-0210 12.1.6 interrupt control the following describes enabling and disabling the maskable interrupts and setting the priority for acknowledgement. the explanation does not apply to nonmaskable interrupts. use the i flag in the flg register, ip l, and bits ilvl2 to ilvl0 in each in terrupt control regi ster to enable or disable maskable interrupts. wh ether an interrupt is request ed is indicated by the ir bit in each interrupt control register. figure 12.3 shows the interrupt control register, fi gure 12.4 shows registers trcic and ssuic/iicic and figure 12.5 shows the intiic register (i=0, 1, 3). figure 12.3 interrupt control register interrupt control register (2) address after reset 004ah xxxxx000b 004dh xxxxx000b 004eh xxxxx000b 0051h xxxxx000b 0052h xxxxx000b 0053h xxxxx000b 0054h xxxxx000b 0056h xxxxx000b 0058h xxxxx000b bit symbol function rw notes: 1. 2. kupic adic s0tic s0ric symbol bit name interrupt priority level select bits interrupt request bit ilv l0 trbic s1tic s1ric tra ic treic rew rite the interrupt control register w hen the interrupt request w hich is applicable for its register is not generated. ref er to 12.6.5 changing interrupt control register contents . b7 b6 b5 b4 b3 b2 b1 b0 rw b2 b1 b0 0 0 0 : level 0 (interrupt disable) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 ilv l1 rw ilv l2 rw only 0 can be w ritten to the ir bit. do not w rite 1. ir 0 : requests no interrupt 1 : requests interrupt rw (1) ? (b7-b4) ? nothing is assigned. if necessary, set to 0. when read, the content is undefined. r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 116 of 453 rej09b0278-0210 figure 12.4 registers trcic and ssuic/iicic interrupt control register (1) address after reset 0047h xxxxx000b 004fh xxxxx000b bit symbol function rw notes: 1. 2. nothing is assigned. if necessary, set to 0. when read, the content is undefined. rw ir 0 : requests no interrupt 1 : requests interrupt ro interrupt priority level select bits interrupt request bit b3 b2 b1 b0 b7 b6 b5 b4 the iicsel bit in the pmr register sw itches functions. rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated. ref er to 12.6.5 changing interrupt control register contents . ilv l0 rw b2 b1 b0 0 0 0 : level 0 (interrupt disable) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 ilv l1 rw ? (b7-b4) ? ilv l2 symbol trcic ssuic/iicic (2) bit name r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 117 of 453 rej09b0278-0210 figure 12.5 intiic register (i=0, 1, 3) inti interrupt control register (i=0, 1, 3) (2) symbol address after reset int1ic 0059h xx00x000b int3ic 005ah xx00x000b int0ic 005dh xx00x000b bit symbol bit name function rw notes: 1. 2. 3. 4. rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated. ref er to 12.6.5 changing interrupt control register contents . if the intipl bit in the inten register is set to 1 (both edges), set the pol bit to 0 (selects fa lling edge). the ir bit may be set to 1 (requests interrupt) w hen the pol bit is rew ritten. refer to 12.6.4 changing interrupt sources. b7 b6 b5 b4 b3 b2 b1 b0 0 ilv l0 rw interrupt priority level select bits b2 b1 b0 0 0 0 : level 0 (interrupt disable) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 ilv l1 rw ilv l2 rw ir interrupt request bit 0 : requests no interrupt 1 : requests interrupt rw (1) pol polarity sw itch bit (4) 0 : selects falling edge 1 : selects rising edge (3) rw ? (b5) reserved bit set to 0. rw ? (b7-b6) ? nothing is assigned. if necessary, set to 0. when read, the content is undefined. only 0 can be w ritten to the ir bit. (do not w rite 1.) r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 118 of 453 rej09b0278-0210 12.1.6.1 i flag the i flag enables or disables maskab le interrupts. setting the i flag to 1 (enabled) enables maskable interrupts. setting the i flag to 0 (disabled) disables all maskable interrupts. 12.1.6.2 ir bit the ir bit is set to 1 (interrupt requested) when an interrupt request is generated. then, when the interrupt request is acknowledged and th e cpu branches to the corr esponding interrupt vector, the ir bit is set to 0 (= interrupt not requested). the ir bit can be set to 0 by a program. do not write 1 to this bit. however, the ir bit operations of the timer rc inte rrupt, clock synchronous serial i/o with chip select interrupt and the i 2 c bus interface interrupt are different. refer to 12.5 timer rc interrupt, clock synchronous serial i/o with chip select interrupts, and i 2 c bus interface interrupt (interrupts with multiple interrupt request sources) . 12.1.6.3 ilvl2 to ilvl0 bits and ipl interrupt priority levels can be set using bits ilvl2 to ilvl0. table 12.3 lists the settings of interrupt priority le vels and table 12.4 lists th e interrupt priority levels enabled by ipl. the following are conditions under which an interrupt is acknowledged: ?i flag = 1 ? ir bit = 1 ? interrupt priority level > ipl the i flag, ir bit, bits ilvl2 to il vl0, and ipl are independ ent of each other. they do not affect one another. table 12.3 settings of interrupt priority levels ilvl2 to ilvl0 bits interrupt priority level priority order 000b level 0 (interrupt disabled) ? 001b level 1 low 010b level 2 011b level 3 100b level 4 101b level 5 110b level 6 111b level 7 high table 12.4 interrupt priority levels enabled by ipl ipl enabled interrupt priority levels 000b interrupt level 1 and above 001b interrupt level 2 and above 010b interrupt level 3 and above 011b interrupt level 4 and above 100b interrupt level 5 and above 101b interrupt level 6 and above 110b interrupt level 7 and above 111b all maskable interrupts are disabled r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 119 of 453 rej09b0278-0210 12.1.6.4 interrupt sequence an interrupt sequence is performed between an inte rrupt request acknowledgement and interrupt routine execution. when an interrupt request is generated while an instruct ion is being executed, the cpu determines its interrupt priority level after the instruction is completed. the cpu starts the interrupt sequence from the following cycle. however, for the smovb, smovf, sstr, or rmpa instruc tions, if an interrupt request is generated while the instruction is being executed, the mcu suspends the instruction to start the interrupt sequence. the interrupt sequence is performed as indicated below. figure 12.6 shows the time requir ed for executing interrupt sequence. (1) the cpu gets interrupt information (interrupt num ber and interrupt request level) by reading address 00000h. the ir bit for the corresponding interr upt is set to 0 (interrupt not requested). (2) (2) the flg register is saved to a temporary register (1) in the cpu immediately before entering the interrupt sequence. (3) the i, d and u flags in the flg register are set as follows: the i flag is set to 0 (interrupts disabled). the d flag is set to 0 (single-step interrupt disabled). the u flag is set to 0 (isp selected). however, the u flag does not change state if an in t instruction for software interrupt number 32 to 63 is executed. (4) the cpu?s internal temporary register (1) is saved to the stack. (5) the pc is saved to the stack. (6) the interrupt priority level of the acknowledged interrupt is set in the ipl. (7) the starting address of the interrupt routine set in the interrupt vector is stored in the pc. after the interrupt sequence is completed, instructions are executed from the starting address of the interrupt routine. figure 12.6 time required for executing interrupt sequence notes: 1. this register cannot be used by user. 2. refer to 12.5 timer rc interrupt, clock synchronous serial i/o with chip select interrupts, and i 2 c bus interface interrupt (interrupts with multiple interrupt request sources) for the ir bit operations of the timer rc interrupt, clock synchronous serial i/o with chip se lect interrupt, and the i 2 c bus interface interrupt. 12345678910 11 12 13 14 15 16 17 18 19 20 cpu clock address bus data bus rd wr address 0000h undefined undefined undefined interrupt information sp-2 sp-1 sp-4 sp-3 vec vec+1 vec+2 pc sp-2 contents sp-1 contents sp-4 contents sp-3 contents vec contents vec+1 contents vec+2 contents the indeterminate state depends on the instruction queue buffer. a read cycle occurs when the instruction queue buffer is ready to acknowledge instructions. r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 120 of 453 rej09b0278-0210 12.1.6.5 interrupt response time figure 12.7 shows the interrupt response time. the interr upt response time is the period between an interrupt request generation and the execution of the first instructio n in the interrupt routine. the interrupt response time includes the period between interrup t request generation and the completion of execution of the instruction (refer to (a) in figure 12.7 ) and the period required to perform the in terrupt sequence (20 cycles, refer to (b) in figure 12.7 ). figure 12.7 interrupt response time 12.1.6.6 ipl change when inte rrupt request is acknowledged when an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the acknowledged interrupt is set in the ipl. when a software interrupt or special interrupt request is acknowledged, the level listed in table 12.5 is set in the ipl. table 12.5 lists the ipl value when software or special interrupt is acknowledged. note: 1. for n, d version only. table 12.5 ipl value when software or special interrupt is acknowledged interrupt source va lue set in ipl watchdog timer, oscillation stop detection, voltage monitor 1 (1) , voltage monitor 2, address break 7 software, address match, single-step not changed interrupt request is generated. interrupt request is acknowledged. instruction interrupt sequence instruction in interrupt routine time (a) 20 cycles (b) interrupt response time (a) period between interrupt request generation and the completion of execution of an instruction. the length of time varies depending on the instruction being executed. the divx instruction requires the longest time, 30 cycles (no wait and when the register is set as the divisor) (b) 21 cycles for address match and single-step interrupts. r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 121 of 453 rej09b0278-0210 12.1.6.7 saving a register in the interrupt sequence, the flg regi ster and pc are saved to the stack. after an extended 16 bits, 4 high-order bits in the pc and 4 high-order (ipl) and 8 low-order bits in the flg register, are saved to the stack, the 16 low-order bits in the pc are saved. figure 12.8 shows the stack state before and after acknowledgement of interrupt request. the other necessary registers are saved by a program at the beginning of the interrupt routine. the pushm instruction can save several registers in the register bank being currently used (1) with a single instruction. note: 1. selectable from registers r0, r1, r2, r3, a0, a1, sb, and fb. figure 12.8 stack state before and after acknowledgement of interrupt request the register saving operation, which is performed as part of the interrupt se quence, saved in 8 bits at a time in four steps. figure 12.9 shows the register saving operation. figure 12.9 register saving operation stack [sp] sp value before interrupt is generated previous stack contents lsb msb address previous stack contents m ? 4 m ? 3 m ? 2 m ? 1 m m+1 stack state before interrupt request is acknowledged [sp] new sp value previous stack contents lsb msb previous stack contents m m+1 stack state after interrupt request is acknowledged pcl pcm flgl flgh pch m ? 4 m ? 3 m ? 2 m ? 1 stack address pch : 4 high-order bits of pc pcm : 8 middle-order bits of pc pcl : 8 low-order bits of pc flgh : 4 high-order bits of flg flgl : 8 low-order bits of flg note: 1. when executing software number 32 to 63 int instructions, this sp is specified by the u flag. otherwise it is isp. stack completed saving registers in four operations. address [sp] ? 5 [sp] pcl pcm flgl flgh pch (3) (4) (1) (2) saved, 8 bits at a time sequence in which order registers are saved note: 1. [sp] indicates the initial value of the sp when an interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. when executing software number 32 to 63 int instructions, this sp is specified by the u flag. otherwise it is isp. [sp] ? 4 [sp] ? 3 [sp] ? 2 [sp] ? 1 pch : 4 high-order bits of pc pcm : 8 middle-order bits of pc pcl : 8 low-order bits of pc flgh : 4 high-order bits of flg flgl : 8 low-order bits of flg r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 122 of 453 rej09b0278-0210 12.1.6.8 returning from an interrupt routine when the reit instruction is executed at the end of an interrupt rout ine, the flg register and pc, which have been saved to the stack, are automatical ly restored. the program, that was running before the interrupt request was acknowledged, starts running again. restore registers saved by a program in an interrupt routine using the popm instruction or others before executing the reit instruction. 12.1.6.9 interrupt priority if two or more interrupt requests are generated while a single instruction is being executed, the interrupt with the higher priority is acknowledged. set bits ilvl2 to ilvl0 to select the desired priority level for maskable interrupts (peripheral functions). however, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, and the higher priority interrupts acknowledged. the priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set by hardware. figure 12.10 shows the priority levels of hardware interrupts. the interrupt priority does not affect software interrupts. the mcu jumps to the interrupt routine when the instruction is executed. figure 12.10 priority levels of hardware interrupts address break watchdog timer oscillation stop detection voltage monitor 1 (1) voltage monitor 2 peripheral function single step address match high low reset note: 1. for n, d version only. r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 123 of 453 rej09b0278-0210 12.1.6.10 interrupt prio rity judgement circuit the interrupt priority judgement circuit selects the hi ghest priority interrupt, as shown in figure 12.11. figure 12.11 interrupt priority level judgement circuit uart1 receive uart0 receive a/d conversion ssu / i 2 c bus (1) key input ipl lowest highest priority of peripheral function interrupts (if priority levels are same) interrupt request level judgment output signal interrupt request acknowledged i flag address match watchdog timer oscillation stop detection voltage monitor 1 (2) notes: 1. the iicsel bit in the pmr register switches functions. 2. for n, d version only. uart0 transmit uart1 transmit timer re int0 int1 int3 timer rb timer ra priority level of interrupt level 0 (default value) voltage monitor 2 timer rc r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 124 of 453 rej09b0278-0210 12.2 int interrupt 12.2.1 inti interrupt (i = 0, 1, 3) the inti interrupt is generated by an inti input. when using the inti interrupt, the intien bit in the inten register is set to 1 (enable). the edge polarity is sel ected using the intipl bit in the inten register and the pol bit in the intiic register. inputs can be passed through a digital filter with three different sampling clocks. table 12.6 lists the pin configuration of int interrupt. figure 12.12 shows the inten register. figure 12.13 shows the intf register. note: 1. the int1 pin is selected by the int1sel bit in the pm r register and the tiosel bit in the traioc register. refer to 7. programmable i/o ports for details. figure 12.12 inten register table 12.6 pin configuration of int interrupt pin name input/output function int0 (p4_5) input int0 interrupt input, timer rb external trigger input, timer rc pulse output forced cutoff input int1 (p1_5 , p1_7 , or p3_6) (1) input int1 interrupt input int3 (p3_3) input int3 interrupt input external input enable register symbol address after reset inten 00f9h 00h bit symbol bit name function rw int0 _ ____ input enable bit int0 _ ____ input polarity select bit (1,2) int1 _ ____ input enable bit int1 _ ____ input polarity select bit (1,2) int3 _ ____ input enable bit int3 _ ____ input polarity select bit (1,2) notes: 1. 2. 0 : disable 1 : enable rw ? (b5-b4) set to 0. rw reserved bits when setting the intipl bit (i = 0 to 3) to 1 (both edges), set the pol bit in the intiic register to 0 (selects fa lling edge). the ir bit in the intiic register may be set to 1 (requests interrupt) w hen the intipl bit is rew ritten. refer to 12.6.4 changing interrupt sources. 0 : disable 1 : enable 0 : one edge 1 : both edges 0 : one edge 1 : both edges rw int0pl rw int1en 0 : disable 1 : enable rw int0en rw int1pl 0 : one edge 1 : both edges rw int3en 00 int3pl b3 b2 b1 b0 b7 b6 b5 b4 r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 125 of 453 rej09b0278-0210 figure 12.13 intf register int0 _ _____ input filter select register symbol address after reset intf 00fah 00h bit symbol bit name function rw int0 _____ input filter select bits int1 _____ input filter select bits int3 _____ input filter select bits int0f0 rw int0f1 rw b7 b6 b5 b4 b3 b2 b1 b0 rw b1 b0 0 0 : no filter 0 1 : filter w ith f 1 sampling 1 0 : filter w ith f 8 sampling 1 1 : filter w ith f32 sampling rw b7 b6 0 0 : no filter 0 1 : filter w ith f 1 sampling 1 0 : filter w ith f 8 sampling 1 1 : filter w ith f32 sampling set to 0. int3f1 int3f0 00 ? (b5-b4) rw res er v ed bits int1f0 b3 b2 0 0 : no filter 0 1 : filter w ith f 1 sampling 1 0 : filter w ith f 8 sampling 1 1 : filter w ith f32 sampling rw int1f1 rw r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 126 of 453 rej09b0278-0210 12.2.2 inti input filter (i = 0, 1, 3) the inti input contains a digital filter. the sampling clock is selected by bits intif1 to intif0 in the intf register. the ir bit in the intiic register is set to 1 (interrupt re quested) when the inti level is sampled for every sampling clock and the sampled input level matches three times. figure 12.14 shows the configuration of inti input filter. figure 12.15 show s an operating example of inti input filter. figure 12.14 configuration of inti input filter figure 12.15 operating example of inti input filter intif0, intif1: bits in intf register intien, intipl: bits in inten register i = 0, 1, 3 = 01b inti port direction register (1) sampling clock digital filter (input level matches 3x) inti interrupt = 10b = 11b f32 f8 f1 intif1 to intif0 intien other than intif1 to intif0 = 00b = 00b intipl = 0 intipl = 1 note: 1. int0: port p4_5 direction register int1: port p1_5 direction register when using the p1_5 pin port p1_7 direction register when using the p1_7 pin int3: port p3_3 direction register both edges detection circuit inti input sampling timing ir bit in intiic register set to 0 in program this is an operation example when bits intif1 to intif0 in the intif register are set to 01b, 10b, or 11b (passing digital filter). i = 0, 1, 3 r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 127 of 453 rej09b0278-0210 12.3 key input interrupt a key input interrupt request is generated by one of the input edges of the k10 to k13 pins. the key input interrupt can be used as a key-on wake-up function to exit wait or stop mode. the kiien (i = 0 to 3) bit in the kien register can select whether the pins are used as kii input. the kiipl bit in the kien register can select the input polarity. when inputting ?l? to the kii pin which sets the kiipl bit to 0 (falling edge), the input of the other pins k10 to k13 is not detected as interrupts. also, when inputting ?h? to the kii pin, which sets the kiipl bit to 1 (rising edge), the input of the other pins k10 to k13 is not detected as interrupts. figure 12.16 shows a block diagram of key input interrupt. figure 12.16 block diagram of key input interrupt ki3 pull-up transistor ki2 pull-up transistor ki3pl = 0 ki3pl = 1 pd1_3 bit ki3en bit pu02 bit in pur0 register pd1_3 bit in pd1 register kupic register interrupt control circuit key input interrupt request ki2pl = 0 ki2pl = 1 pd1_2 bit ki2en bit ki1 pull-up transistor ki1pl = 0 ki1pl = 1 pd1_1 bit ki1en bit ki0 pull-up transistor ki0pl = 0 ki0pl = 1 pd1_0 bit ki0en bit ki0en, ki1en, ki2en, ki3en, ki0pl, ki1pl, ki2pl, ki3pl: bits in kien register pd1_0, pd1_1, pd1_2, pd1_3: bits in pd1 register r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 128 of 453 rej09b0278-0210 figure 12.17 kien register key input enable register (1) symbol address after reset kien 00fbh 00h bit symbol bit name function rw note: 1. rw ki0 input polarity select bit 0 : falling edge 1 : rising edge ki1 input enable bit 0 : disable 1 : enable b3 b2 rw ki2en rw ki1pl ki1 input polarity select bit 0 : falling edge 1 : rising edge ki2 input enable bit 0 : disable 1 : enable b7 b6 b5 b4 b1 b0 the ir bit in the kupic register may be set to 1 (requests interrupt) w hen the kien register is rew ritten. ref er to 12.6.4 changing interrupt sources. ki1en rw ki3en ki3 input enable bit ki3pl rw ki2pl ki2 input polarity select bit 0 : falling edge 1 : rising edge ki3 input polarity select bit 0 : falling edge 1 : rising edge ki0en rw ki0pl rw ki0 input enable bit 0 : disable 1 : enable rw 0 : disable 1 : enable r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 129 of 453 rej09b0278-0210 12.4 address match interrupt an address match interrupt request is generated immediat ely before execution of the instruction at the address indicated by the rmadi register (i = 0 or 1). this inte rrupt is used as a break fu nction by the debugger. when using the on-chip debugger, do not set an address match interrupt (registers of ai er, rmad0, and rmad1 and fixed vector tables) in a user system. set the starting address of any instruction in the rmadi register. bits aier0 and aier 1 in the aier0 register can be used to select enable or disable of the interrupt. the i flag and ipl do not affect the address match interrupt. the value of the pc (refer to 12.1.6.7 saving a register for the value of the pc) which is saved to the stack when an address match interrupt is acknowledged varies depending on the inst ruction at the addre ss indicated by the rmadi register. (the appropriate return address is not saved on the stack.) when returning from the address match interrupt, return by one of the following means: ? change the content of the stack and use the reit instruction. ? use an instruction such as pop to restore the stack as it was before the interrupt request was acknowledged. then use a jump instruction. table 12.7 lists the values of pc saved to stack when address match interrupt is acknowledged. figure 12.18 shows registers aier and rmad0 to rmad1. notes: 1. refer to the 12.1.6.7 saving a register for the pc value saved. 2. operation code: refer to the r8c/tiny series software manual (rej09b0001) . chapter 4. instruction code/number of cycles contains diagrams showing operation code below each syntax. operation code is shown in the bold frame in the diagrams. table 12.7 values of pc saved to stack wh en address match interrupt is acknowledged address indicated by rmadi register (i = 0 or 1) pc value saved (1) ? instruction with 2-byte operation code (2) ? instruction with 1-byte operation code (2) add.b:s #imm8,dest sub.b:s #i mm8,dest and.b:s #imm8,dest or.b:s #imm8,dest mov.b: s #imm8,dest stz #imm8,dest stnz #imm8,dest s tzx #imm81,#imm82,dest cmp.b:s #imm8,dest pushm src popm dest jmps #imm8 jsrs #imm8 mov.b:s #imm,dest (however, dest = a0 or a1) address indicated by rmadi register + 2 instructions other than the above address indicated by rmadi register + 1 table 12.8 correspondence between address match interr upt sources and asso ciated registers address match interrupt source address match inte rrupt enable bit address match interrupt register address match interrupt 0 aier0 rmad0 address match interrupt 1 aier1 rmad1 r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 130 of 453 rej09b0278-0210 figure 12.18 registers ai er and rmad0 to rmad1 a ddress match interrupt enable registe r symbol address after reset aier 0013h 00h bit symbol bit name function rw aier1 address match interrupt 1 enable bit aier0 0 : disable 1 : enable rw b2 b1 b0 address match interrupt 0 enable bit ? (b7-b2) ? nothing is assigned. if necessary, set to 0. when read, the content is 0. b7 b6 b5 b4 0 : disable 1 : enable rw b3 address match interrupt register i (i = 0 or 1) b0 symbol address after reset rma d0 0012h-0010h 000000h rma d1 0016h-0014h 000000h setting range rw function rw ( b19) b3 ( b15) b7 ( b8) b0 b7 ( b16) b0 ? ? (b7-b4) nothing is assigned. if necessary, set to 0. when read, the content is 0. address setting register for address match interrupt 00000h to fffffh ( b23) b7 r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 131 of 453 rej09b0278-0210 12.5 timer rc interrupt, clock synchr onous serial i/o with chip select interrupts, and i 2 c bus interface interrupt (interrupts with multiple interrupt request sources) the timer rc interrupt, clock synchronous serial i/o with chip select interrupt, and i 2 c bus interface interrupt each have multiple interrupt request sources. an interrupt requ est is generated by the logical or of several interrupt request factors and is reflected in the ir bit in the corresponding interrupt co ntrol register. therefore, each of these peripheral functions has its own interrupt request source stat us register (status register) and interrupt request source enable register (enable register) to c ontrol the generation of interrupt requests (change the ir bit in the interrupt control register). table 12.9 lists the registers associated with timer rc in terrupt, clock synchronous serial i/o with chip select interrupt, and i 2 c bus interface interrupt and figure 12.1 9 shows a block diagram of timer rc interrupt. figure 12.19 block diagram of timer rc interrupt table 12.9 registers associated with timer rc interrupt, clock synchronous serial i/o with chip select interrupt, and i 2 c bus interface interrupt status register of interrupt request source enable register of interrupt request source interrupt control register timer rc trcsr trcier trcic clock synchronous serial i/o with chip select sssr sser ssuic i 2 c bus interface icsr icier iicic timer rc interrupt request (ir bit in trcic register) imfa bit imiea bit imfb bit imieb bit imfc bit imiec bit imfd bit imied bit imfa, imfb, imfc, imfd, ovf: bits in trcsr register imiea, imieb, imiec, imied, ovie: bits in trcier register ovf bit ovie bit r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 132 of 453 rej09b0278-0210 as with other maskable interrupts, the timer rc interrupt, clock synchronous serial i/o with chip select interrupt, and i 2 c bus interface interrupt are controlled by the combination of the i flag, ir bit, bits ilvl0 to ilvl2, and ipl. however, since each interrupt source is generated by a co mbination of multip le interrupt request sources, the following differences from other maskable interrupts apply: ? when bits in the enable register corresponding to bits set to 1 in the status register are set to 1 (enable interrupt), the ir bit in the interrupt control register is set to 1 (interrupt requested). ? when either bits in the status register or bits in the enable register corresponding to bits in the status register, or both, are set to 0, the ir bit is set to 0 (interrupt not requested). basically, even though the interrupt is not acknowledged after the ir bit is set to 1, the interrupt requ est will not be maintained. also, the ir bit is not set to 0 even if 0 is written to the ir bit. ? individual bits in the status register are not automa tically set to 0 even if the interrupt is acknowledged. therefore, the ir bit is also not automatically set to 0 when the interrupt is acknowledged. set each bit in the status register to 0 in the interrupt routine. refer to the status register figure for how to set individual bits in the status register to 0. ? when multiple bits in the enable register are set to 1 and other request sources are generated after the ir bit is set to 1, the ir bit remains 1. ? when multiple bits in the enable register are set to 1, determine by the status register which request source causes an interrupt. refer to chapters of the individual peripheral functions ( 14.3 timer rc , 16.2 clock synchronous serial i/o with chip select (ssu) and 16.3 i 2 c bus interface ) for the status register and enable register. refer to 12.1.6 interrupt control for the interrupt control register. r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 133 of 453 rej09b0278-0210 12.6 notes on interrupts 12.6.1 reading address 00000h do not read address 00000h by a program. when a mask able interrupt request is acknowledged, the cpu reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. at this time, the acknowledged interrupt ir bit is set to 0. if address 00000h is read by a program, the ir bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. this may cause the interrupt to be cancel ed, or an unexpected interrupt to be generated. 12.6.2 sp setting set any value in the sp before an interrupt is acknowledged. the sp is set to 0000h afte r reset. therefore, if an interrupt is acknowledged before setting a value in the sp, the program may run out of control. 12.6.3 external interrupt and key input interrupt either ?l? level or an ?h? le vel of width shown in the el ectrical characteristics is ne cessary for the signal input to pins int0 , int1 , int3 and pins ki0 to ki3 , regardless of the cpu clock. for details, refer to table 20.21 (vcc = 5v), table 20.27 (vcc = 3v), table 20.3 3 (vcc = 2.2v), table 20.52 (vcc = 5v), ta bl e 2 0.5 8 (vcc = 3v) external interrupt inti (i = 0, 1, 3) input . r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 134 of 453 rej09b0278-0210 12.6.4 changing interrupt sources the ir bit in the interrupt control register may be se t to 1 (interrupt requested) when the interrupt source changes. when using an interrupt, set the ir bit to 0 (n o interrupt requested) after changing the interrupt source. in addition, changes of interrupt so urces include all factors that change the interr upt sources assigned to individual software interrupt numbers, polarities, and timing. therefore, if a mode change of a peripheral function involves interrupt sources, edge polarities, and ti ming, set the ir bit to 0 (no interrupt requested) after the change. refer to the individual periph eral function for its related interrupts. figure 12.20 shows an example of pro cedure for changing interrupt sources. figure 12.20 example of procedure for changing interrupt sources notes: 1. execute the above settings i ndividually. do not execute two or more settings at once (by one instruction). 2. to prevent interrupt request s from being generated, disable the peripheral function before changing the interrupt source. in this case, use the i flag if all maskable interrupts can be disabled. if all maskable interrupts cannot be disabled, use bits ilvl0 to ilvl2 of the interrupt whose source is changed. 3. refer to 12.6.5 changing interrupt control register contents for the instructions to be used and usage notes. interrupt source change disable interrupts (2, 3) set the ir bit to 0 (interrupt not requested) using the mov instruction (3) change interrupt source (including mode of peripheral function) enable interrupts (2, 3) change completed ir bit: the interrupt control register bit of an interrupt whose source is changed. r8c/26 group, r8c/27 group 12. interrupts rev.2.10 sep 26, 2008 page 135 of 453 rej09b0278-0210 12.6.5 changing interrupt c ontrol regist er contents (a) the contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. if in terrupt requests may be generated, disable interrupts before changing the interrupt control register contents. (b) when changing the contents of an interrupt contro l register after disabling interrupts, be careful to choose appropriate instructions. changing any bit other than ir bit if an interrupt request corresponding to a register is generated while executing the instruction, the ir bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. if this causes a problem, use the following instructions to change the register : and, or, bclr, bset changing ir bit if the ir bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used. therefore, use the mov instruct ion to set the ir bit to 0. (c) when disabling interrupts using the i flag, set the i flag as shown in the sample programs below. refer to (b) regarding changing the contents of interrupt control registers by the sample programs. sample programs 1 to 3 are for preventi ng the i flag from being set to 1 (interrupts enabled) before the interrupt control register is changed for reasons of the internal bus or the instruction queue buffer. example 1: use nop instructions to prevent i flag from being set to 1 before interrupt control register is changed int_switch1: fclr i ; disable interrupts and.b #00h,0056h ; set traic register to 00h nop ; nop fset i ; enable interrupts example 2: use dummy read to delay fset instruction int_switch2: fclr i ; disable interrupts and.b #00h,0056h ; set traic register to 00h mov.w mem,r0 ; dummy read fset i ; enable interrupts example 3: use popc instruction to change i flag int_switch3: pushc flg fclr i ; disable interrupts and.b #00h,0056h ; set traic register to 00h popc flg ; enable interrupts r8c/26 group, r8c/27 group 13. watchdog timer rev.2.10 sep 26, 2008 page 136 of 453 rej09b0278-0210 13. watchdog timer the watchdog timer is a function that detects when a pr ogram is out of control. use of the watchdog timer is recommended to improve the reliability of the system. the watchdog timer contains a 15-bit counter and allows selection of count source protection mode enable or disable. table 13.1 lists information on the count source protection mode. refer to 5.7 watchdog timer reset for details on the watchdog timer. figure 13.1 shows the block diagram of watchdog timer. figure 13.2 shows registers ofs and wdc. figure 13.3 shows registers wdtr, wdts, and cspr. figure 13.1 block diagram of watchdog timer table 13.1 count source protection mode item count source protection mode disabled count source protection mode enabled count source cpu clock low-speed on-chip oscillator clock count operation decrement count start condition either of the following can be selected ? after reset, count starts automatically ? count starts by writing to wdts register count stop condition stop mode, wait mode none reset condition of watchdog timer ? reset ? write 00h to the wdtr register before writing ffh ? underflow operation at the time of underflow watchdog timer interrupt or watchdog timer reset watchdog timer reset cpu clock 1/16 1/128 watchdog timer internal reset signal write to wdtr register wdc7 = 0 wdc7 = 1 set to 7fffh (1) pm12 = 1 watchdog timer reset pm12 = 0 watchdog timer interrupt request prescaler cspro = 0 foco-s cspro = 1 cspro: bit in cspr register wdc7: bit in wdc register pm12: bit in pm1 register note: 1. when the cspro bit is set to 1 (count source protection mode enabled), 0fffh is set. r8c/26 group, r8c/27 group 13. watchdog timer rev.2.10 sep 26, 2008 page 137 of 453 rej09b0278-0210 figure 13.2 registers ofs and wdc option function select register (1) symbol address when shipping ofs 0ffffh ffh (3) bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. csproini count source protect mode after reset select bit 0 : count source protect mode enabled after reset 1 : count source protect mode disabled after reset rw lvd1on voltage detection 1 circuit start bit (5, 6) 0 : voltage monitor 1 reset enabled after hardw are reset 1 : voltage monitor 1 reset disabled after hardw are reset rw romcp1 rom code protect bit 0 : rom code protect enabled 1 : rom code protect disabled rw romcr rom code protect disabled bit 0 : rom code protect disabled 1 : romcp1 enabled rw ? (b1) rw reserved bit set to 1. wdton rw watchdog timer start select bit 0 : starts w atchdog timer automatically after reset 1 : watchdog timer is inactive after reset 1 1 b7 b6 b5 b4 b3 b2 b1 b0 ? (b4) reserved bit set to 1. rw lvd0on voltage detection 0 circuit start bit (2, 4) 0 : voltage monitor 0 reset enabled after hardw are reset 1 : voltage monitor 0 reset disabled after hardw are reset rw for n, d version only. for j, k version, set the lvd0on bit to 1 (voltage monitor 0 reset disabled after hardw are reset). the lvd1on bit setting is valid only by a hardw are reset. when the pow er-on reset function is used, set the lvd1on bit to 0 (voltage monitor 1 reset enabled after hardw are reset). for j, k version only. for n, d version, set the lvd1on bit to 1 (voltage monitor 1 reset disabled after hardw are reset). the ofs register is on the flash memory. write to the ofs register w ith a program. after w riting is completed, do not w rite additions to the ofs register. if the block including the ofs register is erased, ffh is set to the ofs register. the lvd0on bit setting is valid only by a hardw are reset. to use the pow er-on reset, set the lvd0on bit to 0 (voltage monitor 0 reset enabled after hardw are reset). watchdog timer control register symbol address after reset wdc 000fh 00x11111b bit symbol bit name function rw b3 b2 b1 b0 rw high-order bits of w atchdog timer ? (b4-b0) rw ? (b5) rw 00 b7 b6 b5 b4 reserved bit set to 0. when read, the content is undefined. ro wdc7 ? (b6) reserved bit set to 0. prescaler select bit 0 : divide-by-16 1 : divide-by-128 r8c/26 group, r8c/27 group 13. watchdog timer rev.2.10 sep 26, 2008 page 138 of 453 rej09b0278-0210 figure 13.3 registers wdtr, wdts, and cspr watchdog timer reset register symbol address after reset wdtr 000dh undefined rw notes: 1. 2. when 00h is w ritten before w riting ffh, the w atchdog timer is reset. (1) the default value of the w atchdog timer is 7fffh w hen count source protection mode is disabled and 0fffh w hen count source protection mode is enabled. (2) function do not generate an interrupt betw een w hen 00h and ffh are w ritten. when the cspro bit in the cspr register is set to 1 (count source protection mode enabled), 0fffh is s et in the w atc hdog timer. wo b7 b0 watchdog timer start register symbol address after reset wdts 000eh undefined rw b0 b7 wo function the w atchdog timer starts counting after a w rite instruction to this register. count source protection mode register symbol address after reset (1) cspr 001ch 00h bit symbol bit name function rw notes: 1. 2. cspro count source protection mode select bit (2) 0 : count source protection mode disabled 1 : count source protection mode enabled ? (b6-b0) 000 b7 b6 b5 b4 b3 b2 b1 b0 rw 0 0 write 0 before w riting 1 to set the cspro bit to 1. 0 cannot be set by a program. when 0 is w ritten to the csproini bit in the ofs register, the value after reset is 10000000b. 0 reserved bits set to 0. rw 0 r8c/26 group, r8c/27 group 13. watchdog timer rev.2.10 sep 26, 2008 page 139 of 453 rej09b0278-0210 13.1 count source protect ion mode disabled the count source of the watchdog timer is the cpu cl ock when count source protection mode is disabled. table 13.2 lists the specifications of watchdog timer (with count source protection mode disabled). notes: 1. the watchdog timer is reset when 00h is written to the wdtr register before ffh. the prescaler is reset after the mcu is reset. some errors in the period of the watchdog timer may be caused by the prescaler. 2. the wdton bit cannot be changed by a program. to set the wdton bit, write 0 to bit 0 of address 0ffffh with a flash programmer. table 13.2 specifications of watchdog timer (with count source protection mode disabled) item specification count source cpu clock count operation decrement period division ratio of prescaler (n) c ount value of watchdog timer (32768) (1) cpu clock n: 16 or 128 (selected by wdc7 bit in wdc register) example: when the cpu clock frequency is 16 mhz and prescaler divides by 16, the period is approximately 32.8 ms count start condition the wdton bit (2) in the ofs register (0ffffh) selects the operation of the watchdog timer after a reset ? when the wdton bit is set to 1 (watchdog timer is in stop state after reset) the watchdog timer and prescaler stop after a reset and the count starts when the wdts register is written to ? when the wdton bit is set to 0 (w atchdog timer starts automatically after exiting) the watchdog timer and prescaler start counting automatically after a reset reset condition of watchdog timer ? reset ? write 00h to the wdtr register before writing ffh ? underflow count stop condition stop and wait modes (inherit the count from the held value after exiting modes) operation at time of underflow ? when the pm12 bit in the pm1 register is set to 0 watchdog timer interrupt ? when the pm12 bit in the pm1 register is set to 1 watchdog timer reset (refer to 5.7 watchdog timer reset ) r8c/26 group, r8c/27 group 13. watchdog timer rev.2.10 sep 26, 2008 page 140 of 453 rej09b0278-0210 13.2 count source protect ion mode enabled the count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. if the cpu clock stops when a program is out of control, the clock can still be supplied to the watchdog timer. table 13.3 lists the specifications of watchdog ti mer (with count source protection mode enabled). notes: 1. the wdton bit cannot be changed by a program. to set the wdton bit, write 0 to bit 0 of address 0ffffh with a flash programmer. 2. even if 0 is written to the csproini bit in the ofs register, the cspro bit is set to 1. the csproini bit cannot be changed by a program. to set the csproini bit, write 0 to bit 7 of address 0ffffh with a flash programmer. table 13.3 specifications of watchdog timer (with count source protection mode enabled) item specification count source low-speed on-chip oscillator clock count operation decrement period count value of watchdog timer (4096) low-speed on-chip oscillator clock example: period is approximately 32.8 ms when the low-speed on-chip oscillator clock frequency is 125 khz count start condition the wdton bit (1) in the ofs register (0ffffh) selects the operation of the watchdog timer after a reset. ? when the wdton bit is set to 1 (watchdog timer is in stop state after reset) the watchdog timer and prescaler stop after a reset and the count starts when the wdts register is written to ? when the wdton bit is set to 0 (w atchdog timer starts automatically after reset) the watchdog timer and prescaler start counting automatically after a reset reset condition of watchdog timer ? reset ? write 00h to the wdtr register before writing ffh ? underflow count stop condition none (the count does not stop in wait mode after the count starts. the mcu does not enter stop mode.) operation at time of underflow watchdog timer reset (refer to 5.7 watchdog timer reset ) registers, bits ? when setting the csppro bit in the cspr register to 1 (count source protection mode is enabled) (2) , the following are set automatically - set 0fffh to the watchdog timer - set the cm14 bit in the cm1 register to 0 (low-speed on-chip oscillator on) - set the pm12 bit in the pm1 register to 1 (the watchdog timer is reset when watchdog timer underflows) ? the following conditions apply in count source protection mode - writing to the cm10 bit in the cm1 register is disabled (it remains unchanged even if it is set to 1. the mcu does not enter stop mode.) - writing to the cm14 bit in the cm1 register is disabled (it remains unchanged even if it is set to 1. the low-sp eed on-chip oscillator does not stop.) r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 141 of 453 rej09b0278-0210 14. timers the microcomputer contains two 8-bit timers with 8-bit pres caler, a 16-bit timer, and a timer with a 4-bit counter, and an 8-bit counter. the two 8-bit timers with the 8-bit prescal er contain timer ra and time r rb. these timers contain a reload register to memorize the defaul t value of the counter. the 16-bit timer is timer rc which contains the input capture and output compare. the 4 and 8- bit counters are timer re which contains the output compare. all these timers operate independently. table 14.1 lists functional comparison of timers. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 142 of 453 rej09b0278-0210 notes: 1. for j, k version, fc4 and fc32 cannot be selected. 2. for n, d version only. table 14.1 functional comparison of timers item timer ra timer rb timer rc timer re configuration 8-bit timer with 8- bit prescaler (with reload register) 8-bit timer with 8- bit prescaler (with reload register) 16-bit free-run timer (with input capture and output compare) 4-bit counter 8-bit counter count decrement decrement increment increment count source (1) ?f1 ?f2 ?f8 ?foco ?fc32 ?f1 ?f2 ?f8 ?timer ra underflow ?f1 ?f2 ?f4 ?f8 ?f32 ? foco40m ? trcclk ?f4 ?f8 ?f32 ?fc4 function timer mode provided provided provided (input capture function, output compare function) not provided pulse output mode provided not pr ovided not provided not provided event counter mode provided not provided not provided not provided pulse width measurement mode provided not provided not provided not provided pulse period measurement mode provided not provided not provided not provided programmable waveform generation mode not provided provided not provided not provided programmable one-shot generation mode not provided provided not provided not provided programmable wait one-shot generation mode not provided provided not provided not provided input capture mode not provided no t provided provided not provided output compare mode not provided not provided provided provided pwm mode not provided not provided provided not provided pwm2 mode not provided not pr ovided provided not provided real-time clock mode not provided not provided not provided provided (2) input pin traio int0 int0 , trcclk, trctrg trcioa, trciob, trcioc, trciod ? output pin trao traio trbo trcioa, trciob, trcioc, trciod treo related interrupt timer ra interrupt int1 interrupt timer rb interrupt int0 interrupt compare match / input capture a to d interrupt overflow interrupt int0 interrupt timer re interrupt timer stop provided provided provided provided r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 143 of 453 rej09b0278-0210 14.1 timer ra timer ra is an 8-bit timer with an 8-bit prescaler. the prescaler and timer each consist of a reload register and counter. the reload regist er and counter are allocated at the same address, and can be accessed when accessing registers trapre and tra (refer to tables 14.2 to 14.6 the specification s of each mode ). the count source for timer ra is the operating clock that regulates the timing of timer operations such as counting and reloading. figure 14.1 shows a block diagram of timer ra. figures 14.2 and 14.3 show the registers associated with timer ra. timer ra contains the following five operating modes: ? timer mode: the timer counts the internal count source. ? pulse output mode: the timer counts the internal count source and outputs pulses which invert the polarity by underflow of the timer. ? event counter mode: the timer counts external pulses. ? pulse width measurement mode: the timer meas ures the pulse width of an external pulse. ? pulse period measurement mode: the timer meas ures the pulse period of an external pulse. figure 14.1 block diagram of timer ra = 000b = 001b = 011b f2 f8 f1 = 010b foco tck2 to tck0 bit tmod2 to tmod0 = other than 010b counter reload register trapre register (prescaler) data bus timer ra interrupt write to tramr register write 1 to tstop bit tcstf, tstop: tracr register tedgsel, topcr, toena, tiosel, tipf1, tipf0: traioc register tmod2 to tmod0, tck2 to tck0, tckcut: tramr register toggle flip-flop q q clr ck toena bit trao pin int1/traio (p1_5) pin tcstf bit tckcut bit tmod2 to tmod0 = 011b or 100b tmod2 to tmod0 = 010b polarity switching digital filter counter reload register tra register (timer) tipf1 to tipf0 bits = 01b = 10b f8 f1 = 11b f32 tiosel = 0 tiosel = 1 count control circle tmod2 to tmod0 = 001b topcr bit underflow signal measurement completion signal tipf1 to tipf0 bits = other than 000b = 00b int1/traio (p1_7) pin tedgsel = 1 tedgsel = 0 = 100b fc32 (1) note: 1. for j, k version, fc32 cannot be selected. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 144 of 453 rej09b0278-0210 figure 14.2 registers tracr and traioc timer ra control re g iste r (4) symbol address after reset tra cr 0100h 00h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. rw tcstf rw rw ro tsta rt 0 : count stops 1 : during count 0 : count stops 1 : count starts timer ra count status flag (1) tstop active edge judgment flag (3, 5) timer ra underflow flag (3, 5) 0 : no underflow 1 : underflow nothing is assigned. if necessary, set to 0. when read, the content is 0. b3 b2 when this bit is set to 1, the count is forcibly stopped. when read, its content is 0. ? (b3) b1 b0 b7 b6 b5 b4 timer ra count start bit (1) timer ra count forcible stop bit (2) bits tedgf and tundf can be set to 0 by w riting 0 to these bits by a program. how ever, their value remains unchanged w hen 1 is w ritten. in pulse w idth measurement mode and pulse period measurement mode, use the mov instruction to set the tracr register. if it is necessary to avoid changing the values of bits tedgf and tundf, w rite 1 to them. ? (b7-b6) ? ? rw tedgf 0 : active edge not received 1 : active edge received (end of measurement period) set to 0 in timer mode, pulse output mode, and event counter mode. tundf when the tstop bit is set to 1, bits tstart and tcstf and registers trapre and tra are set to the values after a reset. nothing is assigned. if necessary, set to 0. when read, the content is 0. ref er to 14.1.6 notes on tim er ra for precautions regarding bits tstart and tcstf. timer ra i/o control registe r symbol address after reset tra ioc 0101h 00h bit symbol bit name function rw int1 _ ____ /traio select bit b3 b2 tiosel b1 b0 b7 b6 b5 b4 ? tedgsel rw topcr rw traio polarity sw itch bit nothing is assigned. if necessary, set to 0. when read, the content is 0. ? (b7-b6) rw tipf0 rw toena rw traio input filter select bits tipf1 function varies depending on operating mode. traio output control bit trao output enable bit r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 145 of 453 rej09b0278-0210 figure 14.3 registers tramr, trapre, and tra timer ra mode registe r symbol address after reset tra mr 0102h 00h bit symbol bit name function rw notes: 1. 2. for j, k version, fc32 cannot be selected. rw ? tck0 rw when both the tstart and tcstf bits in the tracr register are set to 0 (count stops), rew rite this register. rw timer ra count source cutoff bit 0 : provides count source 1 : cuts off count source tck2 rw tmod1 rw tmod0 timer ra operating mode select bits (1) b2 b1 b0 0 0 0 : timer mode 0 0 1 : pulse output mode 0 1 0 : event counter mode 0 1 1 : pulse w idth measurement mode 1 0 0 : pulse period measurement mode 1 0 1 : 1 1 0 : do not set. 1 1 1 : tmod2 b7 b6 b5 b4 rw timer ra count source select bits b6 b5 b4 0 0 0 : f1 0 0 1 : f8 0 1 0 : foco 0 1 1 : f2 1 0 0 : fc32 (2) 1 0 1 : 1 1 0 : do not set. 1 1 1 : nothing is assigned. if necessary, set to 0. when read, the content is 0. rw tckcut tck1 b3 b2 ? (b3) b1 b0 timer ra prescaler registe r symbol address after reset tra pre 0103h ffh (1) mode function setting range rw note: 1. 00h to ffh rw pu ls e w id t h measurement mode b0 timer mode b7 pulse output mode rw 00h to ffh counts an internal count source rw 00h to ffh when the tstop bit in the tracr register is set to 1, the trapre register is set to ffh. event counter mode counts an external count source 00h to ffh rw measure pulse w idth of input pulses from external (counts internal count source) 00h to ffh rw pulse period measurement mode measure pulse period of input pulses from external (counts internal count source) timer ra register symbol address after reset tra 0104h ffh (1) mode function setting range rw note: 1. when the tstop bit in the tracr register is set to 1, the tra register is set to ffh. b0 all modes counts on underflow of timer ra prescaler register rw b7 00h to ffh r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 146 of 453 rej09b0278-0210 14.1.1 timer mode in this mode, the timer counts an internally generated count source (refer to table 14.2 specifications of timer mode ). figure 14.4 shows the traioc register in timer mode. note: 1. for j, k version, fc32 cannot be selected. figure 14.4 traioc register in timer mode table 14.2 specifications of timer mode item specification count sources f1, f2, f8, foco, fc32 (1) count operations ? decrement ? when the timer underflows, the contents of the reload register are reloaded and the count is continued. divide ratio 1/(n+1)(m+1) n: value set in trapre register, m: value set in tra register count start condition 1 (count starts) is writte n to the tstart bit in the tracr register. count stop conditions ? 0 (count stops) is writ ten to the tstart bit in the tracr register. ? 1 (count forcibly stops) is written to the tstop bit in the tracr register. interrupt request generation timing when timer ra underflows [timer ra interrupt]. int1 /traio pin function programmable i/o port, or int1 interrupt input trao pin function programmable i/o port read from timer the count value can be read by reading registers tra and trapre. write to timer ? when registers trapre and tra are written while the count is stopped, values are written to both the reload register and counter. ? when registers trapre and tra are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 timer write control during count operation ). timer ra i/o control register symbol address after reset tra ioc 0101h 00h bit symbol bit name function rw int1 _ ____ /traio select bit 0 : int1 _ ____ /traio pin (p1_7) 1 : int1 _ ____ /traio pin (p1_5) nothing is assigned. if necessary, set to 0. when read, the content is 0. trao output enable bit traio input filter select bits set to 0 in timer mode. rw traio polarity sw itch bit 0 set to 0 in timer mode. traio output control bit ? (b7-b6) ? topcr rw toena rw rw tipf0 rw tipf1 00 b7 b6 b5 b4 b3 b2 tiosel b1 b0 0 0 tedgsel r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 147 of 453 rej09b0278-0210 14.1.1.1 timer write control during count operation timer ra has a prescaler and a time r (which counts the prescaler unde rflows). the prescaler and timer each consist of a reload register and a coun ter. when writing to the pr escaler or timer, values are written to both the reload register and counter. however, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. in addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. therefore, if the prescaler or timer is written to when count operation is in progress, the counter value is not updated immediately after the write instruction is executed. figure 14.5 shows an operating example of timer ra when counter value is rewritten during count operation. figure 14.5 operating example of timer ra when counter value is rewritten during count operation count source reloads register of timer ra prescaler ir bit in traic register 0 counter of timer ra prescaler reloads register of timer ra counter of timer ra set 01h to the trapre register and 25h to the tra register by a program. after writing, the reload register is written to at the first count source. reload at second count source reload at underflow after writing, the reload register is written to at the first underflow. reload at the second underflow the ir bit remains unchanged until underflow is generated by a new value. 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h 06h new value (01h) previous value new value (25h) previous value 03h 24h 02h 25h the above applies under the following conditions. both bits tstart and tcstf in the tra cr register are set to 1 (during count). r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 148 of 453 rej09b0278-0210 14.1.2 pulse output mode in pulse output mode, the internally generated count sour ce is counted, and a pulse with inverted polarity is output from the traio pin each time the timer underflows (refer to table 14.3 specifications of pulse output mode ). figure 14.6 shows the traioc register in pulse output mode. notes: 1. the level of the output pulse becomes the level when the pulse output starts when the tramr register is written to. 2. for j, k version, fc32 cannot be selected. table 14.3 specifications of pulse output mode item specification count sources f1, f2, f8, foco, fc32 (2) count operations ? decrement ? when the timer underflows, the contents in the reload register is reloaded and the count is continued. divide ratio 1/(n+1)(m+1) n: value set in trapre register, m: value set in tra register count start condition 1 (count starts) is writte n to the tstart bit in the tracr register. count stop conditions ? 0 (count stops) is writ ten to the tstart bit in the tracr register. ? 1 (count forcibly stops) is written to the tstop bit in the tracr register. interrupt request generation timing when timer ra underflows [timer ra interrupt]. int1 /traio pin function pulse output, programmable output port, or int1 interrupt (1) trao pin function programmable i/o port or inverted output of traio (1) read from timer the count value can be read by reading registers tra and trapre. write to timer ? when registers trapre and tra are written while the count is stopped, values are written to both the reload register and counter. ? when registers trapre and tra are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 timer write control during count operation ). select functions ? traio signal polarity switch function the tedgsel bit in the traioc register selects the level at the start of pulse output. (1) ? trao output function pulses inverted from the traio output polarity can be output from the trao pin (selectable by the toena bit in the traioc register). ? pulse output stop function output from the traio pin is stopped by the topcr bit in the traioc register. ?int1 /traio pin select function p1_7 or p1_5 is selected by the tiosel bit in the traioc register. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 149 of 453 rej09b0278-0210 figure 14.6 traioc register in pulse output mode timer ra i/o control registe r symbol address after reset tra ioc 0101h 00h bit symbol bit name function rw int1 _ ____ /traio select bit 0 : int1 _ ____ /traio pin (p1_7) 1 : int1 _ ____ /traio pin (p1_5) b3 b2 0 : po r t p3 _ 7 1 : trao output (inverted traio output from p3_7) tiosel b1 b0 0 : traio output starts at ?h? 1 : traio output starts at ?l? b7 b6 b5 b4 00 tipf1 ? (b7-b6) ? topcr rw toena rw rw tipf0 traio output control bit tedgsel rw traio polarity sw itch bit rw rw 0 : traio output 1 : port p1_7 or p1_5 nothing is assigned. if necessary, set to 0. when read, the content is 0. trao output enable bit traio input filter select bits set to 0 in pulse output mode. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 150 of 453 rej09b0278-0210 14.1.3 event counter mode in event counter mode, external signal inputs to the int1 /traio pin are counted (refer to table 14.4 specifications of event counter mode ). figure 14.7 shows the traioc register in event counter mode. note: 1. the level of the output pulse becomes the level when the pulse output starts when the tramr register is written to. table 14.4 specifications of event counter mode item specification count source external signal which is input to traio pin (active edge selectable by a program) count operations ? decrement ? when the timer underflows, the contents of the reload register are reloaded and the count is continued. divide ratio 1/(n+1)(m+1) n: setting value of trapre register , m: setting value of tra register count start condition 1 (count starts) is writte n to the tstart bit in the tracr register. count stop conditions ? 0 (count stops) is writ ten to the tstart bit in the tracr register. ? 1 (count forcibly stops) is written to the tstop bit in the tracr register. interrupt request generation timing ? when timer ra underflows [timer ra interrupt]. int1 /traio pin function count source input (int1 interrupt input) trao pin function programmable i/o port or pulse output (1) read from timer the count value can be read by reading registers tra and trapre. write to timer ? when registers trapre and tra are written while the count is stopped, values are written to both the reload register and counter. ? when registers trapre and tra are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 timer write control during count operation ). select functions ?int1 input polarity switch function the tedgsel bit in the traioc register selects the active edge of the count source. ? count source input pin select function p1_7 or p1_5 is selected by the tiosel bit in the traioc register. ? pulse output function pulses of inverted polarity can be out put from the trao pin each time the timer underflows (selectable by the toena bit in the traioc register). (1) ? digital filter function bits tipf0 and tipf1 in the traioc re gister enable or disable the digital filter and select the sampling frequency. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 151 of 453 rej09b0278-0210 figure 14.7 traioc register in event counter mode timer ra i/o control registe r symbol address after reset tra ioc 0101h 00h bit symbol bit name function rw int1 _ ____ /traio select bit 0 : int1 _ ____ /traio pin (p1_7) 1 : int1 _ ____ /traio pin (p1_5) note: 1. ? when the same value from the traio pin is sampled three times continuously, the input is determined. traio output control bit set to 0 in event counter mode. nothing is assigned. if necessary, set to 0. when read, the content is 0. trao output enable bit traio input filter select bits (1) b5 b4 0 0 : no filter 0 1 : filter w ith f1 sampling 1 0 : filter w ith f8 sampling 1 1 : filter w ith f32 sampling tipf1 ? (b7-b6) rw tedgsel rw traio polarity sw itch bit rw tipf0 rw topcr rw b3 b2 b7 b6 b5 b4 0 : po r t p3 _ 7 1 : trao output tiosel b1 b0 0 : starts counting at rising edge of the traio input or traio starts output at ?l? 1 : starts counting at fa lling edge of the traio input or traio starts output at ?h? 0 toena r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 152 of 453 rej09b0278-0210 14.1.4 pulse width measurement mode in pulse width measurement mode, the pulse width of an external signal input to the int1 /traio pin is measured (refer to table 14.5 specifications of pulse width measurement mode ). figure 14.8 shows the traioc register in pulse width measurement mode and figure 14.9 shows an operating example of puls e width measurement mode. note: 1. for j, k version, fc32 cannot be selected. table 14.5 specifications of pulse width measurement mode item specification count sources f1, f2, f8, foco, fc32 (1) count operations ? decrement ? continuously counts the selected signal only when measurement pulse is ?h? level, or conversely only ?l? level. ? when the timer underflows, the contents of the reload register are reloaded and the count is continued. count start condition 1 (count starts) is writte n to the tstart bit in the tracr register. count stop conditions ? 0 (count stops) is writ ten to the tstart bit in the tracr register. ? 1 (count forcibly stops) is written to the tstop bit in the tracr register. interrupt request generation timing ? when timer ra underflows [timer ra interrupt]. ? rising or falling of the tr aio input (end of measurement period) [timer ra interrupt] int1 /traio pin function measured pulse input (int1 interrupt input) trao pin function programmable i/o port read from timer the count value can be read by reading registers tra and trapre. write to timer ? when registers trapre and tra are written while the count is stopped, values are written to both the reload register and counter. ? when registers trapre and tra are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 timer write control during count operation ). select functions ? measurement level select the tedgsel bit in the traioc register selects the ?h? or ?l? level period. ? measured pulse input pin select function p1_7 or p1_5 is selected by the tiosel bit in the traioc register. ? digital filter function bits tipf0 and tipf1 in the traioc re gister enable or disable the digital filter and select the sampling frequency. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 153 of 453 rej09b0278-0210 figure 14.8 traioc register in pulse width measurement mode timer ra i/o control registe r symbol address after reset tra ioc 0101h 00h bit symbol bit name function rw int1 _ ____ /traio select bit 0 : int1 _ ____ /traio pin (p1_7) 1 : int1 _ ____ /traio pin (p1_5) note: 1. ? (b7-b6) nothing is assigned. if necessary, set to 0. when read, the content is 0. trao output enable bit traio input filter select bits (1) b5 b4 0 0 : no filter 0 1 : filter w ith f1 sampling 1 0 : filter w ith f8 sampling 1 1 : filter w ith f32 sampling set to 0 in pulse w idth measurement mode. tedgsel rw traio polarity sw itch bit ? topcr rw toena rw rw tipf0 rw traio output control bit tipf1 b7 b6 b5 b4 when the same value from the traio pin is sampled three times continuously, the input is determined. b3 b2 tiosel b1 b0 0 : traio input starts at ?l? 1 : traio input starts at ?h? 0 0 r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 154 of 453 rej09b0278-0210 figure 14.9 operating example of pulse width measurement mode ffffh n 0000h content of counter (hex) n = high level: the contents of tra register, low level: the contents of trapre register count start count stop underflow period tstart bit in tracr register 1 0 measured pulse (traio pin input) 1 0 tedgf bit in tracr register 1 0 tundf bit in tracr register 1 0 ? ?h? level width of measured pulse is measured. (tedgsel = 1) ? trapre = ffh set to 1 by program ir bit in traic register 1 0 set to 0 by program count stop count start set to 0 when interrupt request is acknowledged, or set by program count start set to 0 by program the above applies under the following conditions. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 155 of 453 rej09b0278-0210 14.1.5 pulse period measurement mode in pulse period measurement mode, the pulse period of an external signal input to the int1 /traio pin is measured (refer to table 14.6 specifications of pulse period measurement mode ). figure 14.10 shows the traioc register in pulse period measurement mode and figure 14.11 shows an operating example of puls e period measurement mode. notes: 1. input a pulse with a period longer than twice th e timer ra prescaler period. input a pulse with a longer ?h? and ?l? width than the timer ra prescaler period. if a pulse with a shorter period is input to the traio pin, the input may be ignored. 2. for j, k version, fc32 cannot be selected. table 14.6 specifications of pulse period measurement mode item specification count sources f1, f2, f8, foco, fc32 (2) count operations ? decrement ? after the active edge of the measured pu lse is input, the contents of the read- out buffer are retained at the first underflow of timer ra prescaler. then timer ra reloads the contents in the reload register at the second underflow of timer ra prescaler and continues counting. count start condition 1 (count start) is writt en to the tstart bit in the tracr register. count stop conditions ? 0 (count stop) is writ ten to tstart bit in the tracr register. ? 1 (count forcibly stops) is written to the tstop bit in the tracr register. interrupt request generation timing ? when timer ra underflows or reloads [timer ra interrupt]. ? rising or falling of the tr aio input (end of measurement period) [timer ra interrupt] int1 /traio pin function measured pulse input (1) (int1 interrupt input) trao pin function programmable i/o port read from timer the count value can be read by reading registers tra and trapre. write to timer ? when registers trapre and tra are written while the count is stopped, values are written to both the reload register and counter. ? when registers trapre and tra are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 timer write control during count operation ). select functions ? measurement period select the tedgsel bit in the traioc register selects the measurement period of the input pulse. ? measured pulse input pin select function p1_7 or p1_5 is selected by the tiosel bit in the traioc register. ? digital filter function bits tipf0 and tipf1 in the traioc re gister enable or disable the digital filter and select the sampling frequency. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 156 of 453 rej09b0278-0210 figure 14.10 traioc register in pulse period measurement mode timer ra i/o control registe r symbol address after reset tra ioc 0101h 00h bit symbol bit name function rw int1 _ ____ /traio select bit 0 : int1 _ ____ /traio pin (p1_7) 1 : int1 _ ____ /traio pin (p1_5) note: 1. when the same value from the traio pin is sampled three times continuously, the input is determined. b3 b2 tiosel b1 b0 0 : measures measurement pulse from one rising edge to next rising edge 1 : measures measurement pulse from one falling edge to next fa lling edge 0 0 b7 b6 b5 b4 ? topcr rw toena rw rw tipf0 rw traio output control bit tipf1 tedgsel rw traio polarity sw itch bit ? (b7-b6) nothing is assigned. if necessary, set to 0. when read, the content is 0. trao output enable bit tra io input f ilter select bits (1) b5 b4 0 0 : no filter 0 1 : filter w ith f 1 sampling 1 0 : filter w ith f 8 sampling 1 1 : filter w ith f32 sampling set to 0 in pulse period measurement mode. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 157 of 453 rej09b0278-0210 figure 14.11 operating example of pulse period measurement mode underflow signal of timer ra prescaler notes: 1. the contents of the read-out buffer can be read by r eading the tra register in pulse period measurement mode. 2. after an active edge of the measured pulse is input, the tedgf bit in the tracr register is set to 1 (active edge found) whe n the timer ra prescaler underflows for the second time. 3. the tra register should be read before the next active edge is input after the tedgf bit is set to 1 (active edge found). the contents in the read-out buffer are retained until the tra register is read. if the tra register is not read before the nex t active edge is input, the measured result of the previous period is retained. 4. to set to 0 by a program, use a mov instruction to write 0 to the tedgf bit in the tracr register. at the same time, write 1 to the tundf bit in the tracr register. 5. to set to 0 by a program, use a mov instruction to write 0 to the tundf bit. at the same time, write 1 to the tedgf bit. 6. bits tundf and tedgf are both set to 1 if timer ra underflows and reloads on an active edge simultaneously. 0eh 0dh 0fh 0eh 0dh 0ch 0bh 0ah 09h 0fh 0eh 0dh 01h 00h 0fh 0eh 0fh 0dh 0fh 0bh 0ah 0dh 01h 00h 0fh 0eh 09h tstart bit in tracr register 1 0 1 0 1 0 tedgf bit in tracr register 1 0 measurement pulse (traio pin input) contents of tra 1 0 contents of read-out buffer (1) ir bit in traic register tundf bit in tracr register set to 1 by program starts counting tra reloads tra read (3) retained set to 0 by program conditions: the period from one ri sing edge to the next rising edge of the me asured pulse is measured (tedgsel = 0) with the default value of the tra register as 0fh. 0eh tra reloads retained set to 0 when interrupt request is acknowledged, or set by program set to 0 by program underflow (note 2) (note 2) (note 4) (note 6) (note 5) r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 158 of 453 rej09b0278-0210 14.1.6 notes on timer ra ? timer ra stops counting after a rese t. set the values in the timer ra and timer ra prescalers before the count starts. ? even if the prescaler and timer ra are read out in 16- bit units, these registers are read 1 byte at a time by the mcu. consequently, the timer va lue may be updated during the period when these two registers are being read. ? in pulse period measurement mode, bits tedgf and tundf in the tracr register can be set to 0 by writing 0 to these bits by a program. however, these b its remain unchanged if 1 is written. when using the read-modify-write instruction for the tracr regi ster, the tedgf or tundf bit may be set to 0 although these bits are set to 1 while the instruction is being executed. in this case, write 1 to the tedgf or tundf bit which is not supposed to be set to 0 with the mov instruction. ? when changing to pulse period m easurement mode from another mode, the contents of bits tedgf and tundf are undefined. write 0 to bits tedgf and tundf before the count starts. ? the tedgf bit may be set to 1 by the first timer ra prescaler underflow generate d after the count starts. ? when using the pulse period measur ement mode, leave two or more periods of the timer ra prescaler immediately after the count starts, then set the tedgf bit to 0. ? the tcstf bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the tstart bit to 1 (count starts) while the count is stopped. during this time, do not access registers associated with timer ra (1) other than the tcstf bit. timer ra starts counting at the first valid edge of the count source after the tcstf bit is set to 1 (during count). the tcstf bit remains 1 for 0 to 1 cycle of the count source after setting the tstart bit to 0 (count stops) while the count is in progress. timer ra c ounting is stopped when the tcstf bit is set to 0. during this time, do not access re gisters associated with timer ra (1) other than the tcstf bit. note: 1. registers associated with timer ra : tracr, traioc, tramr, trapre, and tra. ? when the trapre register is continuously written during count operation (tcstf bit is set to 1), allow three or more cycles of the count source clock for each write interval. ? when the tra register is continuously written during count operation (tcstf bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 159 of 453 rej09b0278-0210 14.2 timer rb timer rb is an 8-bit timer with an 8-bit prescaler. the prescaler and timer each consist of a reload regist er and counter (refer to tables 14.7 to 14.10 the specifications of each mode ). timer rb has timer rb primary and time r rb secondary as reload registers. the count source for timer rb is the opera ting clock that regulates the timing of timer operations such as counting and reloading. figure 14.12 shows a block diagram of timer rb. figures 14.13 to 14.15 show the registers associated with timer rb. timer rb has four operation modes listed as follows: ? timer mode: the timer counts an internal count source (peripheral function clock or timer ra underflows). ? programmable waveform generation mode: the timer outputs pulses of a given width successively. ? programmable one-shot generation mode: the timer outputs a one-shot pulse. ? programmable wait one-shot generation mode: the timer outputs a delayed one-shot pulse. figure 14.12 block diagram of timer rb int0pl bit = 00b = 01b = 11b f8 f1 = 10b timer ra underflow tck1 to tck0 bits tstart bit trbpre register (prescaler) timer rb interrupt int0 interrupt tcstf bit toggle flip-flop q q clr ck topl = 1 topl = 0 p3_1 bit in p3 register f2 tmod1 to tmod0 bits = 10b or 11b tosstf bit polarity select inoseg bit input polarity selected to be one edge or both edges digital filter int0 pin int0en bit tmod1 to tmod0 bits = 01b , 10b, 11b counter reload register counter (timer rb) reload register trbpr register data bus trbsc register reload register tckcut bit inostg bit tstart, tcstf: bits in trbcr register tosstf: bit in trbocr register topl, tocnt, inostg, inoseg: bits in trbioc register tmod1 to tmod0, tck1 to tck0, tckcut: bits in trbmr register trbosel: bit in pinsr2 register (timer) tocnt = 0 tocnt = 1 tmod1 to tmod0 bits = 01b , 10b, 11b trbo (p1_3) pin trbosel = 0 trbosel = 1 trbo (p3_1) pin r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 160 of 453 rej09b0278-0210 figure 14.13 registers trbcr and trbocr timer rb control registe r symbol address after reset trbcr 0108h 00h bit symbol bit name function rw notes: 1. 2. 3. when the tstop bit is set to 1, registers trbpre, trbsc, trbpr, and bits tstart and tcstf, and the tosstf bit in the trbocr register are set to values after a reset. 0 : count stops 1 : during count (3) nothing is assigned. if necessary, set to 0. when read, the content is 0. ro ? (b7-b3) ? tcstf timer rb count status flag (1) tstop rw b3 b2 when this bit is set to 1, the count is forcibly stopped. when read, its content is 0. b1 b0 0 : count stops 1 : count starts b7 b6 b5 b4 indicates that count operation is in progress in timer mode or programmable w aveform mode. in programmable one- shot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has been acknow ledged. timer rb count start bit (1) timer rb count forcible stop bit (1, 2) ref er to 14.2.5 notes on tim er rb for precautions regarding bits tstart, tcstf and tstop. tsta rt rw timer rb one-shot control register (2) symbol address after reset trbocr 0109h 00h bit symbol bit name function rw notes: 1. 2. nothing is assigned. if necessary, set to 0. when read, the content is 0. timer rb one-shot status flag (1) when 1 is set to the tstop bit in the trbcr register, the tosstf bit is set to 0. this register is enabled w hen bits tmod1 to tmod0 in the trbmr register is set to 10b (programmable one-shot generation mode) or 11b (programmable w ait one-shot generation mode). ro ? (b7-b3) ? rw rw timer rb one-shot start bit when this bit is set to 1, one-shot trigger generated. when read, its content is 0. timer rb one-shot stop bit when this bit is set to 1, counting of one-shot pulses (including programmable w ait one-shot pulses) stops. when read, its content is 0. b7 b6 b5 b4 b3 b2 0 : one-shot stopped 1 : one-shot operating (including w ait period) b1 b0 tossp tosstf tosst r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 161 of 453 rej09b0278-0210 figure 14.14 registers trbioc and trbmr timer rb i/o control registe r symbol address after reset trbioc 010ah 00h bit symbol bit name function rw topl timer rb output level select bit timer rb output sw itch bit b7 b6 b5 b4 b3 b2 inoseg b1 b0 inostg tocnt nothing is assigned. if necessary, set to 0. when read, the content is 0. one-shot trigger polarity select bit ? (b7-b4) ? function varies depending on operating mode. rw rw rw rw one-shot trigger control bit timer rb mode registe r symbol address after reset trbmr 010bh 00h bit symbol bit name function rw notes: 1. 2. b3 b2 twrc b1 b0 ? (b2) tmod0 rw tmod1 rw timer rb operating mode select bits (1) b1 b0 0 0 : timer mode 0 1 : programmable w aveform generation mode 1 0 : programmable one-shot generation mode 1 1 : programmable w ait one-shot generation mode b7 b6 b5 b4 rw nothing is assigned. if necessary, set to 0. when read, the content is 0. timer rb w rite control bit (2) 0 : write to reload register and counter 1 : write to reload register only ? the twrc bit can be set to either 0 or 1 in timer mode. in programmable w aveform generation mode, programmable one-shot generation mode, or programmable w ait one-shot generation mode, the twrc bit must be set to 1 (w rite to reload register only). tck0 rw change bits tmod1 and tmod0; tck1 and tck0; and tckcut w hen both the tstart and tcstf bits in the trbcr register set to 0 (count stops). rw timer rb count source cutoff bit (1) 0 : provides count source 1 : cuts off count source rw tckcut ? (b6) ? timer rb count source select bits (1) b5 b4 0 0 : f1 0 1 : f8 1 0 : timer ra underflow 1 1 : f2 tck1 nothing is assigned. if necessary, set to 0. when read, the content is 0. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 162 of 453 rej09b0278-0210 figure 14.15 registers t rbpre, trbsc, and trbpr timer rb prescaler register (1) symbol address after reset trbpre 010ch ffh mode function setting range rw note: 1. timer mode b0 b7 rw 00h to ffh counts an internal count source or timer ra underflow s 00h to ffh rw when the tstop bit in the trbcr register is set to 1, the trbpre register is set to ffh. programmable w aveform generation mode rw 00h to ffh programmable one-shot generation mode 00h to ffh rw programmable w ait one-shot generation mode timer rb secondary register (3, 4) symbol address after reset trbsc 010dh ffh mode function setting range rw notes: 1. 2. 3. 4. timer mode ? disabled 00h to ffh b0 b7 wo (2) counts timer rb prescaler underflow s (1) 00h to ffh programmable one-shot generation mode disabled 00h to ffh ? programmable w aveform generation mode to w rite to the trbsc register, perform the follow ing steps. (1) write the value to the trbsc register. (2) write the value to the trbpr register. (if the value does not change, w rite the same value second time.) the count value can be read out by reading the trbpr register even w hen the secondary period is being counted. programmable w ait one-shot generation mode counts timer rb prescaler underflow s (one-shot w idth is counted) 00h to ffh wo (2) the values of registers trbpr and trbsc are reloaded to the counter alternately and counted. when the tstop bit in the trbcr register is set to 1, the trbsc register is set to ffh. timer rb primary register (2) symbol address after reset trbpr 010eh ffh mode function setting range rw notes: 1. 2. when the tstop bit in the trbcr register is set to 1, the trbpr register is set to ffh. programmable w aveform generation mode rw counts timer rb prescaler underflow s (1) 00h to ffh programmable one-shot generation mode counts timer rb prescaler underflow s (one-shot w idth is counted) 00h to ffh rw the values of registers trbpr and trbsc are reloaded to the counter alternately and counted. timer mode rw counts timer rb prescaler underflow s 00h to ffh b7 b0 programmable w ait one-shot generation mode counts timer rb prescaler underflow s (w ait period w idth is counted) 00h to ffh rw r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 163 of 453 rej09b0278-0210 14.2.1 timer mode in timer mode, a count source which is internally gene rated or timer ra underflo ws are counted (refer to table 14.7 specifications of timer mode ). registers trbocr and trbsc are not used in timer mode. figure 14.16 shows the trbioc register in timer mode. figure 14.16 trbioc register in timer mode table 14.7 specifications of timer mode item specification count sources f1, f2, f8, timer ra underflow count operations ? decrement ? when the timer underflows, it reloads t he reload register contents before the count continues (when timer rb underflows, the contents of timer rb primary reload register is reloaded). divide ratio 1/(n+1)(m+1) n: setting value in trbpre register, m: setting value in trbpr register count start condition 1 (count starts) is writte n to the tstart bit in the trbcr register. count stop conditions ? 0 (count stops) is writ ten to the tstart bit in the trbcr register. ? 1 (count forcibly stop) is written to the tstop bit in the trbcr register. interrupt request generation timing when timer rb underflow s [timer rb interrupt] trbo pin function programmable i/o port int0 pin function programmable i/o port or int0 interrupt input read from timer the count value can be read out by reading registers trbpr and trbpre. write to timer ? when registers trbpre and tr bpr are written while the count is stopped, values are written to both the reload register and counter. ? when registers trbpre and trbpr are written to while count operation is in progress: if the twrc bit in the trbmr register is set to 0, the value is written to both the reload register and the counter. if the twrc bit is set to 1, the value is written to the reload register only. (refer to 14.2.1.1 timer wr ite control during count operation .) timer rb i/o control registe r symbol address after reset trbioc 010ah 00h bit symbol bit name function rw nothing is assigned. if necessary, set to 0. when read, the content is 0. one-shot trigger polarity select bit ? (b7-b4) ? b3 b2 inoseg b1 b0 00 inostg tocnt b7 b6 b5 b4 00 topl timer rb output level select bit rw rw one-shot trigger control bit set to 0 in timer mode. rw rw timer rb output sw itch bit r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 164 of 453 rej09b0278-0210 14.2.1.1 timer write control during count operation timer rb has a prescaler and a timer (which counts the prescaler underflows). the prescaler and timer each consist of a reload register and a co unter. in timer mode, the twrc bit in the trbmr register can be used to select whether writing to the prescaler or timer during count operation is performed to both the reload register and counter or only to the reload register. however, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. in addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflow s. therefore, even if the twrc bit is set for writing to both the reload register and counter, the counter va lue is not updated immediately after the write instruction is executed. in addition, if the twrc bit is set for writing to the reload register only, the synchronization of the writing will be shifted if the prescaler value changes. figure 14.17 shows an operating example of timer rb when counter value is rewritten during count operation. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 165 of 453 rej09b0278-0210 figure 14.17 operating example of timer rb when counter value is rewritten during count operation count source reloads register of timer rb prescaler ir bit in trbic register 0 counter of timer rb prescaler reloads register of timer rb counter of timer rb set 01h to the trbpre register and 25h to the trbpr register by a program. after writing, the reload register is written with the first count source. reload with the second count source reload on underflow after writing, the reload register is written on the first underflow. reload on the second underflow the ir bit remains unchanged until underflow is generated by a new value. when the twrc bit is set to 0 (write to reload register and counter) count source reloads register of timer rb prescaler ir bit in trbic register counter of timer rb prescaler reloads register of timer rb counter of timer rb set 01h to the trbpre register and 25h to the trbpr register by a program. after writing, the reload register is written with the first count source. reload on underflow after writing, the reload register is written on the first underflow. reload on underflow only the prescaler values are updated, extending the duration until timer rb underflow. when the twrc bit is set to 1 (write to reload register only) 05h 04h 03h 02h 01h 00h 01h 00h 01h 00h 06h 01h 00h 01h 03h 00h 02h 01h 25h new value (25h) previous value new value (01h) previous value new value (01h) previous value 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h 06h new value (25h) previous value 03h 24h 02h 25h the above applies under the following conditions. both bits tstart and tcstf in the trb cr register are set to 1 (during count). 0 r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 166 of 453 rej09b0278-0210 14.2.2 programmable waveform generation mode in programmable waveform generation mode, the signal output from the trbo pin is inverted each time the counter underflows, while the valu es in registers trbpr and trbsc are counted alternately (refer to table 14.8 specifications of programma ble waveform ge neration mode ). counting starts by counting the setting value in the trbpr register. the trbocr register is unused in this mode. figure 14.18 shows the trbioc register in programma ble waveform generation mode. figure 14.19 shows an operating example of timer rb in programmable waveform generation mode. notes: 1. even when counting the secondary period, the trbpr register may be read. 2. the set values are reflected in the waveform output beginning with the following primary period after writing to the trbpr register. 3. the value written to the tocnt bit is enabled by the following. ? when counting starts. ? when a timer rb interrup t request is generated. the contents after the tocnt bit is changed are reflected from the output of the following primary period. table 14.8 specifications of programmable waveform generation mode item specification count sources f1, f2, f8, timer ra underflow count operations ? decrement ? when the timer underflows, it reloads t he contents of the primary reload and secondary reload registers alternately before the count continues. width and period of output waveform primary period: (n+1)(m+1)/fi secondary period: (n+1)(p+1)/fi period: (n+1){(m+1)+(p+1)}/fi fi: count source frequency n: value set in trbpre register, m: value set in trbpr register p: value set in trbsc register count start condition 1 (count start) is writt en to the tstart bit in the trbcr register. count stop conditions ? 0 (count stop) is writte n to the tstart bit in the trbcr register. ? 1 (count forcibly stop) is written to the tstop bit in the trbcr register. interrupt request generation timing in half a cycle of the count source, after timer rb underflows during the secondary period (at the same time as the trbo output change) [timer rb interrupt] trbo pin function programmable output port or pulse output int0 pin function programmable i/o port or int0 interrupt input read from timer the count value can be read out by reading registers trbpr and trbpre. (1) write to timer ? when registers trbpre, trbsc , and trbpr are writte n while the count is stopped, values are written to bot h the reload register and counter. ? when registers trbpre, trbsc, and tr bpr are written to during count operation, values are written to the reload registers only. (2) select functions ? output level select function the topl bit in the trbioc register se lects the output level during primary and secondary periods. ? trbo pin output switch function timer rb pulse output or p3_1 (p1_3) latch output is selected by the tocnt bit in the trbioc register. (3) ? trbo pin select function p3_1 or p1_3 is selected by the trbosel bit in the pinsr2 register. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 167 of 453 rej09b0278-0210 figure 14.18 trbioc register in programmable waveform generation mode timer rb i/o control registe r symbol address after reset trbioc 010ah 00h bit symbol bit name function rw ? (b7-b4) ? rw rw one-shot trigger control bit nothing is assigned. if necessary, set to 0. when read, the content is 0. one-shot trigger polarity select bit set to 0 in programmable w aveform generation mode. rw tocnt rw 00 topl timer rb output level select bit 0 : outputs ?h? for primary period outputs ?l? for secondary period outputs ?l? w hen the timer is stopped 1 : outputs ?l? for primary period outputs ?h? for secondary period outputs ?h? w hen the timer is stopped timer rb output sw itch bit 0 : outputs timer rb w aveform 1 : outputs value in p3_1 (p1_3) port register b7 b6 b5 b4 b3 b2 inoseg b1 b0 inostg r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 168 of 453 rej09b0278-0210 figure 14.19 operating example of timer rb in programmable waveform generation mode 1 0 1 0 ir bit in trbic register 1 0 count source timer rb prescaler underflow signal counter of timer rb trbo pin output topl bit in trbio register set to 1 by program set to 0 when interrupt request is acknowledged, or set by program. the above applies under the following conditions. tstart bit in trbcr register 1 0 01h 00h 02h timer rb secondary reloads timer rb primary reloads set to 0 by program trbpre = 01h, trbpr = 01h, trbsc = 02h trbioc register tocnt = 0 (timer rb waveform is output from the trbo pin) 02h 01h 00h 01h 00h primary period primary period secondary period waveform output starts waveform output inverted waveform output starts initial output is the same level as during secondary period. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 169 of 453 rej09b0278-0210 14.2.3 programmable one-shot generation mode in programmable one-shot generation mode, a one-shot pulse is output from the trbo pin by a program or an external trigger input (input to the int0 pin) (refer to table 14.9 specifi cations of programmable one-shot generation mode ). when a trigger is generated, the timer starts operating from the point only once for a given period equal to the set value in the trbpr register . the trbsc register is not used in this mode. figure 14.20 shows the trbioc register in program mable one-shot generation mode. figure 14.21 shows an operating example of program mable one-shot generation mode. notes: 1. the set value is reflected at the following one- shot pulse after writing to the trbpr register. 2. do not set both the trbpre and trbpr registers to 00h. table 14.9 specifications of programmable one-shot generation mode item specification count sources f1, f2, f8, timer ra underflow count operations ? decrement the setting value in the trbpr register ? when the timer underflows, it reloads the contents of the reload register before the count completes and the tosstf bit is set to 0 (one-shot stops). ? when the count stops, the timer reloads the contents of the reload register before it stops. one-shot pulse output time (n+1)(m+1)/fi fi: count source frequency, n: setting value in trbpre register , m: setting value in trbpr register (2) count start conditions ? the tstart bit in the trbcr re gister is set to 1 (count starts) and the next trigger is generated ? set the tosst bit in the trbocr register to 1 (one-shot starts) ? input trigger to the int0 pin count stop conditions ? when reloading completes after timer rb underflows during primary period ? when the tossp bit in the trbocr regi ster is set to 1 (one-shot stops) ? when the tstart bit in the trbcr re gister is set to 0 (stops counting) ? when the tstop bit in the trbcr register is set to 1 (forcibly stops counting) interrupt request generation timing in half a cycle of the count source, after the timer underflows (at the same time as the trbo output ends) [timer rb interrupt] trbo pin function pulse output int0 pin functions ? when the inostg bit in the trbioc register is set to 0 (int0 one-shot trigger disabled): programmable i/o port or int0 interrupt input ? when the inostg bit in the trbioc register is set to 1 (int0 one-shot trigger enabled): external trigger (int0 interrupt input) read from timer the count value can be read out by reading registers trbpr and trbpre. write to timer ? when registers trbpre and tr bpr are written while the count is stopped, values are written to both the reload register and counter. ? when registers trbpre and trbpr are written during the count, values are written to the reload register only (the data is transferred to the counter at the following reload). (1) select functions ? output level select function the topl bit in the trbioc register selects the output level of the one-shot pulse waveform. ? one-shot trigger select function refer to 14.2.3.1 one-shot trigger selection . ? trbo pin select function p3_1 or p1_3 is selected by the trbosel bit in the pinsr2 register. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 170 of 453 rej09b0278-0210 figure 14.20 trbioc register in programmable one-shot generation mode timer rb i/o control registe r symbol address after reset trbioc 010ah 00h bit symbol bit name function rw 0 : int0 _ ____ pin one-shot trigger disabled 1 : int0 _ ____ pin one-shot trigger enabled note: 1. rw rw one-shot trigger control bit (1) 0 : falling edge trigger 1 : rising edge trigger rw tocnt rw topl timer rb output level select bit 0 : outputs one-shot pulse ?h? outputs ?l? w hen the timer is stopped 1 : outputs one-shot pulse ?l? outputs ?h? w hen the timer is stopped timer rb output sw itch bit set to 0 in programmable one-shot generation mode. b7 b6 b5 b4 b3 b2 inoseg b1 b0 0 inostg ref er to 14.2.3.1 one-shot trigger selection . nothing is assigned. if necessary, set to 0. when read, its content is 0. one-shot trigger polarity select bit (1) ? (b7-b4) ? r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 171 of 453 rej09b0278-0210 figure 14.21 operating example of programmable one-shot generation mode tosstf bit in trbocr register int0 pin input 1 0 1 0 ir bit in trbic register 1 0 count source timer rb prescaler underflow signal counter of timer rb trbio pin output topl bit in trbioc register set to 1 by program set to 1 by program set to 0 when interrupt request is acknowledged, or set by program the above applies under the following conditions. tstart bit in trbcr register 1 0 1 0 01h 00h 01h 00h 01h count starts timer rb primary reloads count starts timer rb primary reloads set to 0 by program waveform output starts waveform output ends waveform output starts waveform output ends set to 0 when counting ends set to 1 by int0 pin input trigger trbpre = 01h, trbpr = 01h trbioc register topl = 0, tocnt = 0 inostg = 1 (int0 one-shot trigger enabled) inoseg = 1 (edge trigger at rising edge) r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 172 of 453 rej09b0278-0210 14.2.3.1 one-shot trigger selection in programmable one-shot generation mode and programm able wait one-shot generation mode, operation starts when a one-shot trigger is generated while the tcstf b it in the trbcr register is set to 1 (count starts). a one-shot trigger can be generated by either of the following causes: ? 1 is written to the tosst bit in the trbocr register by a program. ? trigger input from the int0 pin. when a one-shot trigger occurs, the tosstf bit in the trbocr register is set to 1 (one-shot operation in progress) after one or two cycles of the count source have elapsed. then, in programmable one-shot generation mode, count operation begins and one-shot waveform ou tput starts. (in programmable wait one-shot generation mode, count operation starts for the wait period.) if a one- shot trigger occurs while the tosstf bit is set to 1, no retriggering occurs. to use trigger input from the int0 pin, input the trigger after making the following settings: ? set the pd4_5 bit in the pd4 register to 0 (input port). ? select the int0 digital filter with bits int0f1 and int0f0 in the intf register. ? select both edges or one edge with th e int0pl bit in inten register. if one edge is selected, further select falling or rising edge with the inoseg bit in trbioc register. ? set the int0en bit in the in ten register to 0 (enabled). ? after completing the above, set the inostg bit in the trbioc register to 1 (int pin one-shot trigger enabled). note the following points with regard to generatin g interrupt requests by trigger input from the int0 pin. ? processing to handle the interrupts is required. refer to 12. interrupts , for details. ? if one edge is selected, use the pol bit in the int0 ic register to select falling or rising edge. (the inoseg bit in the trbioc register does not affect int0 interrupts). ? if a one-shot trigger occurs while the tosstf bit is set to 1, timer rb operation is not affected, but the value of the ir bit in th e int0ic register changes. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 173 of 453 rej09b0278-0210 14.2.4 programmable wait one-shot generation mode in programmable wait one-shot generation mode, a one-shot pulse is output from the trbo pin by a program or an external trigger input (input to the int0 pin) (refer to table 14.10 specifications of programmable wait one-shot generation mode ). when a trigger is generated from that point, the timer outputs a pulse only once for a given length of time equal to the setting value in the trbsc register after waiting for a given length of time equal to the setting value in the trbpr register. figure 14.22 shows the trbioc register in programm able wait one-shot generation mode. figure 14.23 shows an operating example of programmable wait one-shot generation mode. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 174 of 453 rej09b0278-0210 notes: 1. the set value is reflected at the following one-shot pulse after writing to registers trbsc and trbpr. 2. do not set both the trbpre and trbpr registers to 00h. table 14.10 specifications of programmable wait one-shot generation mode item specification count sources f1, f2, f8, timer ra underflow count operations ? decrement the timer rb primary setting value. ? when a count of the timer rb primar y underflows, the timer reloads the contents of timer rb secondar y before the count continues. ? when a count of the timer rb second ary underflows, the timer reloads the contents of timer rb primary before the count completes and the tosstf bit is set to 0 (one-shot stops). ? when the count stops, the timer reload s the contents of the reload register before it stops. wait time (n+1)(m+1)/fi fi: count source frequency n: value set in the trbpre register , m value set in the trbpr register (2) one-shot pulse output time (n+1)(p+1)/fi fi: count source frequency n: value set in the trbpre register, p: value set in the trbsc register count start conditions ? the tstart bit in the trbcr register is set to 1 (count starts) and the next trigger is generated. ? set the tosst bit in the trbocr register to 1 (one-shot starts). ? input trigger to the int0 pin count stop conditions ? when reloading completes after timer rb underflows during secondary period. ? when the tossp bit in the trbocr regi ster is set to 1 (one-shot stops). ? when the tstart bit in the trbcr register is set to 0 (starts counting). ? when the tstop bit in the trbcr register is set to 1 (forcibly stops counting). interrupt request generation timing in half a cycle of the count source after timer rb underflows during secondary period (complete at the same time as waveform output from the trbo pin) [timer rb interrupt] trbo pin function pulse output int0 pin functions ? when the inostg bit in the trbioc register is set to 0 (int0 one-shot trigger disabled): programmable i/o port or int0 interrupt input ? when the inostg bit in the trbioc register is set to 1 (int0 one-shot trigger enabled): external trigger (int0 interrupt input) read from timer the count value can be read out by reading registers trbpr and trbpre. write to timer ? when registers trbpre, tr bsc, and trbpr are written while the count stops, values are written to both the reload register and counter. ? when registers trbpre, trbsc, and trbpr are written to during count operation, values are written to the reload registers only. (1) select functions ? output level select function the topl bit in the trbioc register selects the output level of the one- shot pulse waveform. ? one-shot trigger select function refer to 14.2.3.1 one-shot trigger selection . ? trbo pin select function p3_1 or p1_3 is selected by the trbosel bit in the pinsr2 register. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 175 of 453 rej09b0278-0210 figure 14.22 trbioc register in progra mmable wait one-shot generation mode timer rb i/o control registe r symbol address after reset trbioc 010ah 00h bit symbol bit name function rw 0 : int0 _ ____ pin one-shot trigger disabled 1 : int0 _ ____ pin one-shot trigger enabled note: 1. nothing is assigned. if necessary, set to 0. when read, the content is 0. one-shot trigger polarity select bit (1) ? (b7-b4) ? ref er to 14.2.3.1 one-shot trigger selection . b3 b2 inoseg b1 b0 0 inostg rw b7 b6 b5 b4 tocnt rw topl timer rb output level select bit 0 : outputs one-shot pulse ?h?. outputs ?l? w hen the timer stops or during w ait. 1 : outputs one-shot pulse ?l?. outputs ?h? w hen the timer stops or during w ait. timer rb output sw itch bit set to 0 in programmable w ait one-shot generation mode. rw rw one-shot trigger control bit (1) 0 : falling edge trigger 1 : rising edge trigger r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 176 of 453 rej09b0278-0210 figure 14.23 operating example of programmable wait one-shot generation mode tosstf bit in trbocr register int0 pin input 1 0 1 0 ir bit in trbic register 1 0 count source timer rb prescaler underflow signal counter of timer rb trbio pin output topl bit in trbioc register set to 1 by program set to 1 by setting 1 to tosst bit in trbocr register, or int0 pin input trigger. set to 0 when interrupt request is acknowledged, or set by program. the above applies under the following conditions. tstart bit in trbcr register 1 0 1 0 01h 00h 00h 01h count starts timer rb secondary reloads timer rb primary reloads set to 0 by program wait starts waveform output starts waveform output ends set to 0 when counting ends trbpre = 01h, trbpr = 01h, trbsc = 04h inostg = 1 (int0 one-shot trigger enabled) inoseg = 1 (edge trigger at rising edge) 04h 03h 02h 01h wait (primary period) one-shot pulse (secondary period) r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 177 of 453 rej09b0278-0210 14.2.5 notes on timer rb ? timer rb stops counting after a reset. set the values in the timer rb and timer rb prescalers before the count starts. ? even if the prescaler and timer rb is read out in 16-bit units, these registers are read 1 byte at a time by the mcu. consequently, the timer value may be updated during the period when these two registers are being read. ? in programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the tstart bit in the trbcr register to 0, 0 (stops counting) or setting the tossp bit in the trbocr register to 1 (stops one-shot), the timer reload s the value of reload register and stops. therefore, in programmable one-shot generation mode and prog rammable wait one-shot generation mode, read the timer count value before the timer stops. ? the tcstf bit remains 0 (count stops) for 1 to 2 cycl es of the count source after setting the tstart bit to 1 (count starts) while the count is stopped. during this time, do not access re gisters associated with timer rb (1) other than the tcstf bit. timer rb starts counting at the first valid edge of the count source after the tcstf bit is set to 1 (during count). the tcstf bit remains 1 for 1 to 2 cycles of the count source after setting the tstart bit to 0 (count stops) while the count is in progress. timer rb count ing is stopped when the tcstf bit is set to 0. during this time, do not access re gisters associated with timer rb (1) other than the tcstf bit. note: 1. registers associated with timer rb: trbcr, trbocr, trbioc, trbmr, trbpre, trbsc, and trbpr. ? if the tstop bit in the trbcr register is set to 1 during timer operation, timer rb stops immediately. ? if 1 is written to the tosst or tossp bit in the t rbocr register, the value of the tosstf bit changes after one or two cycles of the count source have elapsed. if the tossp bit is written to 1 during the period between when the tosst bit is written to 1 and when the tosstf bit is set to 1, the tosstf bit may be set to either 0 or 1 depending on the content state. likewise, if the tosst bit is written to 1 during the period between when the tossp bit is written to 1 and when th e tosstf bit is set to 0, the tosstf bit may be set to either 0 or 1. 14.2.5.1 timer mode the following workaround should be performed in timer mode. to write to registers trbpre and trbpr during count operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously, allow th ree or more cycles of the count source for each write interval. ? when the trbpr register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 178 of 453 rej09b0278-0210 14.2.5.2 programmable waveform generation mode the following three workarounds should be performe d in programmable waveform generation mode. (1) to write to registers trbpre and trbpr during c ount operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously, allow th ree or more cycles of the count source for each write interval. ? when the trbpr register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. (2) to change registers trbpre and trbpr during coun t operation (tcstf bit is set to 1), synchronize the trbo output cycle using a timer rb interrupt, etc. this operation should be preformed only once in the same output cycle. also, make sure that writi ng to the trbpr register does not occur during period a shown in figures 14.24 and 14.25. the following shows the detailed workaround examples. ? workaround example (a): as shown in figure 14.24, write to registers trbsc and trbpr in the timer rb interrupt routine. these write operations must be completed by the beginning of period a. figure 14.24 workaround example (a) when timer rb interrupt is used trbo pin output count source/ prescaler underflow signal primary period period a ir bit in trbic register secondary period (b) interrupt sequence instruction in interrupt routine interrupt request is acknowledged (a) interrupt request is generated ensure sufficient time set the secondary and then the primary register immediately (a) period between interrupt request generation and the completion of execution of an instruction. the length of time varies depending on the instruction being executed. the divx instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 20 cycles. 21 cycles for address match and single-step interrupts. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 179 of 453 rej09b0278-0210 ? workaround example (b): as shown in figure 14.25 detect the start of the primary period by the trbo pin output level and write to registers trbsc and trbpr. these write operations must be completed by the beginning of period a. if the port register?s bit value is read after the port direction register?s bit corresponding to the trbo pin is set to 0 (input mode), the read value indicates the trbo pin output value. figure 14.25 workaround example (b) when trbo pin output value is read (3) to stop the timer counting in the primary period, use the tstop bit in the trbcr register. in this case, registers trbpre and trbpr are initialized and th eir values are set to the values after reset. 14.2.5.3 programmable one-shot generation mode the following two workarounds should be performe d in programmable one-shot generation mode. (1) to write to registers trbpre and trbpr during c ount operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously du ring count operation (tcstf bit is set to 1), allow three or more cycles of the co unt source for each write interval. ? when the trbpr register is written continuously du ring count operation (tcstf bit is set to 1), allow three or more cycles of the prescal er underflow for each write interval. (2) do not set both the trbpre and trbpr registers to 00h. trbo pin output count source/ prescaler underflow signal primary period period a read value of the port register?s bit corresponding to the trbo pin (when the bit in the port direction register is set to 0) secondary period (i) the trbo output inversion is detected at the end of the secondary period. ensure sufficient time upon detecting (i), set the secondary and then the primary register immediately. (ii) (iii) r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 180 of 453 rej09b0278-0210 14.2.5.4 programmable wait one-shot generation mode the following three workarounds should be performe d in programmable wait one-shot generation mode. (1) to write to registers trbpre and trbpr during c ount operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously, allow th ree or more cycles of the count source for each write interval. ? when the trbpr register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. (2) do not set both the trbpre and trbpr registers to 00h. (3) set registers trbsc and trbpr using the following procedure. (a) to use ?int0 pin one-shot trigger enabled? as the count start condition set the trbsc register an d then the trbpr register. at this time, after writing to the trbpr register, allow an interval of 0.5 or more cycles of the count source before trigger input from the int0 pin. (b) to use ?writing 1 to tosst bit? as the start condition set the trbsc register, the trbpr register, and then tosst bit. at this time, after writing to the trbpr register, allow an interval of 0.5 or more cycles of the count source before writing to the tosst bit. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 181 of 453 rej09b0278-0210 14.3 timer rc 14.3.1 overview timer rc is a 16-bit timer with four i/o pins. timer rc uses either f1 or foco40m as its operation clock. table 14.11 lists the timer rc operation clock. table 14.12 lists the timer rc i/o pins, and figure 14.26 shows a timer rc block diagram. timer rc has three modes. ? timer mode - input capture function the counter value is captured to a register, using an external signal as the trigger. - output compare function matches between the counter and register values are detected. (pin output state changes when a match is detected.) the following two modes use the output compare function. ? pwm mode pulses of a given width are output continuously. ? pwm2 mode a one-shot waveform or pwm waveform is output following the trigger after the wait time has elapsed. input capture function, output compare function, and pw m mode settings may be specified independently for each pin. in pwm2 mode waveforms are output based on a combination of the counter or the register. table 14.11 timer rc operation clock condition timer rc operation clock count source is f1, f2, f4, f8, f32, or trcclk input (bits tck2 to tck0 in trccr1 register are set to a value from 000b to 101b) f1 count source is foco40m (bits tck2 to tck0 in trccr1 register are set to 110b) foco40m r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 182 of 453 rej09b0278-0210 figure 14.26 timer rc block diagram note: 1. the pins used for trcioc and trciod are selectable. refer to the description of the bits trciocsel and trciodsel in the pinsr3 register in figure 7.10 registers pinsr1, pinsr2, and pinsr3 for details. table 14.12 timer rc i/o pins pin name i/o function trcioa(p1_1) trciob(p1_2) trcioc(p5_3 or p3_4) (1) trciod(p5_4 or p3_5) (1) i/o function differs according to the mode. refer to descriptions of individual modes for details trcclk(p3_3) input external clock input trctrg(p1_1) input pwm2 mode external trigger input trcmr register data bus trccr1 register trcier register trcsr register trcior0 register trc register trcgra register trcgrb register trcgrc register trcgrd register trccr2 register trcdf register trcoer register timer rc control circuit int0 trcclk count source select circuit f1, f2, f4, f8, f32, foco40m timer rc interrupt request trcior1 register trciob trcioc trciod trcioa/trctrg r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 183 of 453 rej09b0278-0210 14.3.2 registers associated with timer rc table 14.13 lists the registers associat ed with timer rc. figures 14.27 to 14.36 show details of the registers associated with timer rc. ? : invalid table 14.13 registers associated with timer rc address symbol mode related information timer pwm pwm2 input capture function output compare function 0120h trcmr valid valid valid valid timer rc mode register figure 14.27 trcmr register 0121h trccr1 valid valid valid valid timer rc control register 1 figure 14.28 trccr1 register figure 14.49 trccr1 register for output compare function figure 14.52 trccr1 register in pwm mode figure 14.56 trccr1 register in pwm2 mode 0122h trcier valid valid valid valid timer rc interrupt enable register figure 14.29 trcier register 0123h trcsr valid valid valid valid timer rc status register figure 14.30 trcsr register 0124h trcior0 valid valid ?? timer rc i/o control register 0, timer rc i/o control register 1 figure 14.36 registers trcior0 and trcior1 figure 14.43 trcior0 register for input capture function figure 14.44 trcior1 register for input capture function figure 14.47 trcior0 register for output compare function figure 14.48 trcior1 register for output compare function 0125h trcior1 0126h 0127h trc valid valid valid valid timer rc counter figure 14.31 trc register 0128h 0129h trcgra valid valid valid valid timer rc general registers a, b, c, and d figure 14.32 registers trcgra, trcgrb, trcgrc, and trcgrd 012ah 012bh trcgrb 012ch 012dh trcgrc 012eh 012fh trcgrd 0130h trccr2 ??? valid timer rc control register 2 figure 14.33 trccr2 register 0131h trcdf valid ?? valid timer rc digital filter function select register figure 14.34 trcdf register 0132h trcoer ? valid valid valid timer rc output mask enable register figure 14.35 trcoer register r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 184 of 453 rej09b0278-0210 figure 14.27 trcmr register timer rc mode register (1) symbol address after reset trcmr 0120h 01001000b bit symbol bit name function rw notes: 1. 2. ? rw tsta rt rw trc count start bit 0 : count stops 1 : count starts pwm mode of trciob select bit (2) 0 : timer mode 1 : pwm mode trcgrc register function select bit (3) pwm mode of trcioc select bit (2) nothing is assigned. if necessary, set to 0. when read, the content is 1. ? (b6) bfc b7 b6 b5 b4 rw rw pwmb 0 : general register 1 : buffer register of trcgra register trcgrd register function select bit 0 : general register 1 : buffer register of trcgrb register 0 : timer mode 1 : pwm mode rw pwmd pwm mode of trciod select bit (2) b3 b2 bfd b1 b0 pwmc these bits are enabled w hen the pwm2 bit is set to 1 (timer mode or pwm mode). 3. set the bfc bit to 0 (general register) in pwm2 mode. 0 : timer mode 1 : pwm mode rw pwm2 pwm2 mode select bit 0 : pwm 2 mode 1 : timer mode or pwm mode rw for notes on pwm2 mode, refer to 14.3.9.5 trcmr register in pwm2 mode . r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 185 of 453 rej09b0278-0210 figure 14.28 trccr1 register timer rc control register 1 symbol address after reset trccr1 0121h 00h bit symbol bit name function rw notes: 1. 2. 3. the trc counter performs free-running operation for the input capture function of the timer mode independent of the cclr bit setting. count source select bits (1) b6 b5 b4 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : trcclk input rising edge 1 1 0 : foco40m 1 1 1 : do not set. 0 : disable clear (free-running operation) 1 : clear by compare match in the trcgra register bits cclr, toa, tob, toc and tod are disabled for the input capture function of the timer mode. tck0 tck1 rw trc counter clear select bit (2, 3) tck2 set to these bits w hen the tstart bit in the trcmr register is set to 0 (count stops). toc rw rw rw rw trciod output level select bit (1) cclr rw trcioc output level select bit (1) rw tob rw trcioa output level select bit (1) trciob output level select bit (1) function varies according to the operating mode (function). (2) b7 b6 b5 b4 b3 b2 tod b1 b0 toa r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 186 of 453 rej09b0278-0210 figure 14.29 trcier register timer rc interrupt enable register symbol address after reset trcier 0122h 01110000b bit symbol bit name function rw rw input capture / compare match interrupt enable bit d 0 : disable interrupt (imid) by the imfd bit 1 : enable interrupt (imid) by the imfd bit input capture / compare match interrupt enable bit c 0 : disable interrupt (imic) by the imfc bit 1 : enable interrupt (imic) by the imfc bit imiec rw overflow interrupt enable bit 0 : disable interrupt (ovi) by the ovf bit 1 : enable interrupt (ovi) by the ovf bit ? (b6-b4) ? rw ov ie nothing is assigned. if necessary, set to 0. when read, the content is 1. rw imieb rw input capture / compare match interrupt enable bit a 0 : disable interrupt (imia) by the imfa bit 1 : enable interrupt (imia) by the imfa bit input capture / compare match interrupt enable bit b 0 : disable interrupt (imib) by the imfb bit 1 : enable interrupt (imib) by the imfb bit imiea b7 b6 b5 b4 b3 b2 imied b1 b0 r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 187 of 453 rej09b0278-0210 figure 14.30 trcsr register timer rc status register symbol address after reset trcsr 0123h 01110000b bit symbol bit name function rw note: 1. ? (b6-b4) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. rw ov f overflow flag [source for setting this bit to 0] write 0 after read. (1) [source for setting this bit to 1] refer to the table below . input capture / compare match flag c imfc rw [source for setting this bit to 0] write 0 after read. (1) [source for setting this bit to 1] refer to the table below . rw input capture / compare match flag d rw imfb rw input capture / compare match flag a input capture / compare match flag b imfa b7 b6 b5 b4 the w riting results are as follow s: ? this bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. ? this bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (this bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0.) ? this bit remains unchanged if 1 is w ritten to it. b3 b2 imfd b1 b0 input capture function output compare func tion trcioa pin input edge (1) trciob pin input edge (1) trcioc pin input edge (1) trciod pin input edge (1) notes: 1. 2. edge selected by bits ioj1 to ioj0 (j = a, b, c, or d). includes the condition that bits bfc and bfd are set to 1 (buffer registers of registers trcgra and trcgrb) . bit symbol imfa imfb imfc imfd ov f when the values of the registers trc and trcgrc ma t c h . (2) when the values of the registers trc and trcgrd ma t c h . (2) pwm2 mode when the trc register overflow s. when the values of the registers trc and trcgra match. when the values of the registers trc and trcgrb match. timer mode pwm mo d e r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 188 of 453 rej09b0278-0210 figure 14.31 trc register figure 14.32 registers trcgra, trcgrb, trcgrc, and trcgrd timer rc counter (1) symbol address after reset trc 0127h-0126h 0000h setting range rw note: 1. (b8) b0 ( b15) b7 access the trc register in 16-bit units. do not access it in 8-bit units. b0 b7 function count a count source. count operation is incremented. when an overflow occurs, the ovf bit in the trcsr register is set to 1. 0000h to ffffh rw timer rc general register a, b, c and d (1) symbol address after reset trcgra trcgrb trcgrc trcgrd 0129h-0128h 012bh-012ah 012dh-012ch 012fh-012eh ffffh ffffh ffffh ffffh rw note: 1. rw function function varies according to the operating mode. access registers trcgra to trcgrd in 16-bit units. do not access them in 8-bit units. b0 b7 (b8) b0 ( b15) b7 r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 189 of 453 rej09b0278-0210 figure 14.33 trccr2 register timer rc control register 2 symbol address after reset trccr2 0130h 00011111b bit symbol bit name function rw notes: 1. 2. 3. ? (b4-b0) nothing is assigned. if necessary, set to 0. when read, the content is 1. ? trc count operation select bit (1, 2) 0 : count continues at compare match w ith the trcgra register 1 : count stops at compare match w ith the trcgra register rw in timer mode and pwm mode these bits are disabled. in timer mode and pwm mode this bit is disabled (the count operation continues independent of the csel bit setting). tceg1 for notes on pwm2 mode, refer to 14.3.9.5 trcmr register in pwm2 mode . b3 b2 tceg0 b1 b0 csel b7 b6 b5 b4 rw rw trctrg input edge select bits (3) b7 b6 0 0 : disable the trigger input from the trctrg pin 0 1 : rising edge selected 1 0 : falling edge selected 1 1 : both edges selected r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 190 of 453 rej09b0278-0210 figure 14.34 trcdf register timer rc digital filter function select register symbol address after reset trcdf 0131h 00h bit symbol bit name function rw notes: 1. 2. these bits are enabled for the input capture function. these bits are enabled w hen in pwm2 mode and bits tceg1 to tceg0 in the trccr2 register are set to 01b, 10b, or 11b (trctrg trigger input enabled). nothing is assigned. if necessary, set to 0. when read, the content is 0. clock select bits for digital filter function (1, 2) ? (b5) dfck0 rw ? b7 b6 0 0 : f32 0 1 : f8 1 0 : f1 1 1 : count source (clock selected by bits tck2 to tck0 in the trccr1 register) b3 b2 dfd b1 b0 dfc b7 b6 b5 b4 rw dfb rw dfa trcioa pin digital filter function select bit (1) trciob pin digital filter function select bit (1) 0 : function is not used 1 : function is used rw rw trciod pin digital filter function select bit (1) trcioc pin digital filter function select bit (1) dfck1 rw dftrg trctrg pin digital filter function select bit (2) rw r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 191 of 453 rej09b0278-0210 figure 14.35 trcoer register timer rc output master enable register symbol address after reset trcoer 0132h 01111111b bit symbol bit name function rw int0 _ ____ of pulse output forced 0 : pulse output forced cutoff input disabled cutoff signal input enabled 1 : pulse output forced cutoff input enabled bit (bits ea, eb, ec, and ed are set to 1 (disable output) w hen ?l? is applied to the int0 _ ____ pin) note: 1. ? (b6-b4) these bits are disabled for input pins set to the input capture function. rw ? trciod output disable bit (1) 0 : enable output 1 : disable output (the trciod pin is used as a programmable i/o port.) nothing is assigned. if necessary, set to 0. when read, the content is 1. rw pto trcioc output disable bit (1) 0 : enable output 1 : disable output (the trcioc pin is used as a programmable i/o port.) ec rw rw eb rw trcioa output disable bit (1) 0 : enable output 1 : disable output (the trcioa pin is used as a programmable i/o port.) trciob output disable bit (1) 0 : enable output 1 : disable output (the trciob pin is used as a programmable i/o port.) b7 b6 b5 b4 b3 b2 ed b1 b0 ea r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 192 of 453 rej09b0278-0210 figure 14.36 registers trcior0 and trcior1 timer rc i/o control register 0 (1) symbol address after reset trcior0 0124h 10001000b bit symbol bit name function rw notes: 1. 2. 3. 4. iob2 rw trcgra mode select bit (2) 0 : output compare function 1 : input capture function rw trcgra input capture input sw itch bit (4) 0 : foco128 signal 1 : trcioa pin input rw 0 : output compare function 1 : input capture function rw rw rw ioa 1 ioa0 trcgra control bits function varies according to the operating mode (function). b7 b6 b5 b4 ioa 2 trcgrb mode select bit (3) the trcior0 register is enabled in timer mode. it is disabled in modes pwm and pwm2. ? (b7) b3 b2 ioa 3 b1 b0 the ioa3 bit is enabled w hen the ioa2 bit is set to 1 (input capture function). trcgrb control bits function varies according to the operating mode (function). when the bfd bit in the trcmr register is set to 1 (buffer register of trcgrb register), set the iod2 bit in the trcior1 register to the same value as the iob2 bit in the trcior0 register. ? iob0 iob1 rw nothing is assigned. if necessary, set to 0. when read, the content is 1. when the bfc bit in the trcmr register is set to 1 (buffer register of trcgra register), set the ioc2 bit in the trcior1 register to the same value as the ioa2 bit in the trcior0 register. timer rc i/o control register 1 (1) symbol address after reset trcior1 0125h 10001000b bit symbol bit name function rw notes: 1. 2. 3. the trcior1 register is enabled in timer mode. it is disabled in modes pwm and pwm2. nothing is assigned. if necessary, set to 0. when read, the content is 1. trcgrc mode select bit (2) 0 : output compare function 1 : input capture function rw ? ? (b7) iod2 rw trcgrd c ontr ol bits rw rw ioc1 ioc0 trcgrc control bits function varies according to the operating mode (function). b7 b6 b5 b4 ioc2 0 : output compare function 1 : input capture function b3 b2 ? (b3) b1 b0 rw function varies according to the operating mode (function). when the bfd bit in the trcmr register is set to 1 (buffer register of trcgrb register), set the iod2 bit in the trcior1 register to the same value as the iob2 bit in the trcior0 register. ? iod0 iod1 rw nothing is assigned. if necessary, set to 0. when read, the content is 1. when the bfc bit in the trcmr register is set to 1 (buffer register of trcgra register), set the ioc2 bit in the trcior1 register to the same value as the ioa2 bit in the trcior0 register. trcgrd mode select bit (3) r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 193 of 453 rej09b0278-0210 14.3.3 common items for multiple modes 14.3.3.1 count source the method of selecting the coun t source is common to all modes. table 14.14 lists the count source selection, and figure 14.37 shows a count source block diagram. figure 14.37 count source block diagram the pulse width of the external clock input to the trcclk pin s hould be three cycles or more of the timer rc operation clock (refer to table 14.11 timer rc operation clock ). to select foco40m as the count source, set the fra00 bit in the fra0 register set to 1 (high-speed on-chip oscillator on), and then set bi ts tck2 to tck0 in the trccr1 register to 110b (foco40m). table 14.14 count source selection count source selection method f1, f2, f4, f8, f32 count source selected using bits tck2 to tck0 in trccr1 register foco40m fra00 bit in fra0 register set to 1 (high-speed on-chip os cillator on) and bits tck2 to tck0 in trccr1 regist er are set to 110b (foco40m) external signal input to trcclk pin bits tck2 to tck0 in trccr1 register are set to 101b (count source is rising edge of external clock) and pd3_3 bit in pd 3 register is set to 0 (input mode) tck2 to tck0 trc register tck2 to tck0: bits in trccr1 register f1 f2 f4 f8 f32 = 001b = 010b = 011b = 000b = 110b = 100b count source trcclk = 101b foco40m r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 194 of 453 rej09b0278-0210 14.3.3.2 buffer operation bits bfc and bfd in the trcmr regist er are used to select the trcgrc or trcgrd register as the buffer register for the trcgra or trcgrb register. ? buffer register for trcgra register: trcgrc register ? buffer register for trcgrb register: trcgrd register buffer operation differs depending on the mode. table 14.15 lists the buffer operation in each m ode, figure 14.38 shows the buffer operation for input capture function, and figure 14.39 shows the buffer operation for output compare function. figure 14.38 buffer operation for input capture function table 14.15 buffer operation in each mode function, mode transfer timing transfer destination register input capture function input capture signal input contents of trcgra (trcgrb) register are transferred to buffer register output compare function co mpare match between trc register and trcgra (trcgrb) register contents of buffer register are transferred to trcgra (trcgrb) register pwm mode pwm2 mode ? compare match between trc register and trcgra register ? trctrg pin trigger input contents of buffer register (trcgrd) are transferred to trcgrb register m transfer n n-1 n+1 trcioa input trc register the above applies under the following conditions: ? the bfc bit in the trcmr register is set to 1 (the trcgrc regi ster functions as the buffer r egister for the trcgra register). ? bits ioa2 to ioa0 in the trcior0 register ar e set to 100b (input capture at the rising edge). m transfer n trcgrc register trcgra register trc trcioa input (input capture signal) trcgra register trcgrc register (buffer) r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 195 of 453 rej09b0278-0210 figure 14.39 buffer operation for output compare function make the following settings in timer mode. ? to use the trcgrc register as the buffe r register for the trcgra register: set the ioc2 bit in the trcior1 register to the sa me value as the ioa2 bit in the trcior0 register. ? to use the trcgrd register as the buf fer register for the trcgrb register: set the iod2 bit in the trcior1 register to the sa me value as the iob2 bit in the trcior0 register. the output compare function, pwm mode, or pwm2 mode, and the trcgrc or trcgrd register is functioning as a buffer register, the imfc bit or imfd bit in the trcsr register is set to 1 when a compare match with the trc register occurs. the input capture function and the trcgrc register or trcgrd register is functioning as a buffer register, the imfc bit or imfd bit in the trcsr register is set to 1 at the input edge of a signal input to the trcioc pin or trciod pin. mn trcgra register m-1 m+1 trc register the above applies under the following conditions: ? the bfc bit in the trcmr register is set to 1 (the trcgrc regi ster functions as the buffer r egister for the trcgra register). ? bits ioa2 to ioa0 in the trcior0 register are set to 001b (?l? output at compare match). n transfer trcgrc register (buffer) m trcioa output trcgrc register trcgra register comparator trc compare match signal r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 196 of 453 rej09b0278-0210 14.3.3.3 digital filter the input to trctrg or trcioj (j = a, b, c, or d) is sampled, and the level is considered to be determined when three matches occur. the digital filter function a nd sampling clock are selected using the trcdf register. figure 14.40 shows a block diagram of digital filter. figure 14.40 block diagram of digital filter c dq latch c dq latch c dq latch match detect circuit edge detect circuit dfj (or dftrg) sampling clock ioa2 to ioa0 iob2 to iob0 ioc2 to ioc0 iod2 to iod0 (or tceg1 to tceg0) dfck1 to dfck0 trcioj input signal (or trctrg input signal) clock cycle selected by tck2 to tck0 (or dfck1 to dfck0) sampling clock trcioj input signal (or trctrg input signal) input signal after passing through digital filter if fewer than three matches occur, the matches are treated as noise and no transmission is performed. maximum signal transmission delay is five sampling clock pulses. three matches occur and a signal change is confirmed. f32 f8 f1 j = a, b, c, or d tck0 to tck2: bits in trccr1 register dftrg, dfck0 to dfck1, dfj: bits in trcdf register ioa0 to ioa2, iob0 to iob2: bits in trcior0 register ioc0 to ioc2, iod0 to iod2: bits in trcior1 register tceg1 to tceg0: bits in trccr2 register c dq latch c dq latch timer rc operation clock f1 or foco40m count source = 00b = 01b = 10b = 11b tck2 to tck0 1 0 = 001b = 010b = 011b = 000b = 100b = 101b f1 f32 trcclk f8 f4 f2 foco40m = 110b r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 197 of 453 rej09b0278-0210 14.3.3.4 forced cutoff of pulse output when using the timer mode?s output compare function, the pwm mode, or the pwm2 mode, pulse output from the trcioj (j = a, b, c, or d) output pin can be fo rcibly cut off and the trcioj pin set to function as a programmable i/o port by means of input to the int0 pin. a pin used for output by the timer mode?s output compare function, the pwm mode, or the pwm2 mode can be set to function as the timer rc output pin by setting the ej bit in the trcoer register to 0 (timer rc output enabled). if ?l? is input to the int0 pin while the pto bit in the trcoer register is set to 1 (pulse output forced cutoff signal input int0 enabled), bits ea, eb, ec , and ed in the trcoer re gister are all set to 1 (timer rc output disabled, trcioj output pin functions as the programmable i/ o port). when one or two cycles of the timer rc operation clock after ?l? input to the int0 pin (refer to table 14.11 timer rc operation clock ) has elapsed, the trcioj output pin becomes a programmable i/o port. make the following settings to use this function. ? set the pin state following forced cutoff of pulse output (high impedance (input), ?l? output, or ?h? output) (refer to 7. programmable i/o ports ). ? set the int0en bit to 1 (int0 input enabled) and the int0pl bit to 0 (one edge) in the inten register. ? set the pd4_5 bit in the pd4 register to 0 (input mode). ? select the int0 digital filter by means of bits int0f1 to int0f0 in the intf register. ? set the pto bit in the trcoer register to 1 (pulse output forced cutoff signal input int0 enabled). the ir bit in the int0ic register is set to 1 (interrupt request) in accordan ce with the setting of the pol bit and a change in the int0 pin input (refer to 12.6 notes on interrupts ). for details on interrupts, refer to 12. interrupts . r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 198 of 453 rej09b0278-0210 figure 14.41 forced cutoff of pulse output int0 input trcioa pto bit d s q ea bit ea bit write value trciob d s q eb bit eb bit write value trcioc d s q ec bit ec bit write value trciod d s q ed bit ed bit write value ea, eb, ec, ed, pto: bits in trcoer register timer rc output data port p1_1 output data port p1_1 input data timer rc output data port p1_2 output data port p1_2 input data timer rc output data port p5_3 (p3_4) (1) output data port p5_3 (p3_4) (1) input data timer rc output data port p5_4 (p3_5) (1) output data port p5_4 (p3_5) (1) input data note: 1. the pin in parentheses ( ) can be assigned by a program. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 199 of 453 rej09b0278-0210 14.3.4 timer mode (i nput capture function) this function measures the width or period of an external signal. an external signal input to the trcioj (j = a, b, c, or d) pin acts as a trigger for transferring th e contents of the trc regist er (counter) to the trcgrj register (input capture). the input cap ture function, or any other mode or function, can be selected for each individual pin. the trcgra register can also select foco128 signal as input-capture trigger input. table 14.16 lists the specifications of input capture f unction, figure 14.42 shows a block diagram of input capture function, figures 14.43 and 14.44 show the regist ers associated with the in put capture function, table 14.17 lists the functions of trcgrj register when us ing input capture function, and figure 14.45 shows an operating example of input capture function. j = a, b, c, or d table 14.16 specifications of input capture function item specification count source f1, f2, f4, f8, f32, foco40m, or external signal (rising edge) input to trcclk pin count operation increment count period 1/fk 65,536 fk: count source frequency count start condition 1 (count starts) is written to the tstart bit in the trcmr register. count stop condition 0 (count stops) is writte n to the tstart bit in the trcmr register. the trc register retains a value before count stops. interrupt request generation timing ? input capture (valid edge of trci oj input or foco128 signal edge) ? the trc register overflows. trcioa, trciob, trcioc, and trciod pin functions programmable i/o port or input capture input (selectable individually by pin) int0 pin function programmable i/o port or int0 interrupt input read from timer the count value can be read by reading trc register. write to timer the trc register can be written to. select functions ? input capture input pin select one or more of pins trcioa, trciob, trcioc, and trciod ? input capture input valid edge selected rising edge, falling edg e, or both rising and falling edges ? buffer operation (refer to 14.3.3.2 buffer operation .) ? digital filter (refer to 14.3.3.3 digital filter .) ? input-capture trigger selected foco128 can be selected for input-capture trigger input of the trcgra register. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 200 of 453 rej09b0278-0210 figure 14.42 block diagram of input capture function notes: 1. the bfc bit in the trcmr register is set to 1 (trcgrc register functions as the buffer register for the trcgra register) 2. the bfd bit in the trcmr register is set to 1 (trcgrd register functions as the buffer register for the trcgrb register) 3. the trigger input of the trcgra register can select the trcioa pin input or foco128 signal. trcgra register trc register input capture signal (3) trcgrc register trcgrb register trcgrd register trciob (note 1) (note 2) trcioc trciod input capture signal input capture signal input capture signal divided by 128 ioa3 = 0 ioa3 = 1 foco foco128 trcioa ioa3: bit in trcior0 register r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 201 of 453 rej09b0278-0210 figure 14.43 trcior0 register for input capture function timer rc i/o control register 0 symbol address after reset trcior0 0124h 10001000b bit symbol bit name function rw notes: 1. 2. 3. trcgra mode select bit (1) set to 1 (input capture) in the input capture function. rw trcgra input capture input sw itch bit(3) 0 : foco128 signal 1 : trcioa pin input rw rw rw ioa 1 ioa 0 trcgra control bits b1 b0 0 0 : input capture to the trcgra register at the rising edge 0 1 : input capture to the trcgra register at the falling edge 1 0 : input capture to the trcgra register at both edges 1 1 : do not set. b7 b6 b5 b4 1 b3 b2 ioa 3 b1 b0 1 ioa 2 rw ? (b7) iob2 rw trcgrb c ontrol bits b5 b4 0 0 : input capture to the trcgrb register at the rising edge 0 1 : input capture to the trcgrb register at the falling edge 1 0 : input capture to the trcgrb register at both edges 1 1 : do not set. the ioa3 bit is enabled w hen the ioa2 bit is set to 1 (input capture function). when the bfd bit in the trcmr register is set to 1 (buffer register of trcgrb register), set the iod2 bit in the trcior1 register to the same value as the iob2 bit in the trcior0 register. ? iob0 iob1 rw nothing is assigned. if necessary, set to 0. when read, the content is 1. when the bfc bit in the trcmr register is set to 1 (buffer register of trcgra register), set the ioc2 bit in the trcior1 register to the same value as the ioa2 bit in the trcior0 register. trcgrb mode select bit (2) set to 1 (input capture) in the input capture function. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 202 of 453 rej09b0278-0210 figure 14.44 trcior1 register for input capture function j = a, b, c, or d bfc, bfd: bits in trcmr register table 14.17 functions of trcgrj register when using input capture function register setting register function input capture input pin trcgra ? general register. can be used to read the trc register value at input capture. trcioa trcgrb trciob trcgrc bfc = 0 general register. can be used to read the trc register value at input capture. trcioc trcgrd bfd = 0 trciod trcgrc bfc = 1 buffer registers. can be used to hold transferred value from the general register. (refer to 14.3.3.2 buffer operation .) trcioa trcgrd bfd = 1 trciob timer rc i/o control register 1 symbol address after reset trcior1 0125h 10001000b bit symbol bit name function rw notes: 1. 2. trcgrc mode select bit (1) set to 1 (input capture) in the input capture function. rw ? rw rw ioc1 ioc0 trcgrc c ontr ol bits b1 b0 0 0 : input capture to the trcgrc register at the rising edge 0 1 : input capture to the trcgrc register at the falling edge 1 0 : input capture to the trcgrc register at both edges 1 1 : do not set. b7 b6 b5 b4 1 b3 b2 ? (b3) b1 b0 1 ioc2 rw ? (b7) iod2 rw trcgrd c ontr ol bits b5 b4 0 0 : input capture to the trcgrd register at the rising edge 0 1 : input capture to the trcgrd register at the falling edge 1 0 : input capture to the trcgrd register at both edges 1 1 : do not set. when the bfd bit in the trcmr register is set to 1 (buffer register of trcgrb register), set the iod2 bit in the trcior1 register to the same value as the iob2 bit in the trcior0 register. nothing is assigned. if necessary, set to 0. when read, the content is 1. ? iod0 iod1 rw nothing is assigned. if necessary, set to 0. when read, the content is 1. when the bfc bit in the trcmr register is set to 1 (buffer register of trcgra register), set the ioc2 bit in the trcior1 register to the same value as the ioa2 bit in the trcior0 register. trcgrd mode select bit (2) set to 1 (input capture) in the input capture function. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 203 of 453 rej09b0278-0210 figure 14.45 operating example of input capture function trc register count value ffffh 0006h tstart bit in trcmr register 65536 trcgra register 0000h 1 0 trcioa input trcgrc register imfa bit in trcsr register ovf bit in trcsr register set to 0 by a program transfer 0003h 0006h 0006h transfer 1 0 1 0 trcclk input count source the above applies under the following conditions: ? bits tck2 to tck0 in the trccr1 register are set to 101b (the count source is trcclk input). ? bits ioa2 to ioa0 in the trciora register are set to 101b (input capture at the falling edge of the trcioa input). ? the bfc bit in the trcmr register is set to 1 (the trcgrc register functions as the buffer register for the trcgra register). 0003h r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 204 of 453 rej09b0278-0210 14.3.5 timer mode (output compare function) this function detects when the contents of the trc register (counter) and th e trcgrj register (j = a, b, c, or d) match (compare match). when a match occurs a signal is output from the trcioj pin at a given level. the output compare function, or othe r mode or function, can be se lected for each individual pin. table 14.18 lists the specifications of output compar e function, figure 14.46 shows a block diagram of output compare function, figures 14.47 to 14.49 show the registers associated with the output compare function, table 14.19 lists the functions of trcgrj register when using output compare function, and figure 14.50 shows an operating example of output compare function. j = a, b, c, or d table 14.18 specifications of output compare function item specification count source f1, f2, f4, f8, f32, foco40m, or external signal (rising edge) input to trcclk pin count operation increment count period ? the cclr bit in the trccr1 register is set to 0 (f ree running operation): 1/fk 65,536 fk: count source frequency ? the cclr bit in the trccr1 register is set to 1 (trc register set to 0000h at trcgra compare match): 1/fk (n + 1) n: trcgra regist er setting value waveform output timing compare match count start condition 1 (count starts) is written to the tstart bit in the trcmr register. count stop condition 0 (count stops) is writte n to the tstart bit in the trcmr register. the output compare output pin retains output level before count stops, the trc register retains a value before count stops. interrupt request generation timing ? compare match (contents of re gisters trc and trcgrj match) ? the trc register overflows. trcioa, trciob, trcioc, and trciod pin functions programmable i/o port or output comp are output (selectable individually by pin) int0 pin function programmable i/o port, pulse output forced cutoff signal input, or int0 interrupt input read from timer the count value can be read by reading the trc register. write to timer the trc register can be written to. select functions ? output compare output pin selected one or more of pins trcioa, trciob, trcioc, and trciod ? compare match output level select ?l? output, ?h? outpu t, or toggle output ? initial output level select sets output level for period fr om count start to compare match ? timing for clearing the trc register to 0000h overflow or compare match with the trcgra register ? buffer operation (refer to 14.3.3.2 buffer operation .) ? pulse output forced cutoff signal input (refer to 14.3.3.4 forced cutoff of pulse output .) ? can be used as an internal timer by disabling timer rc output r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 205 of 453 rej09b0278-0210 figure 14.46 block diagram of output compare function trcioa output control comparator trcgra trc trcioc trcgrc trciob trcgrb trciod trcgrd output control output control output control compare match signal compare match signal compare match signal compare match signal comparator comparator comparator r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 206 of 453 rej09b0278-0210 figure 14.47 trcior0 register for output compare function timer rc i/o control register 0 symbol address after reset trcior0 0124h 10001000b bit symbol bit name function rw notes: 1. 2. when the bfd bit in the trcmr register is set to 1 (buffer register of trcgrb register), set the iod2 bit in the trcior1 register to the same value as the iob2 bit in the trcior0 register. ? iob0 iob1 rw nothing is assigned. if necessary, set to 0. when read, the content is 1. when the bfc bit in the trcmr register is set to 1 (buffer register of trcgra register), set the ioc2 bit in the trcior1 register to the same value as the ioa2 bit in the trcior0 register. trcgrb mode select bit (2) set to 0 (output compare) in the output compare function. rw ? (b7) iob2 rw trcgrb control bits b5 b4 0 0 : disable pin output by compare match (trciob pin functions as the programmable i/o port) 0 1 : ?l? output by compare match in the trcgrb register 1 0 : ?h? output by compare match in the trcgrb register 1 1 : toggle output by compare match in the trcgrb register b3 b2 ioa 3 b1 b0 10 ioa 2 0 b7 b6 b5 b4 rw rw ioa 1 ioa 0 trcgra c ontr ol bits b1 b0 0 0 : disable pin output by compare match (trcioa pin functions as the programmable i/o port) 0 1 : ?l? output by compare match in the trcgra register 1 0 : ?h? output by compare match in the trcgra register 1 1 : toggle output by compare match in the trcgra register trcgra mode select bit (1) set to 0 (output compare) in the output compare function. rw trcgra input capture input sw itch bit set to 1. rw r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 207 of 453 rej09b0278-0210 figure 14.48 trcior1 register for output compare function timer rc i/o control register 1 symbol address after reset trcior1 0125h 10001000b bit symbol bit name function rw notes: 1. 2. trcgrc mode select bit (1) set to 0 (output compare) in the output compare function. rw ? nothing is assigned. if necessary, set to 0. when read, the content is 1. rw rw ioc1 ioc0 trcgrc c ontr ol bits b1 b0 0 0 : disable pin output by compare match 0 1 : ?l? output by compare match in the trcgrc register 1 0 : ?h? output by compare match in the trcgrc register 1 1 : toggle output by compare match in the trcgrc register b7 b6 b5 b4 0 b3 b2 ? (b3) b1 b0 0 ioc2 ? (b7) iod2 rw trcgrd c ontr ol bits b5 b4 0 0 : disable pin output by compare match 0 1 : ?l? output by compare match in the trcgrd register 1 0 : ?h? output by compare match in the trcgrd register 1 1 : toggle output by compare match in the trcgrd register when the bfd bit in the trcmr register is set to 1 (buffer register of trcgrb register), set the iod2 bit in the trcior1 register to the same value as the iob2 bit in the trcior0 register. ? iod0 iod1 rw nothing is assigned. if necessary, set to 0. when read, the content is 1. when the bfc bit in the trcmr register is set to 1 (buffer register of trcgra register), set the ioc2 bit in the trcior1 register to the same value as the ioa2 bit in the trcior0 register. trcgrd mode select bit (2) set to 0 (output compare) in the output compare function. rw r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 208 of 453 rej09b0278-0210 figure 14.49 trccr1 register for output compare function j = a, b, c, or d bfc, bfd: bits in trcmr register table 14.19 functions of trcgrj register when using output compare function register setting register function output compare output pin trcgra ? general register. write a compare value to one of these registers. trcioa trcgrb trciob trcgrc bfc = 0 general register. write a compare value to one of these registers. trcioc trcgrd bfd = 0 trciod trcgrc bfc = 1 buffer register. write the next compare value to one of these registers. (refer to 14.3.3.2 buff er operation .) trcioa trcgrd bfd = 1 trciob timer rc control register 1 symbol address after reset trccr1 0121h 00h bit symbol bit name function rw notes: 1. 2. rw trc counter clear select bit tck2 rw set to these bits w hen the tstart bit in the trcmr register is set to 0 (count stops). toc rw rw rw rw trciod output level select bit (1, 2) cclr 0 : initial output ?l? 1 : initial output ?h? count source select bits (1) rw tob rw trcioa output level select bit (1, 2) trciob output level select bit (1, 2) toa trcioc output level select bit (1, 2) b6 b5 b4 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : trcclk input rising edge 1 1 0 : foco40m 1 1 1 : do not set. 0 : disable clear (free-running operation) 1 : clear by compare match in the trcgra register tck0 tck1 b7 b6 b5 b4 if the pin function is set for w aveform output (refer to tables 7.13 to 7.16 , tables 7.26 to 7.29 , and tables 7.37 to 7.40 ), the initial output level is output w hen the trccr1 register is set. b3 b2 tod b1 b0 r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 209 of 453 rej09b0278-0210 figure 14.50 operating example of output compare function output level held m n p trc register value count source m+1 m+1 tstart bit in trcmr register 1 0 trcioa output imfa bit in trcsr register 1 0 n+1 trciob output ?h? output at compare match set to 0 by a program imfb bit in trcsr register 1 0 initial output ?l? initial output ?l? trcioc output set to 0 by a program imfc bit in trcsr register 1 0 initial output ?h? ?l? output at compare match p+1 m: trcgra register setting value n: trcgrb register setting value p: trcgrc register setting value the above applies under the following conditions: count restarts count stops output level held set to 0 by a program ? bits bfc and bfd in the trcmr register are set to 0 (trcgrc and trcgrd do not operate as buffers). ? bits ea, eb, and ec in the trcoer register are set to 0 (output from trcioa, trciob, and trcioc enabled). ? the cclr bit in the trccr1 register is set to 1 (set the trc register to 0000h by trcgra compare match). ? in the trccr1 register, bits toa and tob are set to 0 (?l? init ial output until compare match) and the toc bit is set to 1 (? h? initial output until compare match). ? bits ioa2 to ioa0 in the trcior0 register are set to 011b (trcioa output inverted at trcgra compare match). ? bits iob2 to iob0 in the trcior0 register are set to 010b (?h? trciob output at trcgrb compare match). ? bits ioc2 to ioc2 in the trcior1 register are set to 001b (?l? trcioc output at trcgrc compare match). output level held output inverted at compare match r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 210 of 453 rej09b0278-0210 14.3.6 pwm mode this mode outputs pwm waveforms. a maximum of three pwm waveforms with the same period are output. the pwm mode, or the timer mode, can be selected fo r each individual pin. (however, since the trcgra register is used when using any pin for the pwm mode , the trcgra register cannot be used for the timer mode.) table 14.20 lists the specifications of pwm mode, figure 14.51 shows a block diagram of pwm mode, figure 14.52 shows the register associated with the pwm mode, table 14.21 lists the functions of trcgrj register in pwm mode, and figures 14.53 and 14.54 show operating examples of pwm mode. j = b, c, or d h = a, b, c, or d table 14.20 specifications of pwm mode item specification count source f1, f2, f4, f8, f32, foco40m, or external signal (rising edge) input to trcclk pin count operation increment pwm waveform pwm period: 1/fk (m + 1) active level width: 1/fk (m - n) inactive width: 1/fk (n + 1) fk: count source frequency m: trcgra register setting value n: trcgrj register setting value count start condition 1 (count starts) is written to the tstart bit in the trcmr register. count stop condition 0 (count stops) is writte n to the tstart bit in the trcmr register. pwm output pin retains output level before count stops, trc register retains value before count stops. interrupt request generation timing ? compare match (contents of registers trc and trcgrh match) ? the trc register overflows. trcioa pin function programmable i/o port trciob, trcioc, and trciod pin functions programmable i/o port or pwm output (selectable individually by pin) int0 pin function programmable i/o port, pulse output forced cutoff signal input, or int0 interrupt input read from timer the count value can be read by reading the trc register. write to timer the trc register can be written to. select functions ? one to three pins selectable as pwm output pins per channel one or more of pins trciob, trcioc, and trciod ? active level selectable by individual pin ? buffer operation (refer to 14.3.3.2 buffer operation .) ? pulse output forced cutoff signal input (refer to 14.3.3.4 forced cutoff of pulse output .) m+1 n+1 m-n (?l? is active level) r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 211 of 453 rej09b0278-0210 figure 14.51 block diagram of pwm mode trciob output control comparator trcgra trc compare match signal trcgrb trcioc trcgrc trcgrd trciod notes: 1. the bfc bit in the trcmr register is set to 1 (trcgrc regist er functions as the buffer register for the trcgra register) 2. the bfd bit in the trcmr register is set to 1 (trcgrd regist er functions as the buffer register for the trcgrb register) (note 1) (note 2) compare match signal compare match signal compare match signal comparator comparator comparator r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 212 of 453 rej09b0278-0210 figure 14.52 trccr1 register in pwm mode j = a, b, c, or d bfc, bfd: bits in trcmr register note: 1. the output level does not change even when a compare match occurs if the trcgra register value (pwm period) is the same as the trcgrb, trcgrc, or trcgrd register value. table 14.21 functions of trcgrj register in pwm mode register setting register function pwm output pin trcgra ? general register. set the pwm period. ? trcgrb ? general register. set the pwm output change point. trciob trcgrc bfc = 0 general register. set the pwm output change point. trcioc trcgrd bfd = 0 trciod trcgrc bfc = 1 buffer register. set the next pwm period. (refer to 14.3.3.2 buffer operation .) ? trcgrd bfd = 1 buffer register. set the next pwm output change point. (refer to 14.3.3.2 buffer operation .) trciob timer rc control register 1 symbol address after reset trccr1 0121h 00h bit symbol bit name function rw j = b, c or d notes: 1. 2. if the pin function is set for w aveform output (refer to table 7.15 , table 7.16 , tables 7.26 to 7.29 , and tables 7.37 to 7.40 ), the initial output level is output w hen the trccr1 register is set. b3 b2 tod b1 b0 b7 b6 b5 b4 trcioc output level select bit (1, 2) disabled in pwm mode toa rw tob rw trcioa output level select bit (1) trciob output level select bit (1, 2) set to these bits w hen the tstart bit in the trcmr register is set to 0 (count stops). toc rw rw rw rw trciod output level select bit (1, 2) cclr 0 : active level ?h? (initial output ?l? ?h? output by compare match in the trcgrj register ?l? output by compare match in the trcgra register 1 : active level ?l? (initial output ?h? ?l? output by compare match in the trcgrj register ?h? output by compare match in the trcgra register rw rw trc counter clear select bit tck2 count source select bits (1) b6 b5 b4 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : trcclk input rising edge 1 1 0 : foco40m 1 1 1 : do not set. 0 : disable clear (free-running operation) 1 : clear by compare match in the trcgra register tck0 tck1 r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 213 of 453 rej09b0278-0210 figure 14.53 operating example of pwm mode m n p trc register value count source m+1 n+1 trcioc output q m-n p+1 m-p m-q q+1 trciod output m: trcgra register setting value n: trcgrb register setting value p: trcgrc register setting value q: trcgrd register setting value inactive level is ?l? active level is ?h? active level is ?l? ?l? initial output until compare match ?h? initial output until compare match set to 0 by a program set to 0 by a program set to 0 by a program trciob output imfa bit in trcsr register 1 0 imfb bit in trcsr register 1 0 imfc bit in trcsr register 1 0 imfd bit in trcsr register 1 0 the above applies under the following conditions: ? bits bfc and bfd in the trcmr register are set to 0 (registers trcgrc and trcgrd do not operate as buffers). ? bits eb, ec, and ed in the trcoer register are set to 0 (output from trciob, trcioc, and trciod enabled). ? in the trccr1 register, bits tob and toc are set to 0 (active level is ?h?) and the tod bit is set to 1 (active level is ?l?) . set to 0 by a program r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 214 of 453 rej09b0278-0210 figure 14.54 operating example of pwm mode (duty 0% and duty 100%) rewritten by a program m p q trc register value n m: trcgra register setting value set to 0 by a program rewritten by a program 0000h q duty 0% trcgrb register imfa bit in trcsr register 1 0 imfb bit in trcsr register 1 0 tstart bit in trcmr register trciob output p (p>m) n 1 0 m p trc register value n 0000h trcgrb register imfa bit in trcsr register 1 0 imfb bit in trcsr register 1 0 tstart bit in trcmr register trciob output p n 1 0 m the above applies under the following conditions: ? the eb bit in the trcoer register is set to 0 (output from trciob enabled). ? the tob bit in the trccr1 register is set to 1 (active level is ?l?). trciob output does not switch to ?l? because no compare match with the trcgrb register has occurred if compare matches occur simultaneously with registers trcgra and trcgrb, the compare match with the trcgrb register has priority. trciob output switches to ?l?. (in other words, no change). trciob output switches to ?l? at compare match with the trcgrb register. (in other words, no change). set to 0 by a program set to 0 by a program duty 100% set to 0 by a program r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 215 of 453 rej09b0278-0210 14.3.7 pwm2 mode this mode outputs a single pwm waveform. after a given wait duration has elapsed following the trigger, the pin output switches to active level. then, after a given duration, the output switches back to inactive level. furthermore, the counter stops at the same time the out put returns to inactive level, making it possible to use pwm2 mode to output a programmable wait one-shot waveform. since timer rc uses multiple general registers in pwm2 mode, other modes cannot be used in conjunction with it. figure 14.55 shows a block diagram of pwm2 mode, table 14.22 lists the specifications of pwm2 mode, figure 14.56 shows the register asso ciated with pwm2 mode, table 14.23 lists the functions of trcgrj register in pwm2 mode, and figures 14.57 to 14.59 show operating examples of pwm2 mode. figure 14.55 block diagram of pwm2 mode trctrg input control trciob output control comparator trcgra trc trcgrd register compare match signal comparator trcgrb comparator trcgrc note: 1. the bfd bit in the trcmr register is set to 1 (the trcgrd r egister functions as the buffer register for the trcgrb register) . count clear signal trigger signal (note 1) r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 216 of 453 rej09b0278-0210 j = a, b, or c table 14.22 specifications of pwm2 mode item specification count source f1, f2, f4, f8, f32, foco40m, or ex ternal signal (rising edge) input to trcclk pin count operation increment trc register pwm waveform pwm period: 1/fk (m + 1) (no trctrg input) active level width: 1/fk (n - p) wait time from count start or trigger: 1/fk (p + 1) fk: count source frequency m: trcgra register setting value n: trcgrb register setting value p: trcgrc register setting value count start conditions ? bits tceg1 to tceg0 in the trccr2 register are se t to 00b (trctrg trigger disabled) or the csel bit in the trccr2 register is set to 0 (count continues). 1 (count starts) is written to the tstart bit in the trcmr register. ? bits tceg1 to tceg0 in the trccr2 register are set to 01b, 10b, or 11b (trctrg trigger enabled) and the tstart bit in the trcmr register is set to 1 (count starts). a trigger is input to the trctrg pin count stop conditions ? 0 (count stops) is written to t he tstart bit in the trcmr register while the csel bit in the trccr2 register is set to 0 or 1. the trciob pin outputs the initial level in accordance with the value of the tob bit in the trccr1 register. the trc register retains the value before count stops. ? the count stops due to a compare match with trcgra while the csel bit in the trccr2 register is set to 1 the trciob pin outputs the initial level. the trc register retains the value before count stops if the cclr bit in the trccr1 register is set to 0. the trc register is set to 0000h if the cclr bit in the trccr1 register is set to 1. interrupt request generation timing ? compare match (contents of trc and trcgrj registers match) ? the trc register overflows trcioa/trctrg pin function programmable i/o port or trctrg input trciob pin function pwm output trcioc and trciod pin functions programmable i/o port int0 pin function programmable i/o port, pulse output forced cutoff signal input, or int0 interrupt input read from timer the count value can be read by reading the trc register. write to timer the trc register can be written to. select functions ? external trigger and valid edge selected the edge or edges of the signal input to the trctrg pin can be used as the pwm output trigger: rising edge, fa lling edge, or both rising and falling edges ? buffer operation (refer to 14.3.3.2 buffer operation .) ? pulse output forced cutoff signal input (refer to 14.3.3.4 forced cutoff of pulse output .) ? digital filter (refer to 14.3.3.3 digital filter .) m+1 trctrg input trciob output (trctrg: rising edge, active level is ?h?) n-p n+1 p+1 p+1 n+1 n-p r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 217 of 453 rej09b0278-0210 figure 14.56 trccr1 register in pwm2 mode j = a, b, c, or d bfc, bfd: bits in trcmr register note: 1. do not set the trcgrb and trcgrc registers to the same value. table 14.23 functions of trcgrj register in pwm2 mode register setting register function pwm2 output pin trcgra ? general register. set the pwm period. trciob pin trcgrb ? general register. set the pwm output change point. trcgrc bfc = 0 general register. set the pwm output change point (wait time after trigger). trcgrd bfd = 0 (not used in pwm2 mode) ? trcgrd bfd = 1 buffer register. set the next pwm output change point. (refer to 14.3.3.2 buffer operation .) trciob pin timer rc control register 1 symbol address after reset trccr1 0121h 00h bit symbol bit name function rw notes: 1. 2. b3 b2 tod b1 b0 toa b7 b6 b5 b4 0 : active level ?h? (initial output ?l? ?h? output by compare match in the trcgrc register ?l? output by compare match in the trcgrb register 1 : active level ?l? (initial output ?h? ?l? output by compare match in the trcgrc register ?h? output by compare match in the trcgrb register rw rw tob rw trcioa output level select bit (1) trciob output level select bit (1, 2) trcioc output level select bit (1) disabled in the pwm2 mode disabled in the pwm2 mode toc rw rw rw rw trciod output level select bit (1) rw if the pin function is set for w aveform output (refer to table 7.15 and table 7.16 ), the initial output level is output w hen the trccr1 register is set. trc counter clear select bit tck2 set to these bits w hen the tstart bit in the trcmr register is set to 0 (count stops). cclr count source select bits (1) b6 b5 b4 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : trcclk input rising edge 1 1 0 : foco40m 1 1 1 : do not set. 0 : disable clear (free-running operation) 1 : clear by compare match in the trcgra register tck0 tck1 r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 218 of 453 rej09b0278-0210 figure 14.57 operating example of pwm2 mode (trctrg trigger input disabled) set to 0 by a program set to 0 by a program trc register value count source m+1 n+1 0000h ffffh p+1 trciob output m: trcgra register setting value n: trcgrb register setting value p: trcgrc register setting value m n p tstart bit in trcmr register 1 0 count stops because the csel bit is set to 1 ?l? initial output ?h? output at trcgrc register compare match ?l? output at trcgrb register compare match imfa bit in trcsr register 1 0 set to 0 by a program imfb bit in trcsr register csel bit in trccr2 register 1 0 set to 1 by a program 1 0 imfc bit in trcsr register 1 0 transfer trcgrb register trcgrd register nnext data transfer n transfer from buffer register to general register the above applies under the following conditions: ? the tob bit in the trccr1 register is set to 0 (initial level is ?l?, ?h? output at compare match with the trcgrc register, ? l? output at compare match with the trcgrb register). ? bits tceg1 and tceg0 in the trccr2 register are set to 00b (trctrg trigger input disabled). set to 0000h by a program previous value held if the tstrat bit is set to 0 tstart bit is set to 0 trc register cleared at trcgra register compare match p+1 ?h? output at trcgrc register compare match no change no change return to initial output if the tstart bit is set to 0 r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 219 of 453 rej09b0278-0210 figure 14.58 operating example of pwm2 mode (trctrg trigger input enabled) set to 0 by a program trc register value count source m+1 n+1 0000h ffffh p+1 trciob output m: trcgra register setting value n: trcgrb register setting value p: trcgrc register setting value m n p tstart bit in trcmr register 1 0 count stops because the csel bit is set to 1 ?l? initial output ?h? output at trcgrc register compare match imfa bit in trcsr register 1 0 set to 0 by a program imfb bit in trcsr register csel bit in trccr2 register 1 0 1 0 imfc bit in trcsr register 1 0 transfer trcgrb register trcgrd register next data transfer n transfer from buffer register to general register the above applies under the following conditions: ? the tob bit in the trccr1 register is set to 0 (initial level is ?l?, ?h? output at compare match with the trcgrc register, ? l? output at compare match with the trcgrb register). ? bits tceg1 and tceg0 in the trccr2 register are set to 11b (t rigger at both rising and falling edges of trctrg input). set to 0000h by a program previous value held if the tstart bit is set to 0 the tstart bit is set to 0 trc register cleared at trcgra register compare match return to initial value if the tstart bit is set to 0 trc register (counter) cleared at trctrg pin trigger input trctrg input count starts when tstart bit is set to 1 n+1 p+1 p+1 ?l? output at trcgrb register compare match inactive level so trctrg input is enabled active level so trctrg input is disabled set to 0 by a program set to 0 by a program n transfer n n transfer transfer from buffer register to general register n set to 1 by a program changed by a program count starts at trctrg pin trigger input r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 220 of 453 rej09b0278-0210 figure 14.59 operating example of pwm2 mode (duty 0% and duty 100%) ? trcgrc register setting value greater than trcgra register setting value m n trc register value p set to 0 by a program 0000h imfb bit in trcsr register 1 0 imfc bit in trcsr register 1 0 tstart bit in trcmr register trciob output 1 0 the above applies under the following conditions: ? the tob bit in the trccr1 register is set to 0 (initial level is ?l?, ?h? output at compare match with the trcgrc register, ? l? output at compare match with the trcgrb register). ? bits tceg1 and tceg0 in the trccr2 register are set to 00b (trctrg trigger input disabled). p+1 imfa bit in trcsr register 1 0 ?l? initial output no compare match with trcgrb register, so ?h? output continues ?h? output at trcgrc register compare match m+1 ? trcgrb register setting value greater than trcgra register setting value m p trc register value n 0000h imfb bit in trcsr register 1 0 imfc bit in trcsr register 1 0 tstart bit in trcmr register trciob output 1 0 n+1 imfa bit in trcsr register 1 0 ?l? initial output ?l? output at trcgrb register compare match with no change no compare match with trcgrc register, so ?l? output continues m+1 m: trcgra register setting value n: trcgrb register setting value p: trcgrc register setting value r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 221 of 453 rej09b0278-0210 14.3.8 timer rc interrupt timer rc generates a timer rc interrupt request from five sources. the timer rc interrupt uses the single trcic register (bits ir and ilvl0 to ilvl2) and a single vector. table 14.24 lists the registers associated with timer rc interrupt, and figure 14.60 shows a block diagram of timer rc interrupt. figure 14.60 block diagram of timer rc interrupt like other maskable interrupts, the timer rc interrupt is controlled by the combination of the i flag, ir bit, bits ilvl0 to ilvl2, and ipl. however, it differs from other maskable interr upts in the following respects because a single interrupt source (timer rc interrupt) is generated from multiple interrupt request sources. ? the ir bit in the trcic register is set to 1 (interrupt requested) when a bit in the trcsr register is set to 1 and the corresponding bit in the trcier regi ster is also set to 1 (interrupt enabled). ? the ir bit is set to 0 (no interrupt request) when th e bit in the trcsr register or the corresponding bit in the trcier register is set to 0, or both are set to 0. in other words, the interrupt request is not maintained if the ir bit is once set to 1 but the interrupt is not acknowledged. ? if after the ir bit is set to 1 another interrupt source is triggered, the ir bit remains set to 1 and does not change. ? if multiple bits in the trcier register are set to 1, use the trcsr register to determine the source of the interrupt request. ? the bits in the trcsr register ar e not automatically set to 0 when an interrupt is acknowledged. set them to 0 within the interrupt routine. refer to figure 14.30 trcsr register , for the procedure for setting these bits to 0. refer to figure 14.29 trcier register , for details of the trcier register. refer to 12.1.6 interrupt control , for details of the trcic register and 12.1.5.2 relocata ble vector tables , for information on interrupt vectors. table 14.24 registers associat ed with timer rc interrupt timer rc status register timer rc interrupt enab le register timer rc inte rrupt control register trcsr trcier trcic timer rc interrupt request (ir bit in trcic register) imfa bit imiea bit imfb bit imieb bit imfc bit imiec bit imfd bit imied bit ovf bit ovie bit imfa, imfb, imfc, imfd, ovf: bits in trcsr register imiea, imieb, imiec, imied, ovie: bits in trcier register r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 222 of 453 rej09b0278-0210 14.3.9 notes on timer rc 14.3.9.1 trc register ? the following note applies when the cclr bit in the trccr1 register is set to 1 (clear trc register at compare match with trcgra register). when using a program to write a value to the trc regi ster while the tstart bit in the trcmr register is set to 1 (count starts), ensure that the write does not overlap with the timing with which the trc register is set to 0000h. if the timing of the write to the trc register and th e setting of the trc register to 0000h coincide, the write value will not be written to the trc regist er and the trc register will be set to 0000h. ? reading from the trc register immedi ately after writing to it can result in the value previous to the write being read out. to prevent this, execute the jmp.b inst ruction between the read a nd the write instructions. program example mov.w #xxxxh, trc ;write jmp.b l1 ;jmp.b instruction l1: mov.w trc,data ;read 14.3.9.2 trcsr register reading from the trcsr register immediately after writin g to it can result in the value previous to the write being read out. to prevent this, execute the jmp.b inst ruction between the read and the write instructions. program example mov.b #xxh, trcsr ;write jmp.b l1 ;jmp.b instruction l1: mov.b trcsr,data ;read 14.3.9.3 count source switching ? stop the count before switching the count source. switching procedure (1) set the tstart bit in the trcmr register to 0 (count stops). (2) change the settings of bits tck2 to tck0 in the trccr1 register. ? after switching the count source from foco40m to anot her clock, allow a minimum of two cycles of f1 to elapse after changing the clock setting before stopping foco40m. switching procedure (1) set the tstart bit in the trcmr register to 0 (count stops). (2) change the settings of bits tck2 to tck0 in the trccr1 register. (3) wait for a minimum of two cycles of f1. (4) set the fra00 bit in the fra0 register to 0 (high-speed on-chip oscillator off). 14.3.9.4 input capture function ? the pulse width of the input capture signal should be three cycles or more of the timer rc operation clock (refer to table 14.11 timer rc operation clock ). ? the value of the trc register is transferred to th e trcgrj register one or two cycles of the timer rc operation clock after the input capture signal is input to the trcioj (j = a, b, c, or d) pin (when the digital filter function is not used). 14.3.9.5 trcmr regist er in pwm2 mode when the csel bit in the trccr2 register is set to 1 (count stops at compare match with the trcgra register), do not set the trcmr register at co mpare match timing of registers trc and trcgra. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 223 of 453 rej09b0278-0210 14.4 timer re timer re has the 4-bit counter and 8-bit counter. timer re has the following 2 modes: ? real-time clock mode generate 1-second signal from fc4 and count seconds, minutes, hours, and days of the week. ? output compare mode count a count source and detect compare matches. (for j, k version, timer re can be used only in output compare mode.) the count source for timer re is the operating clock that regulates the timing of timer operations. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 224 of 453 rej09b0278-0210 14.4.1 real-time clock mode (for n, d version only) in real-time clock mode, a 1-second si gnal is generated from fc4 using a divide-by-2 frequency divider, 4-bit counter, and 8-bit counter and used to count seconds, mi nutes, hours, and days of the week. figure 14.61 shows a block diagram of real-time clock mode and table 14.25 lists the specificati ons of real-time clock mode. figures 14.62 to 14.66 and 14.68 and 14.69 show the regist ers associated with real -time clock mode. table 14.26 lists the interrupt sources, figure 14.67 shows th e definition of time representation, and figure 14.70 shows the operating example in real-time clock mode. figure 14.61 block diagram of real-time clock mode trewk register trehr register tremin register tresec register h12_h24 bit pm bit mnie hrie wkie 000 dyie seie timer re interrupt int bit bsy bit 8-bit counter 4-bit counter overflow (1s) overflow 1/2 (1/256) (1/16) fc4 h12_h24, pm, int: bits in trecr1 register bsy: bit in registers tresec, tremin, trehr, and trewk timing control data bus overflow overflow r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 225 of 453 rej09b0278-0210 table 14.25 specifications of real-time clock mode item specification count source fc4 count operation increment count start condition 1 (count starts) is wr itten to tstart bit in trecr1 register count stop condition 0 (count stops) is wr itten to tstart bit in trecr1 register interrupt request generation timing select any one of the following: ? update second data ? update minute data ? update hour data ? update day of week data ? when day of week data is set to 000b (sunday) treo pin function programmable i/o ports or output of f2, f4, or f8 read from timer when readi ng tresec, tremin, trehr, or trewk register, the count value can be read. the values read from registers tresec, tremin, and trehr are represented by the bcd code. write to timer when bits tstart and tcstf in the trecr1 register are set to 0 (timer stops), the value can be written to registers tresec, tremin, trehr, and trewk. the values written to registers tresec, tremin, and trehr are represented by the bcd codes. select function ? 12-hour mode/24-hour mode switch function r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 226 of 453 rej09b0278-0210 figure 14.62 tresec register in real-time clock mode figure 14.63 tremin register in real-time clock mode timer re second data register symbol address after reset tresec 0118h 00h bit symbol bit name function setting range rw sc10 rw sc11 bsy ro sc12 rw rw timer re busy flag 2nd digit of second count bits when counting 0 to 5, 60 seconds are counted. 0 to 5 (bcd code) sc00 rw 1st digit of second count bits sc01 rw count 0 to 9 every second. when the digit moves up, 1 is added to the 2nd digit of second. 0 to 9 (bcd code) sc02 rw rw b7 b6 b5 b4 this bit is set to 1 w hile registers tresec, tremin, trehr, and trewk are updated. b3 b2 sc03 b1 b0 timer re minute data register symbol address after reset tremin 0119h 00h bit symbol bit name function setting range rw 2nd digit of minute count bits when counting 0 to 5, 60 minutes are counted. 0 to 5 (bcd code) this bit is set to 1 w hile registers tresec, tremin, trehr, and trewk are updated. b3 b2 mn03 b1 b0 b7 b6 b5 b4 mn00 rw 1st digit of minute count bits mn01 rw count 0 to 9 every minute. when the digit moves up, 1 is added to the 2nd digit of minute. 0 to 9 (bcd code) mn02 rw bsy ro mn12 rw mn10 rw mn11 rw rw timer re busy flag r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 227 of 453 rej09b0278-0210 figure 14.64 trehr register in real-time clock mode figure 14.65 trewk register in real-time clock mode timer re hour data register symbol address after reset trehr 011ah 00h bit symbol bit name function setting range rw hr10 rw 0 to 2 (bcd code) hr11 bsy ro ? (b6) ? rw timer re busy flag this bit is set to 1 w hile registers tresec, tremin, trehr, and trewk are updated. 2nd digit of hour count bits count 0 to 1 w hen the h12_h24 bit is set to 0 (12-hour mode). count 0 to 2 w hen the h12_h24 bit is set to 1 (24-hour mode). hr00 rw 1st digit of hour count bits hr01 rw count 0 to 9 every hour. when the digit moves up, 1 is added to the 2nd digit of hour. 0 to 9 (bcd code) hr02 rw rw b7 b6 b5 b4 nothing is assigned. if necessary, set to 0. when read, the content is 0. b3 b2 hr03 b1 b0 timer re day of week data register symbol address after reset trewk 011bh 00h bit symbol bit name function rw b3 b2 ? (b6-b3) b1 b0 wk0 b7 b6 b5 b4 rw wk1 rw day of w eek count bits b2 b1 b0 0 0 0 : sunday 0 0 1 : monday 0 1 0 : tuesday 0 1 1 : wednesday 1 0 0 : thursday 1 0 1 : friday 1 1 0 : saturday 1 1 1 : do not set wk2 rw ? bsy ro nothing is assigned. if necessary, set to 0. when read, the content is 0. timer re busy flag this bit is set to 1 w hile registers tresec, tremin, trehr, and trewk are updated. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 228 of 453 rej09b0278-0210 figure 14.66 trecr1 register in real-time clock mode figure 14.67 definition of time representation timer re control register 1 symbol address after reset trecr1 011ch 00h bit symbol bit name function rw note: 1. rw rw h12_h24 operating mode select bit 0 : 12-hour mode 1 : 24-hour mode rw interrupt request timing bit set to 1 in real-time clock mode. pm a.m./p.m. bit when the h12_h24 bit is set to 0 (12-hour mode) (1) 0 : a.m. 1 : p.m. when the h12_h24 bit is set to 1 (24-hour mode), its value is undefined. trerst timer re reset bit when setting this bit to 0, after setting it to 1, the f ollow ings w ill occur. ? re g is t e r s tresec, tremin, trehr, trewk, and trecr2 are set to 00h. ? bits tcstf, int, pm, h12_h24, and tstart in the trecr1 register are set to 0. ? the 8-bit counter is set to 00h and the 4-bit counter is set to 0h. treo pin output enable bit 0 : disable clock output 1 : enable clock output this bit is automatically modified w hile timer re counts. toena rw rw tsta rt timer re count start bit 0 : count stops 1 : count starts rw ? tcstf ro nothing is assigned. if necessary, set to 0. when read, the content is 0. timer re count status flag 0 : count stopped 1 : counting b7 b6 b5 b4 b3 b2 int b1 b0 ? (b0) noon h12_h24 bit = 1 (24-hour mode) contents of pm bit 0 (a.m.) 1 (p.m.) contents of trehr register h12_h24 bit = 0 (12-hour mode) contents in trewk register 000 (sunday) 0 1 2 3 4 5 7 9 11 13 15 17 6 8 10 12 14 16 0 1 2 3 4 5 7 9 11 1 3 5 6 8 10 0 2 4 h12_h24 bit = 1 (24-hour mode) contents of pm bit 1 (p.m.) contents of trehr register h12_h24 bit = 0 (12-hour mode) contents in trewk register 000 (sunday) 18 19 20 21 22 23 1 3 0 2 ??? 6 7 8 9 10 11 1 3 0 2 date changes ??? ??? 0 (a.m.) 001 (monday) ??? pm bit and h12_h24 bits: bits in trecr1 register the above applies to the case when count starts from a.m. 0 on sunday. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 229 of 453 rej09b0278-0210 figure 14.68 trecr2 register in real-time clock mode table 14.26 interrupt sources factor interrupt source interrupt enable bit periodic interrupt triggered every week value in trewk register is set to 000b (sunday) (1-week period) wkie periodic interrupt triggered every day trewk register is updated (1-day period) dyie periodic interrupt triggered every hour trehr register is updated (1-hour period) hrie periodic interrupt triggered every minute tremin register is updated (1-minute period) mnie periodic interrupt triggered every second tresec register is updat ed (1-second period) seie timer re control register 2 symbol address after reset trecr2 011dh 00h bit symbol bit name function rw note: 1. b3 b2 dy ie b1 b0 seie b7 b6 b5 b4 0 rw mnie rw periodic interrupt triggered every minute enable bit (1) 0 : disable periodic interrupt triggered every minute 1 : enable periodic interrupt triggered every minute periodic interrupt triggered every second enable bit (1) 0 : disable periodic interrupt triggered every second 1 : enable periodic interrupt triggered every second periodic interrupt triggered every hour enable bit (1) 0 : disable periodic interrupt triggered every hour 1 : enable periodic interrupt triggered every hour do not set multiple enable bits to 1 (enable interrupt). hrie rw rw periodic interrupt triggered every day enable bit (1) 0 : disable periodic interrupt triggered every day 1 : enable periodic interrupt triggered every day comie compare match interrupt enable bit rw rw ? (b7-b6) ? nothing is assigned. if necessary, set to 0. when read, the content is 0. set to 0 in real-time clock mode. wkie periodic interrupt triggered every w eek enable bit (1) 0 : disable periodic interrupt triggered every w eek 1 : enable periodic interrupt triggered every w eek r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 230 of 453 rej09b0278-0210 figure 14.69 trecsr register in real-time clock mode timer re count source select register symbol address after reset trecsr 011eh 00001000b bit symbol bit name function rw note: 1. nothing is assigned. if necessary, set to 0. when read, the content is 0. ? rw rcs6 rw rcs5 ? (b4) nothing is assigned. if necessary, set to 0. when read, the content is 0. clock output select bits (1) b6 b5 0 0 : f 2 0 1 : f 4 1 0 : f 8 1 1 : do not set. 4-bit counter select bit set to 0 in real-time clock mode. write to bits rcs5 to rcs6 w hen the toena bit in the trecr1 register is set to 0 (disable clock output). rcs2 rw rw ? (b7) ? real-time clock mode select bit set to 1 in real-time clock mode. rw rcs1 rw count source select bits set to 00b in real-time clock mode. b7 b6 b5 b4 b3 b2 rcs3 b1 b0 00 10 rcs0 r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 231 of 453 rej09b0278-0210 figure 14.70 operating example in real-time clock mode ir bit in treic register 03 ir bit in treic register bits wk2 to wk0 in trewk register (when seie bit in trecr2 register is set to 1 (enable periodic interrupt triggered every second)) (when mnie bit in trecr2 register is set to 1 (enable periodic interrupt triggered every minute)) 1 0 pm bit in trecr1 register bits hr11 to hr00 in trehr register (not changed) set to 0 by acknowledgement of interrupt request or a program 04 bits mn12 to mn00 in tremin register 58 59 00 bsy bit approx. 62.5 ms bits sc12 to sc00 in tresec register 1s bsy: bit in registers tresec, tremin, trehr, and trewk approx. 62.5 ms 1 0 1 0 (not changed) (not changed) r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 232 of 453 rej09b0278-0210 14.4.2 output compare mode in output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and compare value match is detected with the 8-bit co unter. figure 14.71 shows a block diagram of output compare mode and table 14.27 lists the specifications of output compare mode. figures 14.72 to 14.76 show the registers associated with output compare mode, and figure 14.77 shows the operating example in output compare mode. figure 14.71 block diagram of output compare mode toena treo pin fc4 (1) f32 f4 f8 4-bit counter 8-bit counter tresec tremin 1/2 rcs2 = 1 rcs2 = 0 comie timer re interrupt f2 match signal = 00b = 01b = 10b = 11b rcs1 to rcs0 rcs6 to rcs5 = 00b = 01b = 10b = 11b trerst, toena: bits in trecr1 register comie: bit in trecr2 register rcs0 to rcs2, rcs5 to rcs6: bits in trecsr register tq r reset trerst bit data bus comparison circuit note: 1. for j, k version, fc4 cannot be selected. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 233 of 453 rej09b0278-0210 note: 1. for j, k version, fc 4 cannot be selected. table 14.27 specifications of output compare mode item specification count sources f4, f8, f32, fc4 (1) count operations ? increment ? when the 8-bit counter content matches with the tremin register content, the value returns to 00h and count continues. the count value is held while count stops. count period ? when rcs2 = 0 (4-bit counter is not used) 1/fi x 2 x (n+1) ? when rcs2 = 1 (4-bit counter is used) 1/fi x 32 x (n+1) fi: frequency of count source n: setting value of tremin register count start condition 1 (count starts) is writte n to the tstart bit in the trecr1 register count stop condition 0 (count stops) is writt en to the tstart bit in the trecr1 register interrupt request generation timing when the 8-bit counter content matc hes with the tremin register content treo pin function select any one of the following: ? programmable i/o ports ? output f2, f4, or f8 ? compare output read from timer when reading the tresec register, the 8-bit counter value can be read. when reading the tremin register, the compare value can be read. write to timer writing to the tresec register is disabled. when bits tstart and tcstf in the trecr1 register are set to 0 (timer stops), writing to the tremin register is enabled. select functions ? select use of 4-bit counter ? compare output function every time the 8-bit counter value ma tches the tremin register value, treo output polarity is reversed. the treo pin outputs ?l? after reset is deasserted and the timer re is reset by the trerst bit in the trecr1 register. output level is held by setting the tstart bit to 0 (count stops). r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 234 of 453 rej09b0278-0210 figure 14.72 tresec register in output compare mode figure 14.73 tremin register in output compare mode timer re counter data register symbol address after reset tresec 0118h 00h rw b3 b2 b1 b0 ro function 8-bit counter data can be read. although timer re stops counting, the count value is held. the tresec register is set to 00h at the compare match. b7 b6 b5 b4 timer re compare data register symbol address after reset tremin 0119h 00h rw b3 b2 b1 b0 rw function 8-bit compare data is stored. b7 b6 b5 b4 r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 235 of 453 rej09b0278-0210 figure 14.74 trecr1 register in output compare mode figure 14.75 trecr2 register in output compare mode timer re control register 1 symbol address after reset trecr1 011ch 00h bit symbol bit name function rw h12_h24 operating mode select bit rw set to 0 in output compare mode. timer re reset bit when setting this bit to 0, after setting it to 1, the f ollow ing w ill occur. ? re g is t e r s tresec, tremin, trehr, trewk, and trecr2 are set to 00h. ? bits tcstf, int, pm, h12_h24, and tstart in the trecr1 register are set to 0. ? the 8-bit counter is set to 00h and the 4-bit counter is set to 0h. rw rw treo pin output enable bit 0 : disable clock output 1 : enable clock output toena rw rw tsta rt timer re count start bit 0 : count stops 1 : count starts rw interrupt request timing bit set to 0 in output compare mode. pm a.m./p.m. bit trerst ? tcstf ro nothing is assigned. if necessary, set to 0. when read, the content is 0. timer re count status flag 0 : count stopped 1 : counting 00 b7 b6 b5 b4 b3 b2 int b1 b0 0 ? (b0) timer re control register 2 symbol address after reset trecr2 011dh 00h bit symbol bit name function rw rw rw wkie periodic interrupt triggered every w eek enable bit set to 0 in output compare mode. periodic interrupt triggered every hour enable bit hrie rw ? nothing is assigned. if necessary, set to 0. when read, the content is 0. 0 : disable compare match interrupt 1 : enable compare match interrupt ? (b7-b6) rw mnie rw periodic interrupt triggered every minute enable bit periodic interrupt triggered every second enable bit periodic interrupt triggered every day enable bit comie compare match interrupt enable bit rw 0 b7 b6 b5 b4 b3 b2 dy ie b1 b0 00 00 seie r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 236 of 453 rej09b0278-0210 figure 14.76 trecsr register in output compare mode timer re count source select register symbol address after reset trecsr 011eh 00001000b bit symbol bit name function rw notes: 1. 2. for j, k version, fc4 cannot be selected. nothing is assigned. if necessary, set to 0. when read, the content is 0. ? rw rcs6 rw rcs5 ? (b4) nothing is assigned. if necessary, set to 0. when read, the content is 0. clock output select bits (1) b6 b5 0 0 : f2 0 1 : f4 1 0 : f8 1 1 : compare output 4-bit counter select bit 0 : not used 1 : used write to bits rcs5 to rcs6 w hen the toena bit in the trecr1 register is set to 0 (disable clock output). rcs2 rw rw ? (b7) ? real-time clock mode select bit set to 0 in output compare mode. rw rcs1 rw count source select bits b1 b0 0 0 : f4 0 1 : f8 1 0 : f32 1 1 : fc4 (2) b7 b6 b5 b4 b3 b2 rcs3 b1 b0 0 rcs0 r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 237 of 453 rej09b0278-0210 figure 14.77 operating example in output compare mode 00h 8-bit counter content (hexadecimal number) count starts time tstart bit in trecr1 register 1 0 ir bit in treic register 1 0 the above applies under the following conditions. toena bit in trecr1 register = 1 (enable clock output) comie bit in trecr2 register = 1 (enable compare match interrupt) rcs6 to rcs5 bits in trecsr register = 11b (compare output) set to 1 by a program tremin register setting value matched treo output 1 0 tcstf bit in trecr1 register 1 0 output polarity is inverted when the compare matches matched matched 2 cycles of maximum count source set to 0 by acknowledgement of interrupt request or a program r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 238 of 453 rej09b0278-0210 14.4.3 notes on timer re 14.4.3.1 starting and stopping count timer re has the tstart bit for instructing the count to start or stop, and the tcstf bit, which indicates count start or stop. bits tstart an d tcstf are in the trecr1 register. timer re starts counting and the tcstf bit is set to 1 (count starts) when the tstart bit is set to 1 (count starts). it takes up to 2 cycles of the count source until the tcstf bit is set to 1 after setting the tstart bit to 1. during this time, do not access re gisters associated with timer re (1) other than the tcstf bit. also, timer re stops counting when setting the tstart bit to 0 (count stops) and the tcstf bit is set to 0 (count stops). it takes the time for up to 2 cycles of the count source until the tcstf bit is set to 0 after setting the tstart bit to 0. during this ti me, do not access registers associated with timer re other than the tcstf bit. note: 1. registers associated with timer re: tresec, tremin, trehr, trewk, trecr1, trecr2, and trecsr. 14.4.3.2 register setting write to the following registers or bits when timer re is stopped. ? registers tresec, tremin, trehr, trewk, and trecr2 ? bits h12_h24, pm, and int in trecr1 register ? bits rcs0 to rcs3 in trecsr register timer re is stopped when bits tstart and tcstf in the trecr1 register are set to 0 (timer re stopped). also, set all above-mentioned registers and bits (immedia tely before timer re count starts) before setting the trecr2 register. figure 14.78 shows a setting example in real-time clock mode. r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 239 of 453 rej09b0278-0210 figure 14.78 setting example in real-time clock mode stop timer re operation tcstf in trecr1 = 0? tstart in trecr1 = 0 trerst in trecr1 = 1 trerst in trecr1 = 0 setting of registers trecsr, tresec, tremin, trehr, trewk, and bits h12_h24, pm, and int in trecr1 register setting of trecr2 tstart in trecr1 = 1 tcstf in trecr1 = 1? treic 00h (disable timer re interrupt) setting of treic (ir bit 0, select interrupt priority level) timer re register and control circuit reset select clock output select clock source seconds, minutes, hours, days of week, operating mode set a.m./p.m., interrupt timing select interrupt source start timer re operation r8c/26 group, r8c/27 group 14. timers rev.2.10 sep 26, 2008 page 240 of 453 rej09b0278-0210 14.4.3.3 time reading proce dure of real-time clock mode in real-time clock mode, read registers tresec, tr emin, trehr, and trewk wh en time data is updated and read the pm bit in the trecr1 register when th e bsy bit is set to 0 (not while data is updated). also, when reading several registers, an incorrect time will be r ead if data is updated before another register is read after reading any register. in order to prevent this, use the reading procedure shown below. ? using an interrupt read necessary contents of regi sters tresec, tremin, trehr, a nd trewk and the pm bit in the trecr1 register in the timer re interrupt routine. ? monitoring with a program 1 monitor the ir bit in the treic regi ster with a program and read necessa ry contents of registers tresec, tremin, trehr, and trewk and the pm bit in the trecr1 register after the ir bit in the treic register is set to 1 (timer re interrupt request generated). ? monitoring with a program 2 (1) monitor the bsy bit. (2) monitor until the bsy bit is set to 0 after the bsy bit is set to 1 (approximately 62.5 ms while the bsy bit is set to 1). (3) read necessary contents of re gisters tresec, tremin, trehr, and trewk and the pm bit in the trecr1 register after the bsy bit is set to 0. ? using read results if they are the same value twice (1) read necessary contents of re gisters tresec, tremin, trehr, and trewk and the pm bit in the trecr1 register. (2) read the same register as (1) and compare the contents. (3) recognize as the correct value if th e contents match. if the contents do not match, repeat until the read contents match with th e previous contents. also, when reading several registers, r ead them as continuously as possible. r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 241 of 453 rej09b0278-0210 15. serial interface the serial interface consists of two channels (uart0 and uart1). each uarti (i = 0 or 1) has an exclusive timer to generate the transfer clock and operates independently. figure 15.1 shows a uarti (i = 0 or 1) block diag ram. figure 15.2 shows a uarti transmit/receive unit. uarti has two modes: clock synchronous serial i/o mode and clock asynchronous serial i/o mode (uart mode). figures 15.3 to 15.7 show the registers associated with uarti. figure 15.1 uarti (i = 0 or 1) block diagram = 01b f8 f1 = 10b clk1 to clk0 = 00b rxd0 f32 1/16 1/16 1/2 1/(n0+1) uart reception uart transmission clock synchronous type (when internal clock is selected) clock synchronous type reception control circuit transmission control circuit ckdir = 0 ckdir = 1 receive clock transmit clock transmit/ receive unit u0brg register ckdir = 0 internal external ckdir = 1 (uart0) txd0 clk polarity switch circuit clk0 clock synchronous type clock synchronous type (when external clock is selected) clock synchronous type (when internal clock is selected) rxd1 transmit/ receive unit (uart1) txd1 txd1en = 01b f8 f1 = 10b clk1 to clk0 = 00b f32 1/16 1/16 1/2 1/(n0+1) uart reception uart transmission clock synchronous type (when internal clock is selected) clock synchronous type reception control circuit transmission control circuit ckdir=0 ckdir=1 receive clock transmit clock u1brg register ckdir = 0 internal external ckdir = 1 clk polarity switch circuit clk1 clock synchronous type clock synchronous type (when external clock is selected) clock synchronous type (when internal clock is selected) u1pinsel u1pinsel r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 242 of 453 rej09b0278-0210 figure 15.2 uarti transmit/receive unit rxdi 1sp 2sp sp sp par prye = 0 par disabled par enabled prye = 1 uart uart (9 bits) d7 d6 d5 d4 d3 d2 d1 d0 uarti receive register uirb register 0000000d8 msb/lsb conversion circuit data bus high-order bits data bus low-order bits d7 d6 d5 d4 d3 d2 d1 d0 uitb register d8 txdi 1sp 2sp sp sp par uarti transmit register 0 i = 0 or 1 sp: stop bit par: parity bit uart (7 bits) uart (8 bits) clock synchronous type clock synchronous type uart (7 bits) clock synchronous type uart (7 bits) clock synchronous type uart (8 bits) uart (9 bits) uart (7 bits) uart (8 bits) clock synchronous type uart (9 bits) uart prye = 1 par enabled par disabled prye = 0 clock synchronous type msb/lsb conversion circuit uart (8 bits) uart (9 bits) r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 243 of 453 rej09b0278-0210 figure 15.3 registers u0tb to u1tb and u0rb to u1rb uarti transmit buffer register (i = 0 or 1) (1, 2) symbol address after reset u0tb 00a3h-00a2h undefined u1tb 00abh-00aah undefined rw notes: 1. 2. ( b15) b7 ( b8) b0 b0 b7 when the transfer data length is 9 bits, w rite data to high byte first, then low byte. use the mov instruction to w rite to this register. function wo ? transmit data nothing is assigned. if necessary, set to 0. when read, the content is undefined. ? (b8-b0) ? (b15-b9) uarti receive buffer register (i = 0 or 1) (1) symbol address after reset u0rb 00a7h-00a6h undefined u1rb 00afh-00aeh undefined rw notes: 1. 2. ? ? (b7-b0) ? func tion receive data (d7 to d0) ro receive data (d8) ro ? (b8) ? b0 b7 ( b15) b7 ( b8) b0 bit symbol bit name oer overrun error flag (2) 0 : no overrun error 1 : overrun error ro 0 : no parity error 1 : parity error ro fer framing error flag (2) 0 : no framing error 1 : framing error ro nothing is assigned. if necessary, set to 0. when read, the content is undefined. ? (b11-b9) read out the uirb register in 16-bit units. bits sum, per, fer, and oer are set to 0 (no error) w hen bits smd2 to smd0 in the uimr register are set to 000b (serial interface disabled) or the re bit in the uic1 register is set to 0 (receive disabled). the sum bit is set to 0 (no error) w hen bits per, fer, and oer are set to 0 (no error). bits per and fer are set to 0 even w hen the higher byte of the uirb register is read out. also, bits per and fer are set to 0 w hen reading the high-order byte of the uirb register. ro sum error sum flag (2) 0 : no error 1 : error per parity error flag (2) r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 244 of 453 rej09b0278-0210 figure 15.4 registers u0brg to u1brg and u0mr to u1mr uarti bit rate register (i = 0 or 1) (1, 2, 3) symbol address after reset u0brg 00a1h undefined u1brg 00a9h undefined setting range rw notes: 1. 2. 3. b7 00h to ffh func tion assuming the set value is n, uibrg divides the count source by n+1 after setting the clk0 to clk1 bits of the uic0 register, w rite to the uibrg register. b0 use the mov instruction to w rite to this register. wo write to this register w hile the serial i/o is neither transmitting nor receiving. uarti transmit/receive mode register (i = 0 or 1) symbol address after reset u0mr 00a0h 00h u1mr 00a8h 00h bit symbol bit name function rw note: 1. rw b3 b2 b1 b0 smd0 rw 0 b7 b6 b5 b4 serial i/o mode select bits b2 b1 b0 0 0 0 : serial interface disabled 0 0 1 : clock synchronous serial i/o mode 1 0 0 : uart mode transfer data 7 bits long 1 0 1 : uart mode transfer data 8 bits long 1 1 0 : uart mode transfer data 9 bits long other than above : do not set smd1 when the clk0 pin is used, set the pd1_6 bit in the pd1 register to 0 (input). when the clk1 pin is used, set the pd0_5 bit in the pd0 register to 0 (input). smd2 rw rw stps rw 0 : 1 stop bit 1 : 2 stop bits ckdir pry rw rw odd/even parity select bit enable w hen prye = 1 0 : odd parity 1 : even parity pry e parity enable bit 0 : parity disabled 1 : parity enabled rw set to 0. internal/external clock select bit 0 : internal clock 1 : external clock (1) stop bit length select bit ? (b7) res er v ed bit r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 245 of 453 rej09b0278-0210 figure 15.5 registers u0c0 to u1c0 uarti transmit/receive control register 0 (i = 0 or 1) symbol address after reset u0c0 00a4h 00001000b u1c0 00ach 00001000b bit symbol bit name function rw note: 1. b3 b2 txept b1 b0 0 clk0 ? res er v ed bit b7 b6 b5 b4 ? (b2) ckpol clk1 rw brg count source select bits (1) b1 b0 0 0 : selects f1 0 1 : selects f8 1 0 : selects f32 1 1 : do not set. rw rw ro ? (b4) clk polarity select bit 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at f alling edge set to 0. transmit register empty flag 0 : data in transmit register (during transmit) 1 : no data in transmit register (transmit completed) nothing is assigned. if necessary, set to 0. when read, the content is 0. rw rw if the brg count source is sw itched, set the uibrg register again. rw data output select bit 0 : txdi pin is for cmos output 1 : txdi pin is for n-channel open drain output uform transfer format select bit 0 : lsb first 1 : msb f irst nch r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 246 of 453 rej09b0278-0210 figure 15.6 registers u0c1 to u1c1 uarti transmit/receive control register 1 (i = 0 or 1) symbol address after reset u0c1 00a5h 00000010b u1c1 00adh 00000010b bit symbol bit name function rw notes: 1. 2. b0 nothing is assigned. if necessary, set to 0. when read, the content is 0. transmit enable bit (1) 0 : disables transmission 1 : enables transmission transmit buffer empty flag 0 : disables reception 1 : enables reception uiirs b3 b2 b1 ? receive enable bit b7 b6 b5 b4 rw ti ro 0 : data in uitb register 1 : no data in uitb register te ro rw ri receive complete flag (1) 0 : no data in uirb register 1 : data in uirb r egis ter re set the uirrm bit to 0 (disables continuous receive mode) in uart mode. ua rti transmit interrupt cause select bit 0 : transmission buffer empty (ti=1) 1 : transmission completed (txept=1) rw uirrm uarti continuous receive mode enable bit (2) 0 : disables continuous receive mode 1 : enables continuous receive mode rw the ri bit is set to 0 w hen the higher byte of the uirb register is read out. ? (b7-b6) r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 247 of 453 rej09b0278-0210 figure 15.7 registers pinsr1 and pmr pin select register 1 symbol address after reset pinsr1 00f5h 00h bit symbol bit name function rw note: 1. the uart1 pins can be selected by using bits u1pinsel, txd1sel and txd1en in the pmr register. rw rw rw ? (b2) ? (b7-b3) set to 1. when read, the content is 0. set to 0. when read, the content is 0. reserved bits reserved bit rw ua rt1sel1 ua rt1sel0 0000 b7 b6 b5 b4 b3 b2 1 b1 0 b0 b1 b0 0 0 : p3_7(txd1/rxd1) 0 1 : p3_7(txd1), p4_5(rxd1) 1 0 : p3_6(txd1/rxd1) 1 1 : do not set. txd1/rxd1 pin select bit (1) port mode registe r symbol address after reset pmr 00f8h 00h bit symbol bit name function rw int1 _ ____ pin select bit note: 1. the uart1 pins can be selected by using bits u1pinsel, txd1sel and txd1en, and bits uart1sel1 and uart1sel0 in the pinsr1 register. iicsel ssu / i 2 c bus pin sw itch bit 0 : selects ssu function 1 : selects i 2 c bus function rw txd1en txd1/rxd1 select bit (1) 0 : rxd1 1 : txd1 rw txd1sel port/txd1 pin sw itch bit (1) 0 : programmable i/o port 1 : txd1 rw u1 pinsel txd1 pin sw itch bit (1) 0 : p0_0 1 : p3_6, p3_7 rw ssisel ssi pin select bit 0 : p3_3 1 : p1_6 rw int1sel 0 : p1_5, p1_7 1 : p3_6 rw ? (b2-b1) ? nothing is assigned. if necessary, set to 0. when read, the content is 0. b0 b3 b2 b1 b7 b6 b5 b4 pinsr1 regis ter ua rt1sel1, ua rt1sel0 bit u1pinsel bit txd1sel bit txd1en bit p3_7(txd1) 1 p3_7(rxd1) 0 p0_0(txd1) 0 1 p3_7(txd1) 1 p4_5(rxd1) p3_6(txd1) 1 p3_6(rxd1) 0 p0_0(txd1) 0 1 : 0 or 1 10b pmr register pin function 00b 01b 1 r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 248 of 453 rej09b0278-0210 15.1 clock synchronous serial i/o mode in the clock synchronous serial i/o mode, data is transmitted and received using a transfer clock. table 15.1 lists the specifications of clock synchronous serial i/o mode. table 15.2 lists the registers used and settings in clock synchronous serial i/o mode. i = 0 or 1 notes: 1. if an external clock is selected, ensure that th e external clock is ?h? when the ckpol bit in the u0c0 register is set to 0 (transmit data output at falling edge an d receive data input at rising edge of transfer clock), and that the external clock is ?l? when the ckpol bit is set to 1 (transmit data output at rising edge and receive data inpu t at falling edge of transfer clock). 2. if an overrun error occu rs, the receive data (b0 to b8) of the uirb register will be undefined. the ir bit in the siric register remains unchanged. table 15.1 specifications of clock synchronous serial i/o mode item specification transfer data format ? transfer data length: 8 bits transfer clocks ? ckdir bit in uimr register is set to 0 (internal clock): fi/(2(n+1)) fi = f1, f8, f32 n = value set in u0brg register: 00h to ffh ? the ckdir bit is set to 1 (external clock): input from clki pin transmit start conditions ? before transmit starts, the following requirements must be met (1) - the te bit in the uic1 register is set to 1 (tr ansmission enabled) - the ti bit in the uic1 register is set to 0 (d ata in the uitb register) receive start conditions ? before receive starts, the following requirements must be met (1) - the re bit in the uic1 register is set to 1 (reception enabled) - the te bit in the uic1 register is set to 1 (tr ansmission enabled) - the ti bit in the uic1 register is set to 0 (d ata in the uitb register) interrupt request generation timing ? when transmitting, one of the following conditions can be selected - the uiirs bit is set to 0 (transmit buffer empty): when transferring data from the uitb register to uarti transmit register (when transmission starts). - the uiirs bit is set to 1 (transmission completes): when completing data transmission from uarti transmit register. ? when receiving when data transfer from the uarti re ceive register to the uirb register (when reception completes). error detection ? overrun error (2) this error occurs if the se rial interface starts receiving the next data item before reading the uirb regi ster and receives the 7t h bit of the next data. select functions ? clk polarity selection transfer data input/output can be selected to occur synchronously with the rising or the falling edg e of the transfer clock. ? lsb first, msb first selection whether transmitting or receiving data begi ns with bit 0 or begins with bit 7 can be selected. ? continuous receive mode selection receive is enabled immediately by reading the uirb register. r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 249 of 453 rej09b0278-0210 i = 0 or 1 note: 1. set bits which are not in this table to 0 when writing to the above registers in clock synchronous serial i/o mode. table 15.3 lists the i/o pin functions in clock synchronous serial i/o mode. the txdi (i = 0 or 1) pin outputs ?h? level between the operating mode se lection of uarti and transf er start. (if the nch bi t is set to 1 (n-channel open-drain output), this pin is in a high-impedance state.) table 15.2 registers used and settings in clock synchronous serial i/o mode (1) register bit function uitb 0 to 7 set data transmission uirb 0 to 7 data reception can be read oer overrun error flag uibrg 0 to 7 set bit rate uimr smd2 to smd0 set to 001b ckdir select the internal clock or external clock uic0 clk1 to clk0 select the count source in the uibrg register txept transmit register empty flag nch select txdi pin output mode ckpol select the transfer clock polarity uform select the lsb first or msb first uic1 te set this bit to 1 to enable transmissi on/reception ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag uiirs select the uarti tr ansmit interrupt source uirrm set this bit to 1 to use continuous receive mode table 15.3 i/o pin functions in clock synchronous serial i/o mode pin name function selection method txd0 (p1_4) output serial data (outputs dummy data when performing reception only) rxd0 (p1_5) input serial data pd1_5 bit in pd1 register = 0 (p1_5 can be used as an input port when performing transmission only) clk0 (p1_6) output transfer clock ckdir bit in u0mr register = 0 input transfer clock ckdir bi t in u0mr register = 1 pd1_6 bit in pd1 register = 0 txd1 (either p0_0, p3_6, or p3_7) output serial data set registers pinsr1 and pmr (refer to figure 15.7 registers pinsr1 and pmr ) (outputs dummy data when performing reception only) rxd1 (either p3_6, p3_7, or p4_5) input serial data set registers pinsr1 and pmr (refer to figure 15.7 registers pinsr1 and pmr ) corresponding bit in each port direction register = 0 (can be used as an input port when performing transmission only) clk1 (p0_5) output transfer clock ckdir bit in u1mr register = 0 input transfer clock pd0_5 bit in pd0 register = 0 ckdir bit in u1mr register = 1 r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 250 of 453 rej09b0278-0210 figure 15.8 transmit and receive timing ex ample in clock synchronous serial i/o mode transfer clock d0 te bit in uic1 register txdi ? example of transmit timing (when internal clock is selected) set data in uitb register transfer from uitb register to uarti transmit register tc clki tclk stop pulsing because the te bit is set to 0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 tc = tclk = 2(n+1)/fi fi: frequency of uibrg count source (f1, f8, f32) n: setting value to uibrg register the above applies under the following settings: ? ckdir bit in uimr register = 0 (internal clock) ? ckpol bit in uic0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the tra nsfer clock) ? uiirs bit in uic1 register = 0 (an interrupt request is generated when the transmit buffer is empty) d0 set to 0 when interrupt request is acknowledged, or set by a program write dummy data to uitb register transfer from uitb register to uarti transmit register 1/fext d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 receive data is taken in read out from uirb register transfer from uarti receive register to uirb register ti bit in uic1 register 1 0 1 0 1 0 1 0 txept bit in uic0 register ir bit in sitic register set to 0 when interrupt request is acknowledged, or set by a program ? example of receive timing (when external clock is selected) re bit in uic1 register te bit in uic1 register ti bit in uic1 register 1 0 1 0 1 0 ri bit in uic1 register ir bit in siric register 1 0 1 0 clki rxdi the above applies under the following settings: ? ckdir bit in uimr register = 1 (external clock) ? ckpol bit in uic0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the tra nsfer clock) the following conditions are met when ?h? is applied to the clki pin before receiving data: ? te bit in uic1 register = 1 (enables transmit) ? re bit in uic1 register = 1 (enables receive) ? write dummy data to the uitb register fext: frequency of external clock i = 0 or 1 r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 251 of 453 rej09b0278-0210 15.1.1 polarity select function figure 15.9 shows the transfer clock pola rity. use the ckpol bit in the uic0 (i = 0 or 1) register to select the transfer clock polarity. figure 15.9 transfer clock polarity 15.1.2 lsb first/msb first select function figure 15.10 shows the transfer format. use the uform bi t in the uic0 (i = 0 or 1) register to select the transfer format. figure 15.10 transfer format clki (1) d0 txdi ? when the ckpol bit in the uic0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) d1 d2 notes: 1. when not transferring, the clki pin level is ?h?. 2. when not transferring, the clki pin level is ?l?. d3 d4 d5 d6 d7 d0 rxdi d1 d2 d3 d4 d5 d6 d7 clki (2) d0 txdi d1 d2 d3 d4 d5 d6 d7 d0 rxdi d1 d2 d3 d4 d5 d6 d7 ? when the ckpol bit in the uic0 register = 1 (output transmit data at the rising edge and input receive data at the falling edge of the transfer clock) i = 0 or 1 clki d0 txdi ? when uform bit in uic0 register = 0 (lsb first) (1) d1 d2 d3 d4 d5 d6 d7 d0 rxdi d1 d2 d3 d4 d5 d6 d7 clki d7 txdi d6 d5 d4 d3 d2 d1 d0 rxdi ? when uform bit in uic0 register = 1 (msb first) (1) note: 1. the above applies when the ckpol bit in the uic0 register is set to 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock). d7 d6 d5 d4 d3 d2 d1 d0 i = 0 or 1 r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 252 of 453 rej09b0278-0210 15.1.3 continuous receive mode continuous receive mode is selected by setting the uirrm (i = 0 or 1) bit in the uic1 register to 1 (enables continuous receive mode). in this mode, reading the uirb regi ster sets the ti bit in the uic1 register to 0 (data in the uitb register). when the uirrm bit is set to 1, do not write dummy data to the uitb register by a program. r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 253 of 453 rej09b0278-0210 15.2 clock asynchronous serial i/o (uart) mode the uart mode allows data transmission and reception after setting the desire d bit rate and tran sfer data format. table 15.4 lists the specifications of uart mode. tabl e 15.5 lists the registers used and settings for uart mode. i = 0 or 1 note: 1. if an overrun error occu rs, the receive data (b0 to b8) of the uirb register will be undefined. the ir bit in the siric register remains unchanged. table 15.4 specifications of uart mode item specification transfer data formats ? character bit (transfer data): selectable among 7, 8 or 9 bits ? start bit: 1 bit ? parity bit: selectable among odd, even, or none ? stop bit: selectable among 1 or 2 bits transfer clocks ? ckdir bit in uimr register is set to 0 (internal clock): fj/(16(n+1)) fj = f1, f8, f32 n = value set in uibrg register: 00h to ffh ? ckdir bit is set to 1 (ext ernal clock): fext/(16(n+1)) fext: input from clki pin, n = value set in uibrg register: 00h to ffh transmit start conditions ? before transmission starts, the following are required - te bit in uic1 register is set to 1 (transmission enabled) - ti bit in uic1 register is se t to 0 (data in uitb register) receive start conditions ? before reception starts, the following are required - re bit in uic1 register is set to 1 (reception enabled) - start bit detected interrupt request generation timing ? when transmitting, one of the following conditions can be selected - uiirs bit is set to 0 (transmit buffer empty): when transferring data from the uitb register to uarti transmit register (when transmit starts). - uiirs bit is set to 1 (transfer ends): when serial interfac.e completes transmitting data from the uarti transmit register ? when receiving when transferring data from the uart i receive register to uirb register (when receive ends). error detection ? overrun error (1) this error occurs if the se rial interface starts receiving the next data item before reading the uirb re gister and receive the bit preceding the final stop bit of the next data item. ? framing error this error occurs when the set numb er of stop bits is not detected. ? parity error this error occurs when parity is enab led, and the number of 1?s in parity and character bits do not match the number of 1?s set. ? error sum flag this flag is set is set to 1 when an overrun, framing, or parity error is generated. r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 254 of 453 rej09b0278-0210 i = 0 or 1 notes: 1. the bits used for transmit/receive data are as follows: bits 0 to 6 when transfer data is 7 bits long; bits 0 to 7 when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long. 2. the following bits are undefined: bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer data is 8 bits long. table 15.6 lists the i/o pin functions in uart mode. after the uarti (i = 0 or 1) operating mode is selected, the txdi pin outputs ?h? level (if the nc h bit is set to 1 (n-channel open-dr ain output), this pin is in a high- impedance state) until transfer starts. table 15.5 registers used and settings for uart mode register bit function uitb 0 to 8 set transmit data (1) uirb 0 to 8 receive data can be read (1, 2) oer, fer, per, sum error flag uibrg 0 to 7 set a bit rate uimr smd2 to smd0 set to 100b when transfer data is 7 bits long. set to 101b when transfer data is 8 bits long. set to 110b when transfer data is 9 bits long. ckdir select the internal clock or external clock stps select the stop bit pry, prye select whether parity is included and whether odd or even uic0 clk0, clk1 select the count source for the uibrg register txept transmit register empty flag nch select txdi pin output mode ckpol set to 0 uform lsb first or msb first can be selected when transfer data is 8 bits long. set to 0 when transfer data is 7 or 9 bits long. uic1 te set to 1 to enable transmit ti transmit buffer empty flag re set to 1 to enable receive ri receive complete flag uiirs select the factor of uarti transmit interrupt uirrm set to 0 table 15.6 i/o pin functions in uart mode pin name function selection method txd0 (p1_4) output serial data (cannot be used as a port when performing reception only) rxd0 (p1_5) input serial data pd1_5 bit in pd1 register = 0 (p1_5 can be used as an input port when performing transmission only) clk0 (p1_6) programmable i/o port ckdir bit in u0mr register = 0 input transfer clock ckdir bit in u0mr register = 1 pd1_6 bit in pd1 register = 0 txd1 (either p0_0, p3_6, or p3_7) output serial data set registers pinsr1 and pmr (refer to figure 15.7 registers pinsr1 and pmr ) (cannot be used as a port when performing reception only) rxd1 (either p3_6, p3_7, or p4_5) input serial data set registers pinsr1 and pmr (refer to figure 15.7 registers pinsr1 and pmr ) corresponding bit in each port direction register = 0 (can be used as an input port when performing transmission only) clk1 (p0_5) programmable i/o port ckdir bit in u1mr register = 0 input transfer clock pd0_5 bit in pd0 register = 0 ckdir bit in u1mr register = 1 r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 255 of 453 rej09b0278-0210 figure 15.11 transmit timing in uart mode d0 tc d1 d2 d3 d4 d5 d6 d7 p sp st d0 d1 d2 d3 d4 d5 d6 d7 p sp st d0 d1 st d0 tc d1 d2 d3 d4 d5 d6 d7 d8 sp sp st d0 d1 d2 d3 d4 d5 d6 d7 d8 sp sp st d0 d1 st transfer clock te bit in uic1 register txdi set to 0 when interrupt request is acknowledged, or set by a program ? transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit) write data to uitb register tc=16 (n + 1) / fj or 16 (n + 1) / fext fj: frequency of uibrg count source (f1, f8, f32) fext: frequency of uibrg count source (external clock) n: setting value to uibrg register i = 0 or 1 the above timing diagram applies under the following conditions: ? prye bit in uimr register = 1 (parity enabled) ? stps bit in uimr register = 0 (1 stop bit) ? uiirs bit in uic1 register = 1 (an inte rrupt request is generated when transmit completes) start bit parity bit stop pulsing because the te bit is set to 0 txdi write data to uitb register transfer from uitb register to uarti transmit register ti bit in uic1 register 1 0 1 0 1 0 1 0 txept bit in uic0 register ir bit sitic register stop bit ? transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits) 1 0 stop bit stop bit start bit transfer clock te bit in uic1 register ti bit in uic1 register txept bit in uic0 register ir bit in sitic register 1 0 1 0 1 0 transfer from uitb register to uarti transmit register tc=16 (n + 1) / fj or 16 (n + 1) / fext fj: frequency of uibrg count source (f1, f8, f32) fext: frequency of uibrg count source (external clock) n: setting value to uibrg register i = 0 or 1 set to 0 when interrupt request is acknowledged, or set by a program the above timing diagram applies under the following conditions: ? prye bit in uimr register = 0 (parity disabled) ? stps bit in uimr register = 1 (2 stop bits) ? uiirs bit in uic1 register = 0 (an interr upt request is generated when transmit buffer is empty) r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 256 of 453 rej09b0278-0210 figure 15.12 receive timi ng example in uart mode uibrg output set to 0 when interrupt request is accepted, or set by a program ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) the above timing diagram applies when the register bits are set as follows: ? prye bit in uimr register = 0 (parity disabled) ? stps bit in uimr register = 0 (1 stop bit) i = 0 or 1 uic1 register re bit start bit stop bit d0 d1 d7 rxdi transfer clock determined to be ?l? receive data taken in reception triggered when transfer clock is generated by falling edge of start bit transferred from uarti receive register to uirb register uic1 register ri bit siric register ir bit 1 0 1 0 1 0 r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 257 of 453 rej09b0278-0210 15.2.1 bit rate in uart mode, the bit rate is the frequency divided by the uibrg (i = 0 or 1) register. figure 15.13 calculation formula of uibrg (i = 0 or 1) register setting value i = 0 or 1 note: 1. for the high-speed on-chip oscillator, the correction value in the fra7 register should be written into the fra1 register (for n, d version only). this applies when the high-speed on-chip oscillator is sele cted as the system clock and bits fra22 to fra20 in the fra2 register are set to 000b (divide-by-2 mode). for the precision of the high-speed on-chip oscillator, refer to 20. electrical characteristics . table 15.7 bit rate setting example in uart mode (interna l clock selected) bit rate (bps) uibrg count source system clock = 20 mhz system clock = 18.432 mhz (1) system clock = 8 mhz uibrg setting value actual time (bps) setting error (%) uibrg setting value actual time (bps) setting error (%) uibrg setting value actual time (bps) setting error (%) 1200 f8 129 (81h) 1201.92 0.16 119 (77h) 1200.00 0.00 51 (33h) 1201.92 0.16 2400 f8 64 (40h) 2403.85 0.16 59 (3bh) 2400.00 0.00 25 (19h) 2403.85 0.16 4800 f8 32 (20h) 4734.85 -1.36 29 (1dh) 4800.00 0.00 12 (0ch) 4807.69 0.16 9600 f1 129 (81h) 9615.38 0.16 119 (77h) 9600.00 0.00 51 (33h) 9615.38 0.16 14400 f1 86 (56h) 14367.82 -0.22 79 (4fh) 14400.00 0.00 34 (22h) 14285.71 -0.79 19200 f1 64 (40h) 19230.77 0.16 59 (3bh) 19200.00 0.00 25 (19h) 19230.77 0.16 28800 f1 42 (2ah) 29069.77 0.94 39 (27h) 28800.00 0.00 16 (10h) 29411.76 2.12 38400 f1 32 (20h) 37878.79 -1.36 29 (1dh) 38400.00 0.00 12 (0ch) 38461.54 0.16 57600 f1 21 (15h) 56818.18 -1.36 19 (13h) 57600.00 0.00 8 (08h) 55555.56 -3.55 115200 f1 10 (0ah) 113636.36 -1.36 9 (09h) 115200.00 0.00 ??? uart mode ? internal clock selected uibrg register setting value = fj bit rate 16 - 1 fj: count source frequency of the uibrg register (f1, f8, or f32) ? external clock selected fext bit rate 16 - 1 fext: count source frequency of the uibrg register (external clock) uibrg register setting value = i = 0 or 1 r8c/26 group, r8c/27 group 15. serial interface rev.2.10 sep 26, 2008 page 258 of 453 rej09b0278-0210 15.3 notes on serial interface ? when reading data from the uirb (i = 0 or 1) register eith er in the clock synchronous serial i/o mode or in the clock asynchronous serial i/o mode. ensu re the data is read in 16-bit units. when the high-order byte of the uirb register is read, bits per and fe r in the uirb register and the ri bit in the uic1 register are set to 0. to check receive errors, read the uirb register and then use the read data. example (when reading r eceive buffer register): mov.w 00a6h,r0 ; read the u0rb register ? when writing data to the uitb register in the clock asynchronous serial i/o mode with 9-bit transfer data length, write data to the high-order byte first then the low-order byte, in 8-bit units. example (when reading tran smit buffer register): mov.b #xxh,00a3h ; write the high-order byte of u0tb register mov.b #xxh,00a2h ; write the low-order byte of u0tb register r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 259 of 453 rej09b0278-0210 16. clock synchronous serial interface the clock synchronous serial inte rface is configured as follows. clock synchronous serial interface the clock synchronous serial interface uses the registers at addresses 00b8h to 00bfh. registers, bits, symbols, and functions vary even for the same addresses depending on the mode. refer to the register diagrams of each function for details. also, the differences between clock synchronous communi cation mode and clock synchronous serial mode are the options of the transfer clock, clock output format, and data output format. 16.1 mode selection the clock synchronous serial interface has four modes. table 16.1lists the mode selections. refer to 16.2 clock synchronous serial i/o with chip select (ssu) and the sections that follow for details of each mode. clock synchronous serial i/o with chip select (ssu) clock synchronous communication mode 4-wire bus communication mode i 2 c bus interface i 2 c bus interface mode clock synchronous serial mode table 16.1 mode selections iicsel bit in pmr register bit 7 in 00b8h (ice bit in iccr1 register) bit 0 in 00bdh (ssums bit in ssmr2 register, fs bit in sar register) function mode 0 0 0 clock synchronous serial i/o with chip select clock synchronous communication mode 0 0 1 4-wire bus communication mode 11 0 i 2 c bus interface i 2 c bus interface mode 1 1 1 clock synchronous serial mode r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 260 of 453 rej09b0278-0210 16.2 clock synchronous serial i/ o with chip select (ssu) clock synchronous serial i/o with chip select sup ports clock synchronous serial data communication. table 16.2 lists the specifications of clock synchronous serial i/o with chip select and figure 16.1 shows a block diagram of clock synchronous serial i/o with ch ip select. figures 16.2 to 16.9 show the registers associated with clock synchronous serial i/o with chip select. note: 1. clock synchronous serial i/o with chip se lect has only one interrupt vector table. table 16.2 specifications of clock synchronous serial i/o with chip select item specification transfer data format ? tra nsfer data length: 8 bits continuous transmission and reception of serial data are supported since both transmitter and receiver have buffer structures. operating modes ? clock synchronous communication mode ? 4-wire bus communication mode (including bidirectional communication) master/slave device selectable i/o pins ssck (i/o): clock i/o pin ssi (i/o): data i/o pin sso (i/o): data i/o pin scs (i/o): chip-select i/o pin transfer clocks ? when the mss bit in the sscrh register is set to 0 (operates as slave device), external clock is selected (input from ssck pin). ? when the mss bit in the sscrh register is set to 1 (operates as master device), internal clock (selectable among f1 /256, f1/128, f1/64, f1/32, f1/16, f1/8 and f1/4, output from ssck pin) is selected. ? clock polarity and phase of ssck can be selected. receive error detection ? overrun error overrun error occurs during reception and completes in error. while the rdrf bit in the sssr register is set to 1 (data in the ssr dr register) and when next serial data receive is completed, the orer bit is set to 1. multimaster error detection ? conflict error when the ssums bit in the ssmr2 register is set to 1 (4-wire bus communication mode) and the mss bit in the sscrh register is set to 1 (operates as master device) and when st arting a serial communication, the ce bit in the sssr register is set to 1 if ?l? applies to the scs pin input. when the ssums bit in the ssmr2 register is set to 1 (4-wire bus communication mode), the mss bit in the sscrh register is set to 0 (operates as slave device) and the scs pin input changes state from ?l? to ?h?, the ce bit in the sssr register is set to 1. interrupt requests 5 interrupt requests (transmi t-end, transmit-data-empty, receive-data-full, overrun error, and conflict error). (1) select functions ? data transfer direction selects msb-first or lsb-first ? ssck clock polarity selects ?l? or ?h? level when clock stops ? ssck clock phase selects edge of data change and data download ? ssi pin select function the ssisel bit in the pmr register ca n select p3_3 or p1_6 as ssi pin. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 261 of 453 rej09b0278-0210 figure 16.1 block diagram of clock sync hronous serial i/o with chip select ssmr register data bus transmit/receive control circuit sscrl register sscrh register sser register sssr register ssmr2 register sstdr register sstrsr register ssrdr register selector multiplexer sso ssi scs ssck interrupt requests (txi, tei, rxi, oei, and cei) internal clock generation circuit f1 internal clock (f1/i) i = 4, 8, 16, 32, 64, 128, or 256 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 262 of 453 rej09b0278-0210 figure 16.2 sscrh register ss control register h symbol address after reset sscrh 00b8h 00h bit symbol bit name function rw notes: 1. 2. 3. the ssck pin functions as the transfer clock output pin w hen the mss bit is set to 1 (operates as master device). the mss bit is set to 0 (operates as slave device) w hen the ce bit in the sssr register is set to 1 (conflict error occurs). rsstp receive single stop bit (3) 0 : maintains receive operation after receiving 1 byte of data 1 : completes receive operation after receiving 1 byte of data rw ? (b7) nothing is assigned. if necessary, set to 0. when read, the content is 0. the set clock is used w hen the internal clock is selected. ? master/slave device select bit (2) 0 : operates as slave device 1 : operates as master device rw mss ? (b4-b3) ? nothing is assigned. if necessary, set to 0. when read, the content is 0. cks1 cks2 transfer clock rate select bits (1) b2 b1 b0 0 0 0 : f1/256 0 0 1 : f1/128 0 1 0 : f1/64 0 1 1 : f1/32 1 0 0 : f1/16 1 0 1 : f1/8 1 1 0 : f1/4 1 1 1 : do not set. cks0 rw rw rw the rsstp bit is disabled w hen the mss bit is set to 0 (operates as slave device). b7 b6 b5 b4 b3 b2 b1 b0 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 263 of 453 rej09b0278-0210 figure 16.3 sscrl register ss control register l symbol address after reset sscrl 00b9h 01111101b bit symbol bit name function rw notes: 1. 2. 3. ? (b0) ? nothing is assigned. if necessary, set to 0. when read, the content is 1. sres clock synchronous serial i/o w ith chip select control part reset bit when this bit is set to 1, the clock synchronous serial i/o w ith chip select control block and sstrsr register are reset. the values of the registers (1) in the clock synchronous serial i/o w ith chip select register are maintained. rw b3 b2 b1 b0 b7 b6 b5 b4 ? (b7) nothing is assigned. if necessary, set to 0. when read, the content is 0. ? ? (b3-b2) nothing is assigned. if necessary, set to 0. when read, the content is 1. ? solp sol w rite protect bit (2) the output level can be changed by the sol bit w hen this bit is set to 0. the solp bit remains unchanged even if 1 is w ritten to it. when read, the content is 1. rw do not w rite to the sol bit during data transfer. the data output after serial data is output can be changed by w riting to the sol bit before or after transfer. when w riting to the sol bit, set the solp bit to 0 and the sol bit to 0 or 1 simultaneously by the mov instruction. registers sscrh, sscrl, ssmr, sser, sssr, ssmr2, sstdr, and ssrdr. sol serial data output value setting bit when read 0 : the serial data output is set to ?l? 1 : the serial data output is set to ?h? when w ritten (2, 3) 0 : the data output is ?l? after the serial data output 1 : the data output is ?h? after the serial data output rw ? (b6) nothing is assigned. if necessary, set to 0. when read, the content is 1. ? r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 264 of 453 rej09b0278-0210 figure 16.4 ssmr register ss mode register symbol address after reset ssmr 00bah 00011000b bit symbol bit name function rw reserved bit note: 1. 1 msb first/lsb first select bit mls nothing is assigned. if necessary, set to 0. when read, the content is 1. ? (b3) ? (b4) cphs cpos ssck clock polarity select bit (1) b7 b6 b5 b4 b3 b2 b1 b0 ref er to 16.2.1.1 association betw een transfer clock polarity, phase, and data for the settings of the cphs and cpos bits. ro bc1 bc2 bits counter 2 to 0 b2 b1 b0 0 0 0 : 8 bits left 0 0 1 : 1 bit left 0 1 0 : 2 bits left 0 1 1 : 3 bits left 1 0 0 : 4 bits left 1 0 1 : 5 bits left 1 1 0 : 6 bits left 1 1 1 : 7 bits left bc0 ro ro ssck clock phase select bit (1) 0 : ?h? w hen clock stops 1 : ?l? w hen clock stops set to 1. when read, the content is 1. rw rw rw ? rw 0 : transfers data msb first 1 : transfers data lsb first 0 : change data at odd edge (dow nload data at even edge) 1 : change data at even edge (dow nload data at odd edge) r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 265 of 453 rej09b0278-0210 figure 16.5 sser register ss enable register symbol address after reset sser 00bbh 00h bit symbol bit name function rw 0 : disables transmit end interrupt request 1 : enables transmit end interrupt request rw receive enable bit 0 : disables receive 1 : enables receive transmit enable bit 0 : disables transmit 1 : enables transmit 0 : disables receive data full and overrun error interrupt request 1 : enables receive data full and overrun error interrupt request receive interrupt enable bit rw re te teie transmit end interrupt enable bit rw rie tie transmit interrupt enable bit 0 : disables transmit data empty interrupt request 1 : enables transmit data empty interrupt request conflict error interrupt enable bit 0 : disables conflict error interrupt request 1 : enables conflict error interrupt request ? (b2-b1) nothing is assigned. if necessary, set to 0. when read, the content is 0. ceie rw rw rw ? b7 b6 b5 b4 b0 b3 b2 b1 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 266 of 453 rej09b0278-0210 figure 16.6 sssr register ss status register (7) symbol address after reset sssr 00bch 00h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. b0 writing 1 to ce, orer, rdrf, tend, or tdre bits invalid. to set any of these bits to 0, first read 1 then w rite 0. the rdrf bit is set to 0 w hen reading out the data from the ssrdr register. nothing is assigned. if necessary, set to 0. when read, the content is 0. tdre transmit data empty (1, 5, 6) 0 : data is not transferred from registers sstdr to sstrsr 1 : data is transferred from registers sstdr to sstrsr rw b3 b2 b1 b7 b6 b5 b4 rdrf receive data register full (1,4) ? (b1) nothing is assigned. if necessary, set to 0. when read, the content is 0. 0 : no data in ssrdr register 1 : data in ssrdr r egis ter orer ? (b4-b3) rw rw ? conflict error flag (1) 0 : no conflict errors generated 1 : conflict errors generated (2) ce ? bits tend and tdre are set to 0 w hen w riting data to the sstdr register. overrun error flag (1) 0 : no overrun errors generated 1 : overrun errors generated (3) tend transmit end (1, 5) 0 : the tdre bit is set to 0 w hen transmitting the last bit of transmit data 1 : the tdre bit is set to 1 w hen transmitting the last bit of transmit data rw rw when the serial communication is started w hile the ssums bit in the ssmr2 register is set to 1 (four-w ire bus communication mode) and the mss bit in the sscrh register is set to 1 (operates as master device), the ce bit is set to 1 if ?l? is applied to the scs _ ____ pin input. refer to 16.2.7 scs _ ____ pin control and arbitration for more information . sscrh register is set to 0 (operates as slave device) and the scs _ ____ pin input changes the level from ?l? to ?h? during when the ssums bit in the ssmr2 register is set to 1 (four-w ire bus communication mode), the mss bit in the when accessing the sssr register continuously, insert one or more nop instructions betw een the instructions to access it. the tdre bit is set to 1 w hen the te bit in the sser register is set to 1 (transmit enabled). transfer, the ce bit is set to 1. indicates w hen overrun errors occur and receive completes by error reception. if the next serial data receive operation is completed w hile the rdrf bit is set to 1 (data in the ssrdr register), the orer bit is set to 1. after the orer bit is set to 1 (overrun error), transmit and receive operations are disabled w hile the bit remains 1. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 267 of 453 rej09b0278-0210 figure 16.7 ssmr2 register ss mode register 2 symbol address after reset ssmr2 00bdh 00h bit symbol bit name function rw scs _ ____ pin open drain output 0 : cmos output select bit 1 : n-channel open drain output scs _ ____ pin select bits (2) b5 b4 0 0 : functions as port 0 1 : functions as scs _ ____ input pin 1 0 : functions as scs _ ____ output pin (3) 1 1 : functions as scs _ ____ output pin (3) notes: 1. 2. 3. 4. 5. the ssi pin and sso pin corresponding port direction bits are set to 0 (input mode) w hen the soos bit is set to 0 (cmos output). the bide bit is disabled w hen the ssums bit is set to 0 (clock synchronous communication mode). rw bide bidirectional mode enable bit (1, 4) 0 : standard mode (communication using 2 pins of data input and data output) 1 : bidirectional mode (communication using 1 pin of data input and data output) this bit functions as the scs _ ____ input pin before starting transfer. bit is set to 0 (clock synchronous communication mode). rw rw rw rw rw rw 0 : clock synchronous communication mode 1 : four-w ire bus communication mode ssck pin open drain output select bit 0 : cmos output 1 : n-channel open drain output css1 clock synchronous serial i/o w ith chip select mode select bit (1) serial data pin open output drain select bit (1) 0 : cmos output (5) 1 : n-channel open drain output css0 soos sckos ssums csos b2 b1 b7 b6 b5 b4 b0 ref er to 16.2.2.1 association betw een data i/o pins and ss shift register for information on combinations of data i/o pins. the scs _ ____ pin functions as a port, regardless of the values of bits css0 and css1 w hen the ssums scks ssck pin select bit 0 : functions as port 1 : functions as serial clock pin rw b3 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 268 of 453 rej09b0278-0210 figure 16.8 registers sstdr and ssrdr ss transmit data register symbol address after reset sstdr 00beh ffh rw b4 b2 rw b1 function store the transmit data. the stored transmit data is transferred to the sstrsr register and transmission is started w hen it is detected that the sstrsr register is empty. when the next transmit data is w ritten to the sstdr register during the data transmission from the sstrsr register, the data can be transmitted continuously. when the mls bit in the ssmr register is set to 1 (transfer data w ith lsb-first), the data in w hich msb and lsb are reversed is read, after w riting to the sstdr register. b0 b3 b7 b6 b5 ss receive data register symbol address after reset ssrdr 00bfh ffh rw note: 1. the ssrdr register retains the data reception before an overrun error occurs (orer bit in the sssr register set to 1 (overrun error)). when an overrun error occurs, the receive data may contain errors and therefore should be discarded. store the receive data. (1) the receive data is transferred to the ssrdr register and the receive operation is completed w hen 1 byte of data has been received by the sstrsr register. at this time, the next receive operation is possible. continuous reception is possible using registers sstrsr and ssrdr. ro function b3 b2 b1 b0 b7 b6 b5 b4 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 269 of 453 rej09b0278-0210 figure 16.9 pmr register port mode registe r symbol address after reset pmr 00f8h 00h bit symbol bit name function rw int1 _ ____ pin select bit note: 1. the uart1 pins can be selected by using bits u1pinsel, txd1sel and txd1en, and bits uart1sel1 and uart1sel0 in the pinsr1 register. iicsel ssu / i 2 c bus pin sw itch bit 0 : selects ssu function 1 : selects i 2 c bus function rw txd1en txd1/rxd1 select bit (1) 0 : rxd1 1 : txd1 rw txd1sel port/txd1 pin sw itch bit (1) 0 : programmable i/o port 1 : txd1 rw u1 pinsel txd1 pin sw itch bit (1) 0 : p0_0 1 : p3_6, p3_7 rw ssisel ssi pin select bit 0 : p3_3 1 : p1_6 rw int1sel 0 : p1_5, p1_7 1 : p3_6 rw ? (b2-b1) ? nothing is assigned. if necessary, set to 0. when read, the content is 0. b0 b3 b2 b1 b7 b6 b5 b4 pinsr1 regis ter ua rt1sel1, ua rt1sel0 bit u1pinsel bit txd1sel bit txd1en bit p3_7(txd1) 1 p3_7(rxd1) 0 p0_0(txd1) 0 1 p3_7(txd1) 1 p4_5(rxd1) p3_6(txd1) 1 p3_6(rxd1) 0 p0_0(txd1) 0 1 : 0 or 1 10b pmr register pin function 00b 01b 1 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 270 of 453 rej09b0278-0210 16.2.1 transfer clock the transfer clock can be selected fro m among seven internal clocks (f1/256, f1/128, f1/64, f1/ 32, f1/16, f1/8, and f1/4) and an external clock. when using clock synchronous serial i/o with chip sele ct, set the scks bit in the ssmr2 register to 1 and select the ssck pin as the serial clock pin. when the mss bit in the sscrh register is set to 1 (operates as master device), an internal clock can be selected and the ssck pin functions as output. when tran sfer is started, the ssck pin outputs clocks of the transfer rate selected by bits cks0 to cks2 in the sscrh register. when the mss bit in the sscrh register is set to 0 (ope rates as slave device), an external clock can be selected and the ssck pin functions as input. 16.2.1.1 association between transf er clock polarity, phase, and data the association between the transfer clock polarity, phase and data change s according to the combination of the ssums bit in the ssmr2 register and bits cphs and cpos in the ssmr register. figure 16.10 shows the association between transf er clock polarity, phase, and transfer data. also, the msb-first transfer or lsb-first transfer can be selected by setting the mls bit in the ssmr register. when the mls bit is set to 1, transfer is started fr om the lsb and proceeds to th e msb. when the mls bit is set to 0, transfer is started fr om the msb and proceeds to the lsb. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 271 of 453 rej09b0278-0210 figure 16.10 association between transfer clock polarity, phase, and transfer data ssck b0 sso, ssi ? ssums = 0 (clock synchronous communication mode), cphs bit = 0 (data change at odd edge), and cpos bit = 0 (?h? when clock stops) b1 b2 b3 b4 b5 b6 b7 ssck cpos = 0 (?h? when clock stops) b0 sso, ssi ? ssums = 1 (4-wire bus communication mode) and cphs = 0 (data change at odd edge) b1 b2 b3 b4 b5 b6 b7 ssck cpos = 1 (?l? when clock stops) scs ssck cpos = 0 (?h? when clock stops) sso, ssi ? ssums = 1 (4-wire bus communication mode) and cphs = 1 (data download at odd edge) ssck cpos = 1 (?l? when clock stops) scs b0 b1 b2 b3 b4 b5 b6 b7 cphs and cpos: bits in ssmr register, ssums: bits in ssmr2 register r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 272 of 453 rej09b0278-0210 16.2.2 ss shift register (sstrsr) the sstrsr register is a sh ift register for transmittin g and receiving serial data. when transmit data is transferred from the sstdr regi ster to the sstrsr register and the mls bit in the ssmr register is set to 0 (msb-first), the bit 0 in the sstdr register is transferred to bit 0 in the sstrsr register. when the mls bit is set to 1 (lsb-first), bit 7 in the sstdr register is transferred to bit 0 in the sstrsr register. 16.2.2.1 association between data i/o pins and ss shift register the connection between the data i/o pins and sstrsr re gister (ss shift register ) changes according to a combination of the mss bit in the sscrh register an d the ssums bit in the ssmr2 register. the connection also changes according to the bi de bit in the ssmr2 register. figure 16.11 shows the association between data i/o pins and sstrsr register. figure 16.11 association between da ta i/o pins and sstrsr register sstrsr register sso ssi ? ssums = 0 (clock synchronous communication mode) sstrsr register sso ssi ? ssums = 1 (4-wire bus communication mode), bide = 0 (standard mode), and mss = 0 (operates as slave device) sstrsr register sso ssi ? ssums = 1 (4-wire bus communication mode), bide = 0 (standard mode), and mss = 1 (operates as master device) sstrsr register sso ssi ? ssums = 1 (4-wire bus communication mode) and bide = 1 (bidirectional mode) r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 273 of 453 rej09b0278-0210 16.2.3 interrupt requests clock synchronous serial i/o with chip select has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error, and conflict error. si nce these interrupt requests are assigned to the clock synchronous serial i/o with chip select interrupt vector table, determining interrupt sources by flags is required. table 16.3 shows the clock synchronous serial i/o with chip select interrupt requests. ceie, rie, teie and tie: bits in sser register orer, rdrf, tend and tdre: bits in sssr register if the generation conditions in table 16.3 are met, a clock synchronous serial i/o with chip select interrupt request is generated. set each interrupt source to 0 by a clock sy nchronous serial i/ o with chip select interrupt routine. however, the tdre and tend bits are automatically set to 0 by writing transmit data to the sstdr register and the rdrf bit is automatically set to 0 by reading the ssrdr register. in particular, the tdre bit is set to 1 (data transmitted from registers sstdr to sst rsr) at the same time transmit data is written to the sstdr register. setting the tdre bit to 0 (data not transmitted from re gisters sstdr to sstrsr) can cause an additional byte of data to be transmitted. table 16.3 clock synchronous serial i/o with chip select interrupt requests interrupt request abbreviation generation condition transmit data empty txi tie = 1, tdre = 1 transmit end tei teie = 1, tend = 1 receive data full rxi rie = 1, rdrf = 1 overrun error oei rie = 1, orer = 1 conflict error cei ceie = 1, ce = 1 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 274 of 453 rej09b0278-0210 16.2.4 communication mo des and pin functions clock synchronous serial i/o with chip select switches the functions of the i/o pins in each communication mode according to the se tting of the mss bit in the sscrh register and bits re and te in the sser register. table 16.4 shows the association between communication modes and i/o pins. notes: 1. this pin can be used as a programmable i/o port. 2. do not set both bits te and re to 1 in 4-wire bus (bidirectional) communication mode. ssums and bide: bits in ssmr2 register mss: bit in sscrh register te and re: bits in sser register table 16.4 association between communication modes and i/o pins communication mode bit setting pin state ssums bide mss te re ssi sso ssck clock synchronous communication mode 0disabled001input ? (1) input 10 ? (1) output input 1 input output input 101input ? (1) output 10 ? (1) output output 1 input output output 4-wire bus communication mode 10 001 ? (1) input input 1 0 output ? (1) input 1 output input input 101input ? (1) output 10 ? (1) output output 1 input output output 4-wire bus (bidirectional) communication mode (2) 11 001 ? (1) input input 10 ? (1) output input 101 ? (1) input output 10 ? (1) output output r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 275 of 453 rej09b0278-0210 16.2.5 clock synchronous communication mode 16.2.5.1 initialization in cl ock synchronous communication mode figure 16.12 shows the initialization in clock synchronous communication mode. to initialize, set the te bit in the sser register to 0 (transmit di sabled) and the re bit to 0 (receive disabled) before data transmission or reception. set the te bit to 0 and the re bit to 0 before changing the communication mode or format. setting the re bit to 0 does not change the contents of flags rdrf and orer or the contents of the ssrdr register. figure 16.12 initialization in cl ock synchronous communication mode start ssmr2 register ssums bit 0 sscrh register set bits cks0 to cks2 set rsstp bit sssr register orer bit 0 (1) sser register re bit 1 (receive) te bit 1 (transmit) set bits rie, teie, and tie end note: 1. write 0 after reading 1 to set the orer bit to 0. sser register re bit 0 te bit 0 ssmr2 register scks bit 1 set soos bit sscrh register set mss bit ssmr register cphs bit 0 cpos bit 0 set mls bit r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 276 of 453 rej09b0278-0210 16.2.5.2 data transmission figure 16.13 shows an example of clock synchronous serial i/o with chip select operation for data transmission (clock synchronous communication mode). during data transmission, the clock synchronous serial i/o with chip select operates as described below. when clock synchronous serial i/o with chip select is set as a master devi ce, it outputs a synchronous clock and data. when clock synchronous serial i/o with chip sele ct is set as a slave device, it outputs data synchronized with the input clock. when the te bit is set to 1 (transmit enabled) before writing the transmit data to the sstdr register, the tdre bit is automatically set to 0 (data not transferred from registers sstdr to sstrsr) and the data is transferred from registers sstdr to sstrsr. after the tdre bit is set to 1 (data transferred from registers sstdr to sstrsr), transmission starts. when the tie bit in the sser register is set to 1, the txi in terrupt request is generated. when one frame of data is transferred while the tdre bit is set to 0, data is transferred from registers sstdr to sstrsr and transmission of the next frame is star ted. if the 8th bit is transmitted while the tdre bit is set to 1, the tend bit in the sssr register is set to 1 (the tdre bit is set to 1 when the last bit of the transmit data is transmitted) and the state is retained. the tei interrupt request is ge nerated when the teie bit in the sser register is set to 1 (transmit-end interrupt request enabled). th e ssck pin is fixed ?h? after transmit-end. transmit cannot be performed while the orer bit in the ss sr register is set to 1 (overrun error). confirm that the orer bit is set to 0 before transmission. figure 16.14 shows a sample flowchart of data tr ansmission (clock synchronous communication mode). figure 16.13 example of clock synchronous serial i/o with chip select operation for data transmission (clock synchronous communication mode) ssck b0 sso ? ssums = 0 (clock synchronous communication mode), cphs = 0 (data change at odd numbers), and cpos = 0 (?h? when clock stops) b1 b7 b0 b1 b7 1 frame tdre bit in sssr register 0 1 tend bit in sssr register 0 1 tei interrupt request generation write data to sstdr register processing by program 1 frame txi interrupt request generation r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 277 of 453 rej09b0278-0210 figure 16.14 sample flowchart of data transmis sion (clock synchronous communication mode) start initialization read tdre bit in sssr register sssr register tend bit 0 (1) end tdre = 1 ? write transmit data to sstdr register data transmission continues? read tend bit in sssr register tend = 1 ? no yes yes no no yes sser register te bit 0 (1) (2) (3) (1) after reading the sssr register and confirming that the tdre bit is set to 1, write the transmit data to the sstdr register. when the transmit data is written to the sstdr register, the tdre bit is automatically set to 0. (2) determine whether data transmission continues. (3) when data transmission is completed, the tend bit is set to 1. set the tend bit to 0 and the te bit to 0 and complete transmit mode. note: 1. write 0 after reading 1 to set the tend bit to 0. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 278 of 453 rej09b0278-0210 16.2.5.3 data reception figure 16.15 shows an example of clock synchronous serial i/o with chip select operation for data reception (clock synchronous communication mode). during data reception, clock synchronous serial i/o with chip select operates as described below. when the clock synchronous serial i/o with chip select is set as the master device, it outputs a synchronous clock and inputs data. when the clock synchronous serial i/o with chip select is set as a slave device, it inputs data synchronized with the input clock. when clock synchronous serial i/o with chip select is set as a master devi ce, it outputs a receive clock and starts receiving by performing dummy read of the ssrdr register. after 8 bits of data are received, the rdrf bit in the sssr register is set to 1 (data in the ssrdr register) and receive data is stored in the ssrdr register. when the rie bit in the sser register is set to 1 (rxi and oei interrupt requests enabled), the rxi interrupt request is ge nerated. if the ssdr regist er is read, the rdrf bit is automatically set to 0 (no data in the ssrdr register). read the receive data after setting the rsstp bit in the sscrh register to 1 (after receiving 1 byte of data, the receive operation is completed). clock synchronous serial i/o with chip select outputs a clock for receiving 8 bits of data and stops. after that, set the re bit in th e sser register to 0 (receive disabled) and the rsstp bit to 0 (receive operation is continued afte r receiving the 1 byte of data) and read the receive data. if the ssrdr register is read while the re bit is set to 1 (r eceive enabled), a receive clock is output again. when the 8th clock rises while the rdrf bit is set to 1, the orer bit in the sssr register is set to 1 (overrun error: oei) and the op eration is stopped. when the orer bit is se t to 1, receive cannot be performed. confirm that the orer bit is set to 0 before restarting receive. figure 16.16 shows a sample flow chart for data reception (mss = 1) (clock synchronous communication mode). figure 16.15 example of clock synchronous serial i/o with chip select operation for data reception (clock synchronous communication mode) ssck b0 ssi ? ssums = 0 (clock synchronous communic ation mode), cphs = 0 (data download at even edges), and cpos bit = 0 (?h? when clock stops) b0 b7 1 frame rdrf bit in sssr register 0 1 rsstp bit in sscrh register 0 1 dummy read in ssrdr register processing by program rxi interrupt request generation b0 b7 b7 1 frame rxi interrupt request generation read data in ssrdr register read data in ssrdr register set rsstp bit to 1 rxi interrupt request generation r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 279 of 453 rej09b0278-0210 figure 16.16 sample flowchart for data recepti on (mss = 1) (clock synchronous communication mode) start initialization dummy read of ssrdr register read receive data in ssrdr register read orer bit in sssr register last data received? read rdrf bit in sssr register rdrf = 1 ? no yes yes no no yes (1) (2) (3) (1) after setting each register in the clock synchronous serial i/o with chip select register, a dummy read of the ssrdr register is performed and the receive operation is started. (2) determine whether it is the last 1 byte of data to be received. if so, set to stop after the data is received. (3) if a receive error occurs, perform error (6) processing after reading the orer bit. then set the orer bit to 0. transmission/reception cannot be restarted while the orer bit is set to 1. (4) confirm that the rdrf bit is set to 1. if the rdrf bit is set to 1, read the receive data in the ssrdr register. when the ssrdr register is read, the rdrf bit is automatically set to 0. orer = 1 ? end read receive data in ssrdr register read orer bit in sssr register read rdrf in sssr register rdrf = 1 ? no yes orer = 1 ? sser register re bit 0 sscrh register rsstp bit 0 sscrh register rsstp bit 1 overrun error processing no yes (4) (5) (6) (7) (7) confirm that the rdrf bit is set to 1. when the receive operation is completed, set the rsstp bit to 0 and the re bit to 0 before reading the last 1 byte of data. if the ssrdr register is read before setting the re bit to 0, the receive operation is restarted again. (5) before the last 1 byte of data is received, set the rsstp bit to 1 and stop after the data is received. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 280 of 453 rej09b0278-0210 16.2.5.4 data transmission/reception data transmission/reception is an operation combining data transmission and reception which were described earlier. transmission/reception is started by writing data to the sstdr register. when the 8th clock rises or the orer bit is set to 1 (overrun error) while the tdre bit is set to 1 (data is transferred from registers sstd r to sstrsr), the transmit/r eceive operation is stopped. when switching from transmit mode (te = 1) or receiv e mode (re = 1) to transmit/receive mode (te = re = 1), set the te bit to 0 and re bit to 0 before switching. after confirming that the tend bit is set to 0 (the tdre bit is set to 0 when the last bit of the transmit data is transmitted), the rdrf bit is set to 0 (no data in the ssrdr register), and the orer bit is set to 0 (no overrun error), set bits te and re to 1. figure 16.17 shows a sample flowchart for data transmission/reception (clock synchronous communication mode). when exiting transmit/receive mode after this mode is used (te = re = 1), a clock may be output if transmit/receive mode is exit ed after reading the ssrdr re gister. to avoid any clock outputs, perform either of the following: - first set the re bit to 0, and then set the te bit to 0. - set bits te and re at the same time. when subsequently switching to receive mode (te = 0 and re = 1), first set the sres bit to 1, and set this bit to 0 to reset the clock synchronous serial interface cont rol unit and the sstrsr register. then, set the re bit to 1. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 281 of 453 rej09b0278-0210 figure 16.17 sample flowchart for data transmission/reception (clock synchronous communication mode) start initialization read tdre bit in sssr register sssr register tend bit 0 (1) end tdre = 1 ? write transmit data to sstdr register data transmission continues? no yes yes no sser register re bit 0 te bit 0 (1) (2) (3) (1) after reading the sssr register and confirming that the tdre bit is set to 1, write the transmit data to the sstdr register. when the transmit data is written to the sstdr register, the tdre bit is automatically set to 0. (5) set the tend bit to 0 and bits re and te in (6) the sser register to 0 before ending transmit/ receive mode. read receive data in ssrdr register read rdrf bit in sssr register rdrf = 1 ? no yes (4) (2) confirm that the rdrf bit is set to 1. if the rdrf bit is set to 1, read the receive data in the ssrdr register. when reading the ssrdr register is read, the rdrf bit is automatically set to 0. (3) determine whether the data transmission continues (5) note: 1. write 0 after reading 1 to set the tend bit to 0. read tend bit in sssr register tend = 1 ? yes no (6) (4) when the data transmission is completed, the tend bit in the sssr register is set to 1. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 282 of 453 rej09b0278-0210 16.2.6 operation in 4-wire bus communication mode in 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line, and a chip select line is used for communication. this mode includes bidirectional mode in which the data input line and data output line function as a single pin. the data input line and output line change according to the settings of the mss bit in the sscrh register and the bide bit in the ssmr2 register. for details, refer to 16.2.2.1 association between data i/o pins and ss shift register . in this mode, clock polarity, phase, and data settings are performed by the cpos and cphs bits in the ssmr register. for details, refer to 16.2.1.1 association between tran sfer clock polarity, phase, and data . when this mcu is set as the master device, the chip select line controls output. when the clock synchronous serial i/o with chip select is set as a slave device, the chip select line cont rols input. when it is set as master device, the chip select line controls output of the scs pin or controls ou tput of a general port according to the setting of the css1 bit in the ssmr2 register. when the mcu is set as a slave device, the chip select line sets the scs pin as an input pin by setting bits css1 and css0 in the ssmr2 register to 01b. in 4-wire bus communication mode, the mls bit in th e ssmr register is set to 0 and communication is performed msb-first. 16.2.6.1 initialization in 4-wire bus communication mode figure 16.18 shows the initialization in 4-wire bus communication mode. before the data transit/receive operation, set the te bit in the sser register to 0 (tra nsmit disabled), the re bit in the sser register to 0 (receive disabled), and initialize the clock synchronous serial i/o with chip select. to change the communication mode or format, set the te bit to 0 and the re bit to 0 before making the change. setting the re bit to 0 does not change the settings of flags rdrf and orer or the contents of the ssrdr register. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 283 of 453 rej09b0278-0210 figure 16.18 initialization in 4-wire bus communication mode start ssmr2 register ssums bit 1 sssr register orer bit 0 (1) sser register re bit 1 (receive) te bit 1 (transmit) set bits rie, teie, and tie end sser register re bit 0 te bit 0 (2) set the bide bit to 1 in bidirectional mode and set the i/o of the scs pin by bits css0 and css1. (1) (1) the mls bit is set to 0 for msb-first transfer. the clock polarity and phase are set by bits cphs and cpos. (2) note: 1. write 0 after reading 1 to set the orer bit to 0. ssmr2 register scks bit 1 set bits soos, css0 to css1, and bide sscrh register set mss bit ssmr register set bits cphs and cpos mls bits 0 sscrh register set bits cks0 to cks2 set rsstp bit r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 284 of 453 rej09b0278-0210 16.2.6.2 data transmission figure 16.19 shows an example of clock synchronous se rial i/o with chip select operation during data transmission (4-wire bus communication mode). during the data transmit operation, the clock synchronous serial i/o with chip select operates as described below. when the mcu is set as the master device, it outputs a synchronous clock and data. when the mcu is set as a slave device, it outputs data in synchronization with the input clock while the scs pin is ?l?. when the transmit data is written to the sstdr register after setting the te bit to 1 (transmit enabled), the tdre bit is automatically set to 0 (data has not been transferred from the sstdr to the sstrsr register) and the data is transferred from registers sstdr to sstrsr. after the tdre bit is set to 1 (data is transferred from registers sstdr to sstrsr), transmissi on starts. when the tie bit in the sser register is set to 1, a txi interrupt request is generated. after 1 frame of data is transferred while the tdre bit is set to 0, the data is tran sferred from registers sstdr to sstrsr and transmission of the next frame is started. if the 8th bit is transmitted while tdre is set to 1, tend in the sssr register is set to 1 (when the last bit of the transmit data is transmitted, the tdre bit is set to 1) and the state is retained. if the teie bit in the sser register is set to 1 (transmit-end interrupt requests enabled), a tei interrupt request is generated. the ssck pin remains ?h? after transmit-end and the scs pin is held ?h?. when transmitting continuously while the scs pin is held ?l?, write the next transmit data to the sstdr register before transmitting the 8th bit. transmission cannot be performed while the orer bit in th e sssr register is set to 1 (overrun er ror). confirm that the orer bit is set to 0 before transmission. in contrast to the clock synchronous communication mode, the sso pin is placed in high-impedance state while the scs pin is placed in high-impedance state when opera ting as a master device and the ssi pin is placed in high-impedance state while the scs pin is placed in ?h? input state when operat ing as a slave device. the sample flowchart is the same as that for the clock synchronous communication mode (refer to figure 16.14 sample flowchart of data transmission (clock synchronous communication mode) ). r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 285 of 453 rej09b0278-0210 figure 16.19 example of clock synchronous serial i/o with chip select operation during data transmission (4-wire bus communication mode) tdre bit in sssr register 0 1 tend bit in sssr register 0 1 data write to sstdr register processing by program ssck b0 sso ? cphs bit = 0 (data change at odd edges) and cpos bit = 0 (?h? when clock stops) b7 scs (output) ssck ? cphs bit = 1 (data change at even edges) and cpos bit = 0 (?h? when clock stops) cphs, cpos: bits in ssmr register 1 frame tdre bit in sssr register 0 1 tend bit in sssr register 0 1 data write to sstdr register processing by program 1 frame high-impedance b0 b7 high-impedance scs (output) txi interrupt request is generated b7 b0 sso 1 frame 1 frame b6 b6 txi interrupt request is generated tei interrupt request is generated b6 b7 b0 b6 tei interrupt request is generated txi interrupt request is generated txi interrupt request is generated r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 286 of 453 rej09b0278-0210 16.2.6.3 data reception figure 16.20 shows an example of clock synchronous se rial i/o with chip select operation during data reception (4-wire bus communication mode). during data reception, clock synchron ous serial i/o with chip select operates as described below. when the mcu is set as the master device, it outputs a synchronous clock and inputs data. when the mcu is set as a slave device, it outputs data synchr onized with the inpu t clock while the scs pin receives ?l? input. when the mcu is set as the master device, it outputs a receive clock and starts receiving by performing a dummy read of the ssrdr register. after the 8 bits of data are received, the rdrf bit in the sssr register is set to 1 (data in the ssrdr register) and receive data is stored in the ssr dr register. when the rie bit in the sser register is set to 1 (rxi and oei interrupt requests enabled), an rxi interrupt reques t is generated. when the ss rdr register is read, the rdrf bit is automatically set to 0 (no data in the ssrdr register). read the receive data after setting the rsstp bit in th e sscrh register to 1 (after receiving 1-byte data, the receive operation is completed). clock synchronous serial i/o with chip select outputs a clock for receiving 8 bits of data and stops. after that, set the re bit in th e sser register to 0 (receive disabled) and the rsstp bit to 0 (receive operation is continued af ter receiving 1-byte data) and read the receive data. when the ssrdr register is read while the re bit is set to 1 (r eceive enabled), a receive clock is output again. when the 8th clock rises while the rdrf bit is set to 1, the orer bit in the sssr register is set to 1 (overrun error: oei) and the operation is st opped. when the orer bit is set to 1, reception can not be performed. confirm that the orer bit is set to 0 before restarting reception. the timing with which bits rdrf and orer are set to 1 varies depending on the setting of the cphs bit in the ssmr register. figure 16.20 shows when bits rdrf and orer are set to 1. when the cphs bit is set to 1 (dat a download at the odd edges), bits rd rf and orer are set to 1 at some point during the frame. the sample flowchart is the same as that for the clock synchronous communication mode (refer to figure 16.16 sample flowchart for data reception (mss = 1) (clock synchronou s communication mode) ). r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 287 of 453 rej09b0278-0210 figure 16.20 example of clock synchronous serial i/o with chip select operation during data reception (4-wire bus communication mode) ssck b0 ssi ? cphs bit = 0 (data download at even edges) and cpos bit = 0 (?h? when clock stops) b7 scs (output) ssck ? cphs bit = 1 (data download at odd edges) and cpos bit = 0 (?h? when clock stops) cphs and cpos: bit in ssmr register 1 frame rdrf bit in sssr register 0 1 rsstp bit in sscrh register 0 1 dummy read in ssrdr register processing by program 1 frame high-impedance b0 b7 high-impedance scs (output) b7 b0 data read in ssrdr register rxi interrupt request is generated rxi interrupt request is generated data read in ssrdr register rxi interrupt request is generated b0 b7 b0 b7 b7 b0 ssi 1 frame rdrf bit in sssr register 0 1 rsstp bit in sscrh register 0 1 dummy read in ssrdr register processing by program 1 frame data read in ssrdr register rxi interrupt request is generated rxi interrupt request is generated rxi interrupt request is generated set rsstp bit to 1 data read in ssrdr register set rsstp bit to 1 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 288 of 453 rej09b0278-0210 16.2.7 scs pin control an d arbitration when setting the ssums bit in the ssmr2 register to 1 (4-wire bus communication mode) and the css1 bit in the ssmr2 register to 1 (functions as scs output pin), set the mss bit in the sscrh register to 1 (operates as the master device) and check the arbitration of the scs pin before starting serial transfer. if clock synchronous serial i/o with chip select detect s that the synchronized internal scs signal is held ?l? in this period, the ce bit in the sssr register is set to 1 (c onflict error) and the mss bit is automa tically set to 0 (operates as a slave device). figure 16.21 shows the arbitration check timing. future transmit operations are not performed while the ce bi t is set to 1. set the ce bit to 0 (no conflict error) before starting transmission. figure 16.21 arbitration check timing data write to sstdr register maximum time of scs internal synchronization during arbitration detection high-impedance scs input internal scs (synchronization) mss bit in sscrh register transfer start ce scs output 0 1 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 289 of 453 rej09b0278-0210 16.2.8 notes on clock synchronous serial i/o with chip select set the iicsel bit in the pmr register to 0 (select clock synchronous serial i/o with chip select function) to use the clock synchronous serial i/o with chip select function. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 290 of 453 rej09b0278-0210 16.3 i 2 c bus interface the i 2 c bus interface is the circuit that performs serial comm unication based on the data transfer format of the philips i 2 c bus. table 16.5 lists the specifications of i 2 c bus interface, figure 16.22 shows a block diagram of i 2 c bus interface, and figure 16.23 shows the external circuit connection ex ample of pins scl and sda. figures 16.24 to 16.30 show the registers associated with the i 2 c bus interface. * i 2 c bus is a trademark of koninklijke philips electronics n. v. note: 1. all sources use one interrupt vector for i 2 c bus interface. table 16.5 specifications of i 2 c bus interface item specification communication formats ?i 2 c bus format - selectable as master/slave device - continuous transmit/receive operation (because the shift register, transmit data register, and receive data register are independent) - start/stop conditions are automatically generated in master mode - automatic loading of acknowledge bit during transmission - bit synchronization/wait function (in master mode, the state of the scl signal is monitored per bit and the timing is synchronized automatically. if the transfer is not possible yet, the scl signal goes ?l? and the interface stands by.) - support for direct drive of pins sc l and sda (n-channel open drain output) ? clock synchronous serial format - continuous transmit/receive operation (because the shift register, transmit data register, and receive data register are independent) i/o pins scl (i/o): serial clock i/o pin sda (i/o): serial data i/o pin transfer clocks ? when the mst bit in the iccr1 register is set to 0 the external clock (input from the scl pin) ? when the mst bit in the iccr1 register is set to 1 the internal clock selected by bits cks0 to cks3 in the iccr1 register (output from the scl pin) receive error detection ? overrun error detection (clock synchronous serial format) indicates an overrun error during reception. when the last bit of the next data item is received while the rdrf bit in the icsr register is set to 1 (data in the icdrr register), the al bit is set to 1. interrupt sources ?i 2 c bus format ................................ 6 sources (1) transmit data empty (including when sl ave address matches), transmit ends, receive data full (including when slav e address matches), arbitration lost, nack detection, and stop condition detection. ? clock synchronous serial format .... 4 sources (1) transmit data empty, transmit ends, receive data full and overrun error select functions ?i 2 c bus format - selectable output level for acknowledge signal during reception ? clock synchronous serial format - msb-first or lsb-first selectable as data transfer direction r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 291 of 453 rej09b0278-0210 figure 16.22 block diagram of i 2 c bus interface iccr1 register data bus iccr2 register icmr register icdrt register sar register icsr register address comparison circuit output control scl interrupt request (txi, tei, rxi, stpi, naki) transfer clock generation circuit icdrs register icdrr register bus state judgment circuit arbitration judgment circuit icier register interrupt generation circuit transmit/receive control circuit noise canceller sda output control f1 noise canceller r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 292 of 453 rej09b0278-0210 figure 16.23 external circuit connect ion example of pins scl and sda scl sda scl input scl output sda input sda output (master) vcc vcc scl sda scl input scl output sda input sda output (slave 1) scl sda scl input scl output sda input sda output scl sda (slave 2) r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 293 of 453 rej09b0278-0210 figure 16.24 iccr1 register iic bus control register 1 symbol address after reset iccr1 00b8h 00h bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. in multimaster operation use the mov instruction to set bits trs and mst. when the first 7 bit after the start condition in slave receive mode match w ith the slave address set in the sar register and the 8th bit is set to 1, the trs bit is set to 1. rw ice iic bus interface enable bit 0 : this module is halted (pins scl and sda are set to port function) 1 : this module is enabled for transfer operations (pins scl and sda are bus drive state) set according to the necessary transfer rate in master mode. refer to table 16.6 transfer rate examples for the transfer rate. this bit is used for maintaining of the setup time in transmit mode of slave mode. the time is 10tcyc w hen the cks3 bit is set to 0 and 20tcyc w hen the cks3 bit is set to 1. (1t cyc = 1/f1(s)) rw trs transmit clock select bits 3 to 0 (1) b3 b2 b1 b0 0 0 0 0 : f1/28 0 0 0 1 : f1/40 0 0 1 0 : f1/48 0 0 1 1 : f1/64 0 1 0 0 : f1/80 0 1 0 1 : f1/100 0 1 1 0 : f1/112 0 1 1 1 : f1/128 1 0 0 0 : f1/56 1 0 0 1 : f1/80 1 0 1 0 : f1/96 1 0 1 1 : f1/128 1 1 0 0 : f1/160 1 1 0 1 : f1/200 1 1 1 0 : f1/224 1 1 1 1 : f1/256 b5 b4 0 0 : slave receive mode (4) 0 1 : slave transmit mode 1 0 : master receive mode 1 1 : master transmit mode rw mst rw rw transfer/receive select bit (2, 3, 6) cks2 cks3 cks0 cks1 rw rw b1 b7 b6 b5 b4 b3 b2 master/slave select bit (5, 6) in master mode w ith the i 2 c bus format, w hen arbitration is lost, bits mst and trs are set to 0 and the iic enters slave receive mode. when an overrun error occurs in master receive mode of the clock synchronous serial format, the mst bit is set to 0 and the iic enters slave receive mode. b0 rew rite the trs bit betw een transfer frames. rcv d receive disable bit after reading the icdrr register w hile the trs bit is set to 0 0 : maintains the next receive operation 1 : disables the next receive operation rw r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 294 of 453 rej09b0278-0210 figure 16.25 iccr2 register iic bus control register 2 symbol address after reset iccr2 00b9h 01111101b bit symbol bit name function rw notes: 1. 2. 3. 4. scp start/stop condition generation disable bit when w riting to the to bbsy bit, w rite 0 simultaneously. (3) when read, the content is 1. writing 1 is invalid. rw when read 0 : bus is in released state (sda signal changes from ?l? to ?h? w hile scl signal is in ?h? state) 1 : bus is in occupied state (sda signal changes from ?h? to ?l? w hile scl signal is in ?h? state) when w ritten (3) 0 : generates stop condition 1 : generates start condition rw this bit is disabled w hen the clock synchronous serial format is used. this bit is enabled in master mode. when w riting to the bbsy bit, w rite 0 to the scp bit using the mov instruction simultaneously. execute the same w ay w hen the start condition is regenerating. when w riting to the sdao bit, w rite 0 to the sdaop bit using the mov instruction simultaneously. do not w rite during a transfer operation. bbsy bus busy bit (4) sdaop sdao rw when read 0 : sda pin output is held ?l? 1 : sda pin output is held ?h? when w ritten (1,2) 0 : sda pin output is changed to ?l? 1 : sda pin output is changed to high-impedance (?h? output via external pull-up resistor) sda output value control bit sdao w rite protect bit when rew rite to sdao bit, w rite 0 simultaneously. (1) when read, the content is 1. ? (b2) nothing is assigned. if necessary, set to 0. when read, the content is 1. sclo scl monitor flag 0 : scl pin is set to ?l? 1 : scl pin is set to ?h? b7 b6 b5 b4 b0 b3 b2 b1 ? (b0) nothing is assigned. if necessary, set to 0. when read, the content is 1. ? iicrst rw when hang-up occurs due to communication failure during i 2 c bus interface operation, w rite 1, to reset the control block of the i 2 c bus interface w ithout setting ports or initializing registers. ro rw ? iic control part reset bit r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 295 of 453 rej09b0278-0210 figure 16.26 icmr register iic bus mode register symbol address after reset icmr 00bah 00011000b bit symbol bit name function rw msb-f irst/lsb-f irst select bit notes: 1. 2. 3. 4. 5. 6. mls rw rw bc1 bc2 bits counter 2 to 0 i 2 c bus format (remaining transfer bit count w hen read out and data bit count of next transfer w hen w ritten). (1,2) b2 b1 b0 0 0 0 : 9 bits (3) 0 0 1 : 2 bits 0 1 0 : 3 bits 0 1 1 : 4 bits 1 0 0 : 5 bits 1 0 1 : 6 bits 1 1 0 : 7 bits 1 1 1 : 8 bits clock synchronous serial format (w hen read, the remaining transfer bit count and w hen w ritten 000b). b2 b1 b0 0 0 0 : 8 bits 0 0 1 : 1 bit 0 1 0 : 2 bits 0 1 1 : 3 bits 1 0 0 : 4 bits 1 0 1 : 5 bits 1 1 0 : 6 bits 1 1 1 : 7 bits bc0 rw rw 0 bcwp bc w rite protect bit b7 b6 b5 b4 b3 b2 b1 b0 when rew riting bits bc0 to bc2, w rite 0 simultaneously. (2,4) when read, the content is 1. rw the setting value is enabled in master mode of the i 2 c bus format. it is disabled in slave mode of the i 2 c bus format or w hen the clock synchronous serial format is used. 0 : no w ait (transfer data and acknow ledge bit consecutively) 1 : wait (after the clock falls for the final data bit, ?l? period is extended for tw o transfer clocks cycles) set to 0. rw rw 0 : data transfer w ith msb-first (6) 1 : data transfer w ith lsb-first ? (b5) wait set to 0 w hen the i 2 c bus format is used. when w riting to bits bc0 to bc2, w rite 0 to the bcwp bit using the mov instruction. ? (b4) nothing is assigned. if necessary, set to 0. when read, the content is 1. ? rew rite betw een transfer frames. when w riting values other than 000b, w rite w hen the scl signal is ?l?. after data including the acknow ledge bit is transferred, these bits are automatically set to 000b. when the start condition is detected, these bits are automatically set to 000b. do not rew rite w hen the clock s y nchronous serial format is used. reserved bit wait insertion bit (5) r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 296 of 453 rej09b0278-0210 figure 16.27 icier register iic bus interrupt enable register symbol address after reset icier 00bbh 00h bit symbol bit name function rw notes: 1. 2. set the stie bit to 1 (enable stop condition detection interrupt request) w hen the stop bit in the icsr register is set to 0. 0 : disables transmit end interrupt request 1 : enables transmit end interrupt request rw rw an overrun error interrupt request is generated w hen the clock synchronous format is used. tie transmit interrupt enable bit 0 : disables transmit data empty interrupt request 1 : enables transmit data empty interrupt request teie transmit end interrupt enable bit acknow ledge bit judgment select bit 0 : value of receive acknow ledge bit is ignored and continuous transfer is performed. 1 : when receive acknow ledge bit is set to 1, continuous transfer is halted. rw stop condition detection interrupt enable bit 0 : disables stop condition detection interrupt request 1 : enables stop condition detection interrupt request (2) 0 : disables nack receive interrupt request and arbitration lost/overrun error interrupt request 1 : enables nack receive interrupt request and arbitration lost/overrun error interrupt request (1) nack receive interrupt enable bit rie receive interrupt enable bit 0 : disables receive data full and overrun error interrupt request 1 : enables receive data full and overrun error interrupt request (1) rw stie ackbt rw rw ro ackbr rw receive acknow ledge bit 0 : acknow ledge bit received from receive device in transmit mode is set to 0. 1 : acknow ledge bit received from receive device in transmit mode is set to 1. transmit acknow ledge select bit na kie b7 b6 b5 b4 acke 0 : 0 is transmitted as acknow ledge bit in receive mode. 1 : 1 is transmitted as acknow ledge bit in receive mode. b0 b3 b2 b1 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 297 of 453 rej09b0278-0210 figure 16.28 icsr register iic bus status register (7) symbol address after reset icsr 00bch 0000x000b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. 7. b0 the nackf bit is enabled w hen the acke bit in the icier register is set to 1 (w hen the receive acknow ledge bit is set to 1, transfer is halted). tdre transmit data empty (1,6) in the follow ing cases, this flag is set to 1. ? data is transferred from registers icdrt to icdrs and the icdrt register is empty ? when setting the trs bit in the iccr1 register to 1 (transmit mode) ? when generating the start condition (including retransmit) ? when changing from slave receive mode to slave transmit mode rw b3 b2 b1 b7 b6 b5 b4 rw aas al adz tend transmit end (1,6) rw rw general call address recognition flag (1,2) when the general call address is detected, this flag is set to 1. arbitration lost flag/overrun error flag (1) when the i 2 c bus format is used, this flag indicates that arbitration has been lost in master mode. in the follow ing cases, this flag is set to 1. (3) ? when the internal sda signal and sda pin level do not match at the rise of the scl signal in master transmit mode ? when the start condition is detected and the sda pin is held ?h? in master transmit/receive mode this flag indicates an overrun error w hen the clock synchronous format is used. in the follow ing case, this flag is set to 1. ? when the last bit of the next data item is received w hile the rdrf bit is set to 1 slave address recognition flag (1) this flag is set to 1 w hen the first frame follow ing start condition matches bits sva0 to sva6 in the sar register in slave receive mode. (detect the slave address and generate call address) receive data register full (1,5) when the 9th clock cycle of the scl signal in the i 2 c bus format occurs w hile the tdre bit is set to 1, this flag is set to 1. this flag is set to 1 w hen the final bit of the transmit frame is transmitted in the clock synchronous format. no acknow ledge detection flag (1,4) this flag is enabled in slave receive mode of the i 2 c bus format. each bit is set to 0 by reading 1 before w riting 0. na ckf when no acknow ledge is detected from the receive device after transmission, this flag is set to 1 rw rw when receive data is transferred from in registers icdrs to icdrr , this flag is set to 1 when accessing the icsr register continuously, insert one or more nop instructions betw een the instructions to access it. stop stop condition detection flag (1) when the stop condition is detected after the frame is transferred, this flag is set to 1 rw the rdrf bit is set to 0 w hen reading data from the icdrr register. bits tend and tdre are set to 0 w hen w riting data to the icdrt register. when tw o or more master devices attempt to occupy the bus at nearly the same time, if the i 2 c bus inter f ac e monitors the sda pin and the data w hich the i 2 c bus interface transmits is different, the al flag is set to 1 and the bus is occupied by the another master. rw rdrf r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 298 of 453 rej09b0278-0210 figure 16.29 registers sar, icdrt, icdrr, and icdrs slave address register symbol address after reset sar 00bdh 00h bit symbol bit name function rw b7 b6 b0 b1 b5 b3 b2 b4 rw format select bit 0 : i 2 c bus format 1 : clock synchronous serial format rw fs sva2 sva0 rw sva3 sva1 slave address 6 to 0 set an address different from that of the other slave devices w hich are connected to the i 2 c bus. when the 7 high-order bits of the first frame transmitted after the starting condition match bits sva0 to sva6 in slave mode of the i 2 c bus format, the mcu operates as a slave device. rw rw rw sva6 sva5 sva4 rw rw iic bus transmit data registe r symbol address after reset icdrt 00beh ffh rw b0 rw function store transmit data when it is detected that the icdrs register is empty, the stored transmit data item is transferred to the icdrs register and data transmission starts. when the next transmit data item is w ritten to the icdrt register during transmission of the data in the icdrs register, continuous transmit is enabled. when the mls bit in the icmr register is set to 1 (data transferred lsb-first) and after the data is w ritten to the icdrt register, the msb-lsb inverted data is read. b7 b6 b5 b4 b3 b2 b1 iic bus receive data register symbol address after reset icdrr 00bfh ffh rw store receive data when the icdrs register receives 1 byte of data, the receive data is transferred to the icdrr register and the next receive operation is enabled. ro function b0 b7 b6 b5 b4 b3 b2 b1 iic bus shift register symbol icdrs rw this register is used to transmit and receive data. the transmit data is transferred from registers icrdt to the icdrs and data is transmitted from the sda pin w hen transmitting. after 1 byte of data is received, data is transferred from registers icdrs to icdrr w hile receiving. ? function b3 b2 b1 b0 b7 b6 b5 b4 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 299 of 453 rej09b0278-0210 figure 16.30 pmr register port mode registe r symbol address after reset pmr 00f8h 00h bit symbol bit name function rw int1 _ ____ pin select bit note: 1. the uart1 pins can be selected by using bits u1pinsel, txd1sel and txd1en, and bits uart1sel1 and uart1sel0 in the pinsr1 register. iicsel ssu / i 2 c bus pin sw itch bit 0 : selects ssu function 1 : selects i 2 c bus function rw txd1en txd1/rxd1 select bit (1) 0 : rxd1 1 : txd1 rw txd1sel port/txd1 pin sw itch bit (1) 0 : programmable i/o port 1 : txd1 rw u1 pinsel txd1 pin sw itch bit (1) 0 : p0_0 1 : p3_6, p3_7 rw ssisel ssi pin select bit 0 : p3_3 1 : p1_6 rw int1sel 0 : p1_5, p1_7 1 : p3_6 rw ? (b2-b1) ? nothing is assigned. if necessary, set to 0. when read, the content is 0. b0 b3 b2 b1 b7 b6 b5 b4 pinsr1 regis ter ua rt1sel1, ua rt1sel0 bit u1pinsel bit txd1sel bit txd1en bit p3_7(txd1) 1 p3_7(rxd1) 0 p0_0(txd1) 0 1 p3_7(txd1) 1 p4_5(rxd1) p3_6(txd1) 1 p3_6(rxd1) 0 p0_0(txd1) 0 1 : 0 or 1 10b pmr register pin function 00b 01b 1 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 300 of 453 rej09b0278-0210 16.3.1 transfer clock when the mst bit in the iccr1 register is set to 0, the transfer clock is the external clock input from the scl pin. when the mst bit in the iccr1 register is set to 1, the transfer clock is the internal clock selected by bits cks0 to cks3 in the iccr1 register and the transfer clock is outp ut from the scl pin. table 16.6 lists the transfer rate examples. table 16.6 transfer rate examples iccr1 register transfer clock transfer rate cks3 cks2 cks1 cks0 f1 = 5 mhz f1 = 8 mhz f1 = 10 mhz f1 = 16 mhz f1 = 20 mhz 0 0 0 0 f1/28 179 khz 286 khz 357 khz 571 khz 714 khz 1 f1/40 125 khz 200 khz 250 khz 400 khz 500 khz 1 0 f1/48 104 khz 167 khz 208 khz 333 khz 417 khz 1 f1/64 78.1 khz 125 khz 156 khz 250 khz 313 khz 1 0 0 f1/80 62.5 khz 100 khz 125 khz 200 khz 250 khz 1 f1/100 50.0 khz 80.0 khz 100 khz 160 khz 200 khz 1 0 f1/112 44.6 khz 71.4 khz 89.3 khz 143 khz 179 khz 1 f1/128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 1 0 0 0 f1/56 89.3 khz 143 khz 179 khz 286 khz 357 khz 1 f1/80 62.5 khz 100 khz 125 khz 200 khz 250 khz 1 0 f1/96 52.1 khz 83.3 khz 104 khz 167 khz 208 khz 1 f1/128 39.1 khz 62.5 khz 78.1 khz 125 khz 156 khz 1 0 0 f1/160 31.3 khz 50.0 khz 62.5 khz 100 khz 125 khz 1 f1/200 25.0 khz 40.0 khz 50.0 khz 80.0 khz 100 khz 1 0 f1/224 22.3 khz 35.7 khz 44.6 khz 71.4 khz 89.3 khz 1 f1/256 19.5 khz 31.3 khz 39.1 khz 62.5 khz 78.1 khz r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 301 of 453 rej09b0278-0210 16.3.2 interrupt requests the i 2 c bus interface has six interr upt requests when the i 2 c bus format is used and four interrupt requests when the clock synchronous serial format is used. table 16.7 lists the interrupt requests of i 2 c bus interface. since these interrupt requests are allocated at the i 2 c bus interface interrupt vector table, determining the source bit by bit is necessary. stie, nakie, rie, teie, tie: bits in icier register al, stop, nackf, rdrf, tend, tdre: bits in icsr register when the generation conditions list ed in table 16.7 are met, an i 2 c bus interface interrupt request is generated. set the interrupt generation conditions to 0 by the i 2 c bus interface interrupt routin e. however, bits tdre and tend are automatically set to 0 by writing transmit data to the icdrt register and the rdrf bit is automatically set to 0 by reading the icdrr register. wh en writing transmit data to the icdrt register, the tdre bit is set to 0. when data is transferred from re gisters icdrt to icdrs, the tdre bit is set to 1 and by further setting the tdre bit to 0, 1 additional byte may be transmitted. set the stie bit to 1 (enable stop condition detecti on interrupt request) when the stop bit is set to 0. table 16.7 interrupt requests of i 2 c bus interface interrupt request generation condition format i 2 c bus clock synchronous serial transmit data empty txi tie = 1 and tdre = 1 enabled enabled transmit ends tei teie = 1 and tend = 1 enabled enabled receive data full rxi rie = 1 and rdrf = 1 enabled enabled stop condition detection stpi stie = 1 and stop = 1 enabled disabled nack detection naki nakie = 1 and al = 1 (or nakie = 1 and nackf = 1) enabled disabled arbitration lost/overrun error enabled enabled r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 302 of 453 rej09b0278-0210 16.3.3 i 2 c bus interface mode 16.3.3.1 i 2 c bus format setting the fs bit in the sar register to 0 enable communication in i 2 c bus format. figure 16.31 shows the i 2 c bus format and bus timing. the 1st frame following the start condition consists of 8 bits. figure 16.31 i 2 c bus format and bus timing s r/w a data a a/a p 1 7 1 1 n 1 1 1 1 m (a) i 2 c bus format (fs = 0) transfer bit count (n = 1 to 8) transfer frame count (m = from 1) s r/w a data a/a p 1 7 1 1 n1 1 1 1 m1 (b) i 2 c bus format (when start condition is retransmitted, fs = 0) upper: transfer bit count (n1, n2 = 1 to 8) lower: transfer frame count (m1, m2 = 1 or more) sla sla a/a 1 s 1 r/w a data 7 1 1 n2 sla 1 m2 sda scl s sla r/w a data a data a p 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 (1) i 2 c bus format (2) i 2 c bus timing explanation of symbols s : start condition the master device changes the sda signal from ?h? to ?l? while the scl signal is held ?h?. sla : slave address r/w : indicates the direction of data transmit/receive data is transmitted from the slave device to the master device when r/w value is 1 and from the master device to the slave devi ce when r/w value is 0. a : acknowledge the receive device sets the sda signal to ?l?. data : transmit / receive data p : stop condition the master device changes the sda signal from ?l? to ?h? while the scl signal is held ?h?. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 303 of 453 rej09b0278-0210 16.3.3.2 master transmit operation in master transmit mode, the master device outputs th e transmit clock and data, and the slave device returns an acknowledge signal. figures 16.32 and 16.33 show the operatin g timing in master transmit mode (i 2 c bus interface mode). the transmit procedure and operation in ma ster transmit mode are as follows. (1) set the stop bit in the icsr register to 0 to rese t it. then set the ice bit in the iccr1 register to 1 (transfer operation enabled). then set bits wait a nd mls in the icmr register and set bits cks0 to cks3 in the iccr1 register (initial setting). (2) read the bbsy bit in the iccr2 regi ster to confirm that the bus is free. set bits trs and mst in the iccr1 register to master transmit mode. the start conditi on is generated by writing 1 to the bbsy bit and 0 to the scp bit by the mov instruction. (3) after confirming that the tdre bit in the icsr regi ster is set to 1 (data is transferred from registers icdrt to icdrs), write transmit data to the icdr t register (data in which a slave address and r/w are indicated in the 1st byte). at this time, the tdre bit is automatically set to 0, data is transferred from registers icdrt to icdrs, an d the tdre bit is set to 1 again. (4) when transmission of 1 byte of data is completed while the tdre bit is set to 1, the tend bit in the icsr register is set to 1 at the rise of the 9th transmit clock pulse. read the ackbr bit in the icier register, and confirm that the slave is selected. write the 2nd byte of data to the icdrt register. since the slave device is not acknowledged when the ackbr bit is set to 1, generate the stop condition. the stop condition is generated by the writing 0 to the bbsy bit and 0 to the scp bit by the mov instruction. the scl signal is held ?l? until data is available and the stop condition is generated. (5) write the transmit data after the 2nd byte to the icdrt register every time the tdre bit is set to 1. (6) when writing the number of bytes to be transmitte d to the icdrt register, wait until the tend bit is set to 1 while the tdre bit is set to 1. or wait for nack (the nackf bit in the icsr register is set to 1) from the receive device while the acke bit in the icier register is set to 1 (when the receive acknowledge bit is set to 1, transf er is halted). then generate the stop condition before setting bits tend and nackf to 0. (7) when the stop bit in the icsr register is set to 1, return to slave receive mode. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 304 of 453 rej09b0278-0210 figure 16.32 operating timing in master transmit mode (i 2 c bus interface mode) (1) figure 16.33 operating timing in master transmit mode (i 2 c bus interface mode) (2) sda (master output) scl (master output) 12 89 67 45 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 12 sda (slave output) tdre bit in icsr register 1 0 tend bit in icsr register 1 0 icdrt register icdrs register r/w slave address address + r/w processing by program (2) instruction of start condition generation (3) data write to icdrt register (1st byte) a (4) data write to icdrt register (2nd byte) (5) data write to icdrt register (3rd byte) data 2 address + r/w data 1 data 1 sda (master output) scl (master output) 12 89 67 45 3 b7 b6 b5 b4 b3 b2 b1 b0 sda (slave output) tdre bit in icsr register 1 0 tend bit in icsr register 1 0 icdrt register icdrs register data n processing by program (6) generate stop condition and set tend bit to 0 (3) data write to icdrt register a/a (7) set to slave receive mode 9 a data n r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 305 of 453 rej09b0278-0210 16.3.3.3 master receive operation in master receive mode, the master device outputs the r eceive clock, receives data from the slave device, and returns an acknowledge signal. figures 16.34 an d 16.35 show the operating timi ng in master receive mode (i 2 c bus interface mode). the receive procedure and operation in master receive mode are shown below. (1) after setting the tend bit in th e icsr register to 0, switch fr om master transmit mode to master receive mode by setting the trs bit in the iccr1 register to 0. also, set the tdre bit in the icsr register to 0. (2) when performing the dummy read of the icdrr regi ster and starting the recei ve operation, the receive clock is output in synchronization with the internal clock and data is received. the master device outputs the level set by the ackbt bit in the icier register to the sda pin at the rising edge of the 9th clock cycle of the receive clock. (3) the 1-frame data receive is completed and the rdrf bit in the icsr register is set to 1 at the rise of the 9th clock cycle. at this time, when reading the ic drr register, the received data can be read and the rdrf bit is set to 0 simultaneously. (4) continuous receive operation is enabled by reading the icdrr register every time the rdrf bit is set to 1. if the 8th clock cycle falls after the icdrr regi ster is read by another process while the rdrf bit is set to 1, the scl signal is fixed ?l? until the icdrr register is read. (5) if the next frame is the last receive frame and the rcvd bit in the iccr1 regist er is set to 1 (disables the next receive operation) before reading the icdrr register, stop co ndition generation is enabled after the next receive operation. (6) when the rdrf bit is set to 1 at the rise of the 9th clock cycle of the receive clock, generate the stop condition. (7) when the stop bit in the icsr register is set to 1, read the icdrr register and set the rcvd bit to 0 (maintain the following receive operation). (8) return to slave receive mode. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 306 of 453 rej09b0278-0210 figure 16.34 operating timing in master receive mode (i 2 c bus interface mode) (1) sda (master output) scl (master output) 1 8 967 45 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 12 sda (slave output) tdre bit in icsr register 1 0 tend bit in icsr register 1 0 icdrr register icdrs register data 1 processing by program (1) set tend and trs bits to 0 before setting tdre bits to 0 a (2) read icdrr register data 1 9 trs bit in iccr1 register 1 0 rdrf bit in icsr register 1 0 a (3) read icdrr register master transmit mode master receive mode r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 307 of 453 rej09b0278-0210 figure 16.35 operating timing in master receive mode (i 2 c bus interface mode) (2) sda (master output) scl (master output) 12 89 67 45 3 b7 b6 b5 b4 b3 b2 b1 b0 sda (slave output) 1 0 rcvd bit in iccr1 register 1 0 icdrr register icdrs register data n-1 processing by program (6) stop condition generation a/a (8) set to slave receive mode 9 a data n rdrf bit in icsr register data n data n-1 (5) set rcvd bit to 1 before reading icdrr register (7) read icdrr register before setting rcvd bit to 0 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 308 of 453 rej09b0278-0210 16.3.3.4 slave transmit operation in slave transmit mode, the slave device outputs the tran smit data while the master device outputs the receive clock and returns an acknowledge signal. figures 16.36 and 16.37 show the operating timing in slave transmit mode (i 2 c bus interface mode). the transmit procedure and operation in slave transmit mode are as follows. (1) set the ice bit in the iccr1 register to 1 (trans fer operation enabled). set bits wait and mls in the icmr register and bits cks0 to cks3 in the iccr1 register (initial setting). set bits trs and mst in the iccr1 register to 0 and wait until the slave address matches in slave receive mode. (2) when the slave address matches at the 1st frame after detecting the start condition, the slave device outputs the level set by the ackbt bit in the icier register to the sda pin at the rise of the 9th clock cycle. at this time, if the 8th bit of data (r/w ) is 1, bits trs and tdre in the icsr register are set to 1, and the mode is switched to slave transmit mode automatically. continuous transmission is enabled by writing transmit data to the icdrt register every time the tdre bit is set to 1. (3) when the tdre bit in the icdrt register is set to 1 after writing the last transmit data to the icdrt register, wait until the tend bit in the icsr register is set to 1 while the tdre bit is set to 1. when the tend bit is set to 1, set the tend bit to 0. (4) the scl signal is released by setting the trs bit to 0 and performing a dummy read of the icdrr register to end the process. (5) set the tdre bit to 0. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 309 of 453 rej09b0278-0210 figure 16.36 operating timing in slave transmit mode (i 2 c bus interface mode) (1) sda (master output) scl (master output) 1 8 967 45 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 12 sda (slave output) tdre bit in icsr register 1 0 tend bit in icsr register 1 0 icdrr register icdrs register data 1 processing by program a data 2 9 trs bit in iccr1 register 1 0 a slave transmit mode slave receive mode scl (slave output) icdrt register data 1 (1) data write to icdrt register (data 1) (2) data write to icdrt register (data 2) data 2 (2) data write to icdrt register (data 3) data 3 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 310 of 453 rej09b0278-0210 figure 16.37 operating timing in slave transmit mode (i 2 c bus interface mode) (2) sda (slave output) scl (master output) 12 89 67 45 3 b7 b6 b5 b4 b3 b2 b1 b0 sda (master output) tdre bit in icsr register 1 0 tend bit in icsr register 1 0 icdrt register icdrs register data n processing by program (3) set the tend bit to 0 a 9 a data n slave receive mode slave transmit mode trs bit in iccr1 register 1 0 icdrr register (4) dummy read of icdrr register after setting trs bit to 0 (5) set tdre bit to 0 scl (slave output) r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 311 of 453 rej09b0278-0210 16.3.3.5 slave receive operation in slave receive mode, the master de vice outputs the transmit clock and data, and the slave device returns an acknowledge signal. figures 16.38 an d 16.39 show the operating timing in slave receive mode (i 2 c bus interface mode). the receive procedure and operation in slave receive mode are as follows. (1) set the ice bit in the iccr1 register to 1 (trans fer operation enabled). set bits wait and mls in the icmr register and bits cks0 to cks3 in the iccr1 register (initial setting). set bits trs and mst in the iccr1 register to 0 and wait until the slave address matches in slave receive mode. (2) when the slave address matches at the 1st frame after detecting the start condition, the slave device outputs the level set in the ackbt bit in the icier re gister to the sda pin at the rise of the 9th clock cycle. since the rdrf bit in the icsr register is set to 1 simultaneously, perform the dummy-read (the read data is unnecessary because it indicates the slave address and r/w ). (3) read the icdrr register every time the rdrf bit is set to 1. if the 8th cl ock cycle falls while the rdrf bit is set to 1, the scl signal is fixed ?l? until the icdrr register is read. the setting change of the acknowledge signal returned to the master devi ce before reading the icdrr register takes affect from the following transfer frame. (4) reading the last byte is performed by r eading the icdrr register in like manner. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 312 of 453 rej09b0278-0210 figure 16.38 operating timing in slave receive mode (i 2 c bus interface mode) (1) figure 16.39 operating timing in slave receive mode (i 2 c bus interface mode) (2) sda (master output) scl (master output) 1 8 967 45 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 12 sda (slave output) icdrr register icdrs register data 1 processing by program a (2) dummy read of icdrr register data 1 9 rdrf bit in icsr register 1 0 a (2) read icdrr register scl (slave output) data 2 sda (master output) scl (master output) 8 967 45 3 b7 b6 b5 b4 b3 b2 b1 b0 12 sda (slave output) icdrr register icdrs register data 1 processing by program a (3) read icdrr register data 1 9 rdrf bit in icsr register 1 0 a (4) read icdrr register scl (slave output) data 2 (3) set ackbt bit to 1 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 313 of 453 rej09b0278-0210 16.3.4 clock synchronous serial mode 16.3.4.1 clock synchronous serial format set the fs bit in the sar register to 1 to use the clock synchronous serial format for communication. figure 16.40 shows the transfer format of clock synchronous serial format. when the mst bit in the iccr1 register is set to 1, the transfer clock is output from the scl pin, and when the mst bit is set to 0, the external clock is input. the transfer data is output between su ccessive falling edges of the scl clock, and data is determined at the rising edge of the scl clock. msb-first or lsb-first can be selected as the order of the data transfer by setting the mls bit in the icmr register. the sda output leve l can be changed by the sdao bit in the iccr2 register during transfer standby. figure 16.40 transfer format of clock synchronous serial format scl b0 sda b1 b2 b3 b4 b5 b6 b7 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 314 of 453 rej09b0278-0210 16.3.4.2 transmit operation in transmit mode, transmit data is output from the sda pin in synchronization with the falling edge of the transfer clock. the transfer clock is output when the mst bit in the iccr1 register is set to 1 and input when the mst bit is set to 0. figure 16.41 shows the operating timing in tr ansmit mode (clock synchronous serial mode). the transmit procedure and operation in transmit mode are as follows. (1) set the ice bit in the iccr1 register to 1 (transfe r operation enabled). set bits cks0 to cks3 in the iccr1 register and set the mst bit (initial setting). (2) the tdre bit in the icsr register is set to 1 by selecting transmit mode after setting the trs bit in the iccr1 register to 1. (3) data is transferred from registers icdrt to ic drs and the tdre bit is automatically set to 1 by writing transmit data to the icdrt register after c onfirming that the tdre bit is set to 1. continuous transmission is enabled by writing data to the icdrt register every time the tdre bit is set to 1. when switching from transmit to receive mode, set the trs bit to 0 while the tdre bit is set to 1. figure 16.41 operating timing in transmit mode (clock synchronous serial mode) sda (output) scl 8 7 b7 b1 b0 12 icdrt register icdrs register processing by program 17 81 b6 b7 b0 b6 b0 tdre bit in icsr register 1 0 trs bit in iccr1 register 1 0 data 1 data 2 data 3 data 1 data 2 data 3 (2) set trs bit to 1 (3) data write to icdrt register (3) data write to icdrt register (3) data write to icdrt register (3) data write to icdrt register r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 315 of 453 rej09b0278-0210 16.3.4.3 receive operation in receive mode, data is latched at the rising edge of the transfer clock. the transf er clock is output when the mst bit in the iccr1 register is set to 1 and input when the mst bit is set to 0. figure 16.42 shows the operating timing in re ceive mode (clock synchronous serial mode). the receive procedure and operation in receive mode are as follows. (1) set the ice bit in the iccr1 register to 1 (transfe r operation enabled). set bits cks0 to cks3 in the iccr1 register and set the mst bit (initial setting). (2) the output of the receive clock starts when the mst bit is set to 1 while the transfer clock is being output. (3) data is transferred from register s icdrs to icdrr and the rdrf bit in the icsr register is set to 1, when the receive operation is completed. since the next byte of data is enabled when the mst bit is set to 1, the clock is output conti nuously. continuous receive is enab led by reading the icdrr register every time the rdrf bit is set to 1. an overrun is de tected at the rise of the 8th clock cycle while the rdrf bit is set to 1, and th e al bit in the icsr register is set to 1. at this time, the last receive data is retained in the icdrr register. (4) when the mst bit is set to 1, set the rcvd bit in the iccr1 register to 1 (disables the next receive operation) and read the icdrr regi ster. the scl signal is fixed ?h ? after reception of the following byte of data is completed. figure 16.42 operating timing in receive mode (clock synchronous serial mode) sda (input) scl 8 7 b7 b1 b0 12 icdrr register icdrs register processing by program 17 81 b6 b7 b0 b6 b0 rdrf bit in icsr register 1 0 mst bit in iccr1 register 1 0 data 1 data 2 (2) set mst bit to 1 (when transfer clock is output) (3) read icdrr register 2 trs bit in iccr1 register 1 0 data 2 data 3 data 1 (3) read icdrr register r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 316 of 453 rej09b0278-0210 16.3.5 noise canceller the states of pins scl and sda ar e routed through the noise canceller before being latched internally. figure 16.43 shows a block diagram of noise canceller. the noise canceller consists of two cascaded latch and ma tch detector circuits. when the scl pin input signal (or sda pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next circuit. when they do not match, the former value is retained. figure 16.43 block diagram of noise canceller c dq latch c dq latch match detection circuit scl or sda input signal internal scl or sda signal f1 (sampling clock) period of f1 f1 (sampling clock) r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 317 of 453 rej09b0278-0210 16.3.6 bit synchronization circuit when setting the i 2 c bus interface to master mode , the high-level period may b ecome shorter in the following two cases: ? if the scl signal is driven l level by a slave device ? if the rise speed of the scl signal is reduced by a load (load capacity or pull-up resistor) on the scl line. therefore, the scl signal is monitored and communication is synchronized bit by bit. figure 16.44 shows the timing of bit synchronization circuit and table 16.8 lists the time between changing scl signal from ?l? output to high-impedance and monitoring of scl signal. figure 16.44 timing of bit synchronization circuit 1tcyc = 1/f1(s) table 16.8 time between changing scl signal from ?l? output to high-impedance and monitoring of scl signal iccr1 register time for monitoring scl cks3 cks2 0 0 7.5tcyc 1 19.5tcyc 1017.5tcyc 1 41.5tcyc vih reference clock of scl monitor timing scl internal scl r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 318 of 453 rej09b0278-0210 16.3.7 examples of register setting figures 16.45 to 16.48 show examples of register setting when using i 2 c bus interface. figure 16.45 example of register setting in master transmit mode (i 2 c bus interface mode) start initial setting read bbsy bit in iccr2 register end bbsy = 0 ? write transmit data to icdrt register transmit mode ? master receive mode tend = 1 ? no yes yes no (1) judge the state of the scl and sda lines (2) set to master transmit mode (3) generate the start condition (4) set the transmit data of the 1st byte (slave address + r/w) (5) wait for 1 byte to be transmitted (6) judge the ackbr bit from the specified slave device (7) set the transmit data after 2nd byte (except the last byte) (8) wait until the icrdt register is empty (9) set the transmit data of the last byte (10) wait for end of transmission of the last byte (11) set the tend bit to 0 (12) set the stop bit to 0 (13) generate the stop condition (14) wait until the stop condition is generated (15) set to slave receive mode set the tdre bit to 0 iccr1 register trs bit 1 mst bit 1 iccr2 register scp bit 0 bbsy bit 1 read tend bit in icsr register no read ackbr bit in icier register yes ackbr = 0 ? write transmit data to icdrt register tdre = 1 ? read tdre bit in icsr register last byte ? write transmit data to icdrt register tend = 1 ? read tend bit in icsr register icsr register tend bit 0 icsr register stop bit 0 iccr2 register scp bit 0 bbsy bit 0 read stop bit in icsr register stop = 1 ? iccr1 register trs bit 0 mst bit 0 icsr register tdre bit 0 no yes no yes no yes no yes no yes (1) (2) (3) (4) (5) (6) (7) (8) (12) (10) (13) (14) (11) (9) (15) ? set the stop bit in the icsr register to 0 ? set the iicsel bit in the pmr register to 1 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 319 of 453 rej09b0278-0210 figure 16.46 example of register setting in master receive mode (i 2 c bus interface mode) end rdrf = 1 ? master receive mode no yes (1) set the tend bit to 0 and set to master receive mode. set the tdre bit to 0 (1,2) (2) set the ackbt bit to the transmit device (1) (3) dummy read the icdrr register (1) (4) wait for 1 byte to be received (5) judge (last receive - 1) (6) read the receive data (7) set the ackbt bit of the last byte and set to disable continuous receive operation (rcvd = 1) (2) (8) read the receive data of (last byte - 1) (9) wait until the last byte is received (10) set the stop bit to 0 (11) generate the stop condition (12) wait until the stop condition is generated (13) read the receive data of the last byte (14) set the rcvd bit to 0 (15) set to slave receive mode iccr1 register trs bit 0 dummy read in icdrr register read rdrf bit in icsr register last receive - 1 ? icsr register tend bit 0 icsr register stop bit 0 iccr2 register scp bit 0 bbsy bit 0 read stop bit in icsr register stop = 1 ? icsr register tdre bit 0 no (1) (2) (3) (4) (5) (6) (7) (8) (12) (10) (13) (14) (11) (9) (15) icier register ackbt bit 0 no yes read icdrr register icier register ackbt bit 1 iccr1 register rcvd bit 1 read icdrr register read rdrf bit in icsr register rdrf = 1 ? read icdrr register iccr1 register rcvd bit 0 iccr1 register mst bit 0 no yes yes notes: 1. do not generate the interrupt while processing steps (1) to (3). 2. when receiving 1 byte, skip steps (2) to (6) after (1) and jump to process of step (7). processing of step (8) is dummy read of the icdrr register. r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 320 of 453 rej09b0278-0210 figure 16.47 example of register setting in slave transmit mode (i 2 c bus interface mode) end write transmit data to icdrt register slave transmit mode no yes (1) set the aas bit to 0 (2) set the transmit data (except the last byte) (3) wait until the icrdt register is empty (4) set the transmit data of the last byte (5) wait until the last byte is transmitted (6) set the tend bit to 0 (7) set to slave receive mode (8) dummy read the icdrr register to release the scl signal (9) set the tdre bit to 0 tdre = 1 ? read tdre bit in icsr register last byte ? write transmit data to icdrt register tend = 1 ? read tend bit in icsr register icsr register tend bit 0 icsr register aas bit 0 iccr1 register trs bit 0 icsr register tdre bit 0 no yes no yes (1) (2) (3) (4) (5) (6) (7) (8) (9) dummy read in icdrr register r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 321 of 453 rej09b0278-0210 figure 16.48 example of register se tting in slave receive mode (i 2 c bus interface mode) end rdrf = 1 ? slave receive mode no yes (1) set the aas bit to 0 (1) (2) set the ackbt bit to the transmit device (3) dummy read the icdrr register (4) wait until 1 byte is received (5) judge (last receive - 1) (6) read the receive data (7) set the ackbt bit of the last byte (1) (8) read the receive data of (last byte - 1) (9) wait until the last byte is received (10) read the receive data of the last byte dummy read icdrr register read rdrf bit in icsr register last receive - 1 ? (1) (2) (3) (4) (5) (6) (7) (8) (10) (9) icier register ackbt bit 0 no yes read icdrr register icier register ackbt bit 1 read icdrr register read rdrf bit in icsr register rdrf = 1 ? read icdrr register no yes note: 1. when receiving 1 byte, skip steps (2) to (6) after (1) and jump to processing step (7). processing step (8) is dummy read of the icdrr register. icsr register aas bit 0 r8c/26 group, r8c/27 group 16. cl ock synchronous serial interface rev.2.10 sep 26, 2008 page 322 of 453 rej09b0278-0210 16.3.8 notes on i 2 c bus interface set the iicsel bit in the pmr register to 1 (select i 2 c bus interface function) to use the i 2 c bus interface. 16.3.8.1 multimaster operation the following actions must be performed to use the i 2 c bus interface in multimaster operation. ? transfer rate set the transfer rate by 1/1.8 or faster than the fastes t rate of the other masters. for example, if the fastest transfer rate of the other masters is set to 400 kbps, the i 2 c-bus transfer rate in this mcu should be set to 223 kbps (= 400/1.18) or more. ? bits mst and trs in the iccr1 register setting (a) use the mov instruction to set bits mst and trs. (b) when arbitration is lost, confirm the contents of b its mst and trs. if the contents are other than the mst bit set to 0 and the trs bit set to 0 (slave recei ve mode), set the mst bit to 0 and the trs bit to 0 again. 16.3.8.2 master receive mode either of the following actions must be performed to use the i 2 c bus interface in ma ster receive mode. (a) in master receive mode while the rdrf bit in the icsr register is set to 1, read the icdrr register before the rising edge of the 8th clock. (b) in master receive mode, set the rcvd bit in th e iccr1 register to 1 (disables the next receive operation) to perform 1-byte communications. r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 323 of 453 rej09b0278-0210 17. hardware lin the hardware lin performs lin communication in cooperation with timer ra and uart0. 17.1 features the hardware lin has the features listed below. figure 17.1 shows a block diagram of hardware lin. master mode ? generates synch break ? detects bus collision slave mode ? detects synch break ? measures synch field ? controls synch break and synch field signal inputs to uart0 ? detects bus collision note: 1. the wakeup function is detected by int1. figure 17.1 block diagram of hardware lin timer ra uart0 interrupt control circuit bus collision detection circuit synch field control circuit rxd0 input control circuit rxd0 pin txd0 pin lstart bit sbe bit line bit timer ra interrupt tiosel = 0 hardware lin tiosel = 1 rxd data timer ra underflow signal bcie, sbie, and sfie bits uart0 transfer clock uart0 te bit timer ra output pulse uart0 txd data mst bit line, mst, sbe, lstart, bcie, sbie, sfie: bits in lincr register tiosel: bit in traioc register te: bit in u0c1 register r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 324 of 453 rej09b0278-0210 17.2 input/output pins the pin configuration of the hardware lin is listed in table 17.1. table 17.1 pin configuration name abbreviation input/output function receive data input rxd0 input receive data input pin of the hardware lin transmit data output txd0 output transmit data output pin of the hardware lin r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 325 of 453 rej09b0278-0210 17.3 register configuration the hardware lin contains the registers listed below. these registers are detailed in figures 17.2 and 17.3. ? lin control register (lincr) ? lin status register (linst) figure 17.2 lincr register lin control register symbol address after reset lincr 0106h 00h bit symbol bit name function rw notes: 1. 2. 3. lin operation start bit 0 : causes lin to stop 1 : causes lin to start operating (3) rw lin operation mode setting bit (2) 0 : slave mode (synch break detection circuit actuated) 1 : master mode (timer ra output or?ed w ith txd0) 0 : disables synch field measurement- completed interrupt 1 : enables synch field measurement- completed interrupt sfie synch field measurement- completed interrupt enable bit b7 b6 b5 b4 b3 b2 b1 b0 0 : rxd0 input enabled 1 : rxd0 input disabled when this bit is set to 1, timer ra input is enabled and rxd0 input is disabled. when read, the content is 0. rw rw ro rw rw rxd0 input status flag synch break detection start bit (1) synch break detection interrupt enable bit bus collision detection interrupt enable bit 0 : disables synch break detection interrupt 1 : enables synch break detection interrupt 0 : disables bus collision detection interrupt 1 : enables bus co llision detection interrupt sbie bcie rxdsf lstart inputs to timer ra and uart0 are prohibited immediately after this bit is set to 1. (refer to figure 17.5 example of header field transm ission flow chart (1) and figure 17.9 exam ple of header field reception flow chart (2) .) before changing lin operation modes, temporarily stop the lin operation (line bit = 0). sbe after setting the lstart bit, confirm that the rxdsf flag is set to 1 before synch break input starts. 0 : unmasked after synch break is detected 1 : unmasked after synch field measurement is completed rw rxd0 input unmasking timing select bit (effective only in slave mode) mst rw line r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 326 of 453 rej09b0278-0210 figure 17.3 linst register lin status register symbol address after reset linst 0107h 00h bit symbol bit name function rw ? (b7-b6) ? 1 show s synch field measurement completed. sfdct synch field measurement- completed flag ro rw rw rw ro b3 b2 b1 b0 b7 b6 b5 b4 ro sbdct bit clear bit bcdct bit clear bit 1 show s synch break detected or synch break generation completed. 1 show s bus collision detected. when this bit is set to 1, the sfdct bit is set to 0. when read, the content is 0. when this bit is set to 1, the sbdct bit is set to 0. when read, the content is 0. nothing is assigned. if necessary, set to 0. when read, the content is 0. b2clr sbdct bcdct b0clr b1clr when this bit is set to 1, the bcdct bit is set to 0. when read, the content is 0. synch break detection flag bus collision detection f lag sfdct bit clear bit r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 327 of 453 rej09b0278-0210 17.4 functional description 17.4.1 master mode figure 17.4 shows typical operation of the hardware lin when transmitting a header field in master mode. figures 17.5 and 17.6 show an example of header field tran smission flowchart. when transmitting a header field, the ha rdware lin operates as described below. (1) when the tstart bit in the tracr register for timer ra is set by writing 1 in software, the hardware lin outputs ?l? level from the txd0 pin for the peri od that is set in registers trapre and tra for timer ra. (2) when timer ra underflo ws upon reaching the terminal count, th e hardware lin reverses the output of the txd0 pin and sets the sbdct flag in the linst re gister to 1. furthermore, if the sbie bit in the lincr register is set to 1, it generates a timer ra interrupt. (3) the hardware lin transmits 55h via uart0. (4) the hardware lin transmits an id field via uart0 after it finishes sending 55h. (5) the hardware lin performs communication for a re sponse field after it finish es sending the id field. figure 17.4 typical operation when sending a header field txd0 pin synch break 1 0 sbdct flag in the linst register 1 0 ir bit in the traic register 1 0 synch field identifier (1) (2) (3) (4) (5) set by writing 1 to the b1clr bit in the linst register cleared to 0 upon acceptance of interrupt request or by a program shown above is the case where line = 1, mst = 1, sbie = 1 r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 328 of 453 rej09b0278-0210 figure 17.5 example of header fi eld transmission flowchart (1) timer ra set to timer mode bits tmod0 to tmod2 in tramr register 000b timer ra set the pulse output level from low to start tedgsel bit in traioc register 1 timer ra set the int1/traio pin to p1_5 tiosel bit in traioc register 1 timer ra set the count source (f1, f2, f8, foco) bits tck0 to tck2 in tramr register timer ra set the synch break width trapre register tra register hardware lin set to master mode mst bit in lincr register 1 hardware lin set the lin operation to start line bit in lincr register 1 hardware lin set the register to enable interrupts (bus collision detection , synch break detection, synch field measurement) bits bcie, sbie, sfie in lincr register hardware lin clear the status flags (bus collision detection, synch break detection, synch field measurement) bits b2clr, b1clr, b0 clr in linst register 1 set the count source and registers tra and trapre as suitable for the synch break period. during master mode, the synch field measurement- completed interrupt cannot be used. a for the hardware lin function, set the tiosel bit in the traioc register to 1. uart0 set to transmit/receive mode (transfer data length : 8 bits, internal clock, 1 stop bit, parity disabled) u0mr register uart0 set the brg count source (f1, f8, f32) bits clk0 to clk2 in u0c0 register uart0 set the bit rate u0brg register hardware lin set the lin operation to stop lincr register line bit 0 set the brg count source and u0brg register as appropriate for the bit rate. r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 329 of 453 rej09b0278-0210 figure 17.6 example of header fi eld transmission flowchart (2) timer ra set the timer to start counting tstart bit in tracr register 1 timer ra read the count status flag tcstf flag in tracr register hardware lin read the synch break detection flag sbdct flag in linst register timer ra set the timer to stop counting tstart bit in tracr register 0 timer ra read the count status flag tcstf flag in tracr register uart0 communication via uart0 te bit in u0c1 register 1 u0tb register 0055h the timer ra interrupt may be used to terminate generation of synch break. one to two cycles of the cpu clock are required after synch break generation completes before the sbdct flag is set to 1. transmit the id field. a tcstf = 1 ? sbdct = 1 ? yes tcstf = 0 ? yes uart0 communication via uart0 u0tb register id field no yes no no if registers trapre and tra for timer ra do not need to be read or the register settings do not need to be changed after writing 0 to the tstart bit, the procedure for reading tcstf flag = 0 can be omitted. zero to one cycle of the timer ra count source is required after timer ra stops counting before the tcstf flag is set to 0. transmit the synch field. after timer ra synch break is generated, the timer should be made to stop counting. if registers trapre and tra for timer ra do not need to be read or the register settings do not need to be changed after writing 1 to the tstart bit, the procedure for reading tcstf flag = 1 can be omitted. zero to one cycle of the timer ra count source is required after timer ra starts counting before the tcstf flag is set to 1. timer ra generates synch break. r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 330 of 453 rej09b0278-0210 17.4.2 slave mode figure 17.7 shows typical operation of the hardware lin when receiving a header field in slave mode. figure 17.8 through figure 17.10 show an example of header field transmission flowchart. when receiving a header field, the hard ware lin operates as described below. (1) synch break detection is enabled by writing 1 to th e lstart bit in the lincr register of the hardware lin. (2) when ?l? level is input for a duration equal to or greater than the period set in timer ra, the hardware lin detects it as synch break. at this time, the sbdct flag in the linst register is set to 1. furthermore, if the sbie bit in the lincr register is set to 1, the hardware lin generates a timer ra interrupt. then it goes to synch field measurement. (3) the hardware lin receives a synch fi eld (55h). at this time, it measur es the period of the start bit and bits 0 to 6 by using timer ra. in this case, it is poss ible to select whether to input the synch field signal to rxd0 of uart0 by setting the sbe bit in the lincr register accordingly. (4) the hardware lin sets the sfdct flag in the linst register to 1 when it fi nishes measuring the synch field. furthermore, if the sfie bit in the lincr regi ster is set to 1, it generates a timer ra interrupt. (5) after it finishes measuring the synch field, calcula te a transfer rate from the count value of timer ra and set to uart0 and registers trapre and tra of timer ra again. then it receives an id field via uart0. (6) the hardware lin performs comm unication for a response field after it finishes receiving the id field. figure 17.7 typical operation when receiving a header field rxd0 pin synch break 1 0 rxd0 input for uart0 1 0 rxdsf flag in the lincr register 1 0 synch field identifier (2) (3) (5) (6) shown above is the case where line = 1, mst = 0, sbe = 1, sbie = 1, sfie = 1 (4) (1) sbdct flag in the linst register 1 0 sfdct flag in the linst register 1 0 ir bit in the traic register 1 0 set by writing 1 to the b0clr bit in the linst register cleared to 0 when synch field measurement finishes measure this period set by writing 1 to the b1clr bit in the linst register cleared to 0 upon acceptance of interrupt request or by a program set by writing 1 to the lstart bit in the lincr register r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 331 of 453 rej09b0278-0210 figure 17.8 example of header field reception flowchart (1) set the count source and registers tra and trapre as appropriate for the synch break period. select the timing at which to unmask the rxd0 input for uart0. if the rxd0 input is chosen to be unmasked after detection of synch break, the synch field signal is also input to uart0. a for the hardware lin function, set the tiosel bit in the traioc register to 1. timer ra set to pulse width measurement mode bits tmod0 to tmod2 in the tramr register 011b timer ra set the pulse width measurement level low tedgsel bit in the traioc register 0 timer ra set the int1/traio pin to p1_5 tiosel bit in the traioc register 1 timer ra set the count source (f1, f2, f8, foco) bits tck0 to tck2 in the tramr register timer ra set the synch break width trapre register tra register hardware lin set the lin operation to stop line bit in the lincr register 0 hardware lin set to slave mode mst bit in the lincr register 0 hardware lin set the rxd0 input unmasking timing (after synch break detection, or after synch field measurement) sbe bit in the lincr register hardware lin set the register to enable interrupts (bus collision detection, synch break detection, synch field measurement) bits bcie, sbie, sfie in the lincr register hardware lin set the lin operation to start line bit in the lincr register 1 r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 332 of 453 rej09b0278-0210 figure 17.9 example of header field reception flowchart (2) timer ra set to start a pulse width measurement tstart bit in the tracr register 1 timer ra read the count status flag tcstf flag in the tracr register hardware lin set to start synch break detection lstart bit in the lincr register 1 hardware lin read the rxd0 input status flag rxdsf flag in the lincr register a tcstf = 1 ? yes rxdsf = 1 ? yes no no timer ra waits until the timer starts counting. hardware lin clear the status flags (bus collision detec tion, synch break detection, synch field measurement) bits b2clr, b1clr, b0clr in the linst register 1 hardware lin read the synch break detection flag sbdct flag in the linst register sbdct = 1 ? yes no b hardware lin detects a synch break. the interrupt of the timer ra may be used. when synch break is detected, timer ra is reloaded with the initially set count value. even if the duration of the input ?l? level is shorter than the set period, timer ra is reloaded with the initially set count value and waits until the next ?l? level is input. one to two cycles of the cpu clock are required after synch break detection before the sbdct flag is set to 1. when the sbe bit in the lincr register is set to 0 (unmasked after synch break is detected), timer ra can be used in timer mode after the sbdct flag in the linst register is set to 1 and the rxdsf flag is set to 0. hardware lin wait s until the rxd0 input for uart0 is masked. do not apply ?l? level to the rxd pin until the rxdsf flag reads 1 after writing 1 to the lstart bit. this is because the signal applied during this time is input directly to uart0. one to two cycles of the cpu clock and zero to one cycle of the timer ra count source are required after the lstart bit is set to 1 before the rxdsf flag is set to 1. after this, input to timer ra and uart0 is enabled. zero to one cycle of the timer ra count source is required after timer ra starts counting before the tcstf flag is set to 1. r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 333 of 453 rej09b0278-0210 figure 17.10 example of header field reception flowchart (3) hardware lin read the synch field measurement- completed flag sfdct flag in the linst register uart0 set the uart0 communication rate u0brg register communication via uart0 (the sbdct flag is set when the timer ra counter underflows upon reaching the terminal count.) b sfdct = 1 ? yes uart0 communication via uart0 clock asynchronous serial interface (uart) mode transmit id field no hardware lin measures the synch field. the interrupt of timer ra may be used (the sbdct flag is set when the timer ra counter underflows upon reaching the terminal count). when the sbe bit in the lincr register is set to 1 (unmasked after synch field measurement is completed), timer ra may be used in timer mode after the sfdct bit in the linst register is set to 1. set a communication rate based on the synch field measurement result. yes timer ra set the synch break width again trapre register tra register r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 334 of 453 rej09b0278-0210 17.4.3 bus collision detection function the bus collision detection function can be used when uart0 is enabled for transmission (te bit in the u0c1 register = 1). figure 17.11 shows the typical operatio n when a bus collision is detected. figure 17.11 typical operation when a bus collision is detected txd0 pin 1 0 rxd0 pin 1 0 transfer clock 1 0 line bit in the lincr register 1 0 te bit in the u0c1 register 1 0 bcdct flag in the linst register 1 0 ir bit in the traic register 1 0 cleared to 0 upon acceptance of interrupt request or by a program set by writing 1 to the b2clr bit in the linst register set to 1 by a program set to 1 by a program r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 335 of 453 rej09b0278-0210 17.4.4 hardware li n end processing figure 17.12 shows an example of hardware lin communication completion flowchart. use the following timing for hardware lin end processing: ? if the hardware bus collision detection function is used perform hardware lin end processing af ter checksum transmission completes. ? if the bus collision detection function is not used perform hardware lin end processing after head er field transmission and reception complete. figure 17.12 example of hardware lin communication completion flowchart hardware lin clear the status flags (bus collision detection, synch break detection, synch field measurement) bits b2clr, b1clr, b0clr in the linst register 0 timer ra read the count status flag tcstf flag in tracr register uart0 complete transmission via uart0 when the bus collision detection function is not used, end processing for the uart0 transmission is not required. tcstf = 0 ? yes no set the timer to stop counting. zero to one cycle of the timer ra count source is required after timer ra starts counting before the tcstf flag is set to 1. after clearing hardware lin status flag, stop the hardware lin operation. timer ra set the timer to stop counting tstart bit in tracr register 0 hardware lin set the lin operation to stop line bit in the lincr register 0 r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 336 of 453 rej09b0278-0210 17.5 interrupt requests there are four interrupt requests th at are generated by the hardware li n: synch break detection, synch break generation completed, synch field measurement complete d, and bus collision detect ion. these interrupts are shared with timer ra. table 17.2 lists the interrupt requests of hardware lin. table 17.2 interrupt requests of hardware lin interrupt request status flag cause of interrupt synch break detection sbdct generated when timer ra has underflowed after measuring the ?l? level duration of rxd0 input, or when a ?l? level is input for a duration longer than the synch break period during communication. synch break generation completed generated when ?l? level output to txd0 for the duration set by timer ra completes. synch field measurement completed sfdct generated when measurement for 6 bits of the synch field by timer ra is completed. bus collision detection bcdct ge nerated when the rxd0 input and txd0 output values differed at data latch timing while uart0 is enabled for transmission. r8c/26 group, r8c/27 group 17. hardware lin rev.2.10 sep 26, 2008 page 337 of 453 rej09b0278-0210 17.6 notes on hardware lin for the time-out processing of the head er and response fields, use another timer to measure the duration of time with a synch break detection interrupt as the starting point. r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 338 of 453 rej09b0278-0210 18. a/d converter the a/d converter consists of one 10- bit successive approximation a/d converter circuit with a capacitive coupling amplifier. the analog input shares pins p0_0 to p0_7, and p1_0 to p1_3. therefore, when us ing these pins, ensure that the corresponding port direction bits are set to 0 (input mode). when not using the a/d converter, set the vcut bit in the adcon1 register to 0 (vref unconnected) so that no current will flow from the vref pin into the resistor ladder. this helps to reduce the power consumption of the chip. the result of a/d conversion is stored in the ad register. table 18.1 lists the performance of a/d converter. figure 18.1 shows a block diagram of a/d converter. figures 18.2 and 18.3 show the a/d converter-related registers. notes: 1. the analog input voltage does not depend on use of a sample and hold function. when the analog input voltage is over the reference voltage, the a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. 2. when 2.7 v avcc 5.5 v, the frequency of ad must be 10 mhz or below. when 2.2 v avcc < 2.7 v, the frequency of ad must be 5 mhz or below. without a sample and hold function, the ad frequency should be 250 khz or above. with a sample and hold function, the ad frequency should be 1 mhz or above. 3. in repeat mode, only 8-bit mode can be used. table 18.1 performance of a/d converter item performance a/d conversion method successive approximat ion (with capacitive coupling amplifier) analog input voltage (1) 0 v to avcc operating clock ad (2) 4.2 v avcc 5.5 v f1, f2, f4, foco-f 2.2 v avcc < 4.2 v f2, f4, foco-f (n, d version) 2.7 v avcc < 4.2 v f2, f4, foco-f (j, k version) resolution 8 bits or 10 bits selectable absolute accuracy avcc = vref = 5 v, ad = 10 mhz ? 8-bit resolution 2 lsb ? 10-bit resolution 3 lsb avcc = vref = 3.3 v, ad = 10 mhz ? 8-bit resolution 2 lsb ? 10-bit resolution 5 lsb avcc = vref = 2.2 v, ad = 5 mhz ? 8-bit resolution 2 lsb ? 10-bit resolution 5 lsb operating mode one-shot and repeat (3) analog input pin 12 pins (an0 to an11) a/d conversion start condition software trigger set the adst bit in the adcon0 regi ster to 1 (a/d conversion starts) conversion rate per pin ? without sample and hold function 8-bit resolution: 49 ad cycles, 10-bit resolution: 59 ad cycles ? with sample and hold function 8-bit resolution: 28 ad cycles, 10-bit resolution: 33 ad cycles r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 339 of 453 rej09b0278-0210 figure 18.1 block diagram of a/d converter comparator avss data bus resistor ladder vcut = 0 vcut = 1 vref successive conversion register ad register adcon0 vcom vin p1_0/an8 p1_1/an9 p1_2/an10 p1_3/an11 adgsel0 = 1 ch0 to ch2, adgsel0, cks0: bits in adcon0 register cks1, vcut: bits in adcon1 register adgsel0 = 0 p0_7/an0 ch2 to ch0 = 000b p0_6/an1 p0_5/an2 p0_4/an3 p0_3/an4 p0_2/an5 p0_1/an6 p0_0/an7 decoder cks0 = 1 cks1 = 1 cks1 = 0 ad a/d conversion rate selection cks0 = 0 f2 f4 foco-f f1 cks0 = 1 cks0 = 0 ch2 to ch0 = 001b ch2 to ch0 = 010b ch2 to ch0 = 011b ch2 to ch0 = 100b ch2 to ch0 = 101b ch2 to ch0 = 110b ch2 to ch0 = 111b ch2 to ch0 = 100b ch2 to ch0 = 101b ch2 to ch0 = 110b ch2 to ch0 = 111b r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 340 of 453 rej09b0278-0210 figure 18.2 adcon0 register a/d control register 0 (1) symbol address after reset adcon0 00d6h 00h bit symbol bit name function rw notes: 1. 2. 3. 4. adgsel0 = 0 adgsel0 = 1 an0 an1 an2 an3 an4 an8 an5 an9 an6 an10 an7 an11 b0 b3 b2 b1 md a/d operating mode select bit (2) b7 b6 b5 b4 0 ch2 rw analog input pin select bits (note 4) 0 : one-shot mode 1 : repeat mode rw rw adgsel0 rw a/d input group select bit (4) 0 : selects port p0 group (an0 to an7) 1 : selects port p1 group (an8 to an11) ch1 rw ch0 ? (b5) reserved bit set to 0. rw adst a/d conversion start flag 0 : stops a/d conversion 1 : starts a/d conversion rw set ?ad frequency to 10 mhz or below . the analog input pin can be selected according to a combination of bits ch0 to ch2 and the adgsel0 bit. cks0 frequency select bit 0 [when cks1 in adcon1 register = 0] 0 : select f4 1 : select f2 [when cks1 in adcon1 register = 1] 0 : select f1 (3) 1 : select foco-f rw if the adcon0 register is rew ritten during a/d conversion, the conversion result is undefined. when changing a/d operation mode, set the analog input pin again. ch2 to ch0 000b do not set. 001b 010b 011b 100b 101b 110b 111b r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 341 of 453 rej09b0278-0210 figure 18.3 registers adcon1, adcon2, and ad a/d control register 1 (1) symbol address after reset adcon1 00d7h 00h bit symbol bit name function rw notes: 1. 2. 3. when the vcut bit is set to 1 (connected) from 0 (not connected), w ait for 1 s or more before starting a/d conversion. b3 b2 vcut b1 b0 00 refer to the description of the cks0 bit in the adcon0 register function. b7 b6 b5 b4 ? (b2-b0) 00 0 if the adcon1 register is rew ritten during a/d conversion, the conversion result is undefined. cks1 rw rw rw ? (b6-b7) reserved bits vref connect bit (3) 0 : vref not connected 1 : vref connected set the bits bit to 0 (8-bit mode) in repeat mode. reserved bits set to 0. 8/10-bit mode select bit (2) 0 : 8-bit mode 1 : 10-bit mode rw set to 0. frequency select bit 1 bits rw a/d control register 2 (1) symbol address after reset adcon2 00d4h 00h bit symbol bit name function rw note: 1. 0 : without sample and hold 1 : with sample and hold rw if the adcon2 register is rew ritten during a/d conversion, the conversion result is undefined. smp a/d conversion method select bit nothing is assigned. if necessary, set to 0. when read, the content is 0. ? (b7-b4) ? ? (b3-b1) rw reserved bits set to 0. b7 b6 b5 b4 0 b3 b2 b1 b0 00 a /d registe r symbol address after reset ad 00c1h-00c0h undefined function ro when bits bit in adcon1 register is set to 1 (10-bit mode). when bits bit in adcon1 register is set to 0 (8-bit mode). 8 low -order bits in a/d conversion result a/d conversion result rw ro nothing is assigned. if necessary, set to 0. when read, the content is 0. ? 2 high-order bits in a/d conversion result when read, the content is undefined. b0 b7 ( b8) b0 ( b15) b7 r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 342 of 453 rej09b0278-0210 18.1 one-shot mode in one-shot mode, the input voltage of one selected pin is a/d converted once. table 18.2 lists the specifications of one-shot mode. fi gure 18.4 shows the adcon0 register in one-shot mode and figure 18.5 shows the adcon1 register in one-shot mode. table 18.2 specifications of one-shot mode item specification function the input voltage of one pin selected by bits ch2 to ch0 and adgsel0 is a/d converted once start condition set the adst bit to 1 (a/d conversion starts) stop condition ? a/d conversion completes (adst bit is set to 0) ? set the adst bit to 0 interrupt request generation timing a/d conversion completes input pin select one of an0 to an11 reading of a/d conversion result read ad register r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 343 of 453 rej09b0278-0210 figure 18.4 adcon0 register in one-shot mode a/d control register 0 (1) symbol address after reset adcon0 00d6h 00h bit symbol bit name function rw notes: 1. 2. 3. 4. adgsel0 = 0 adgsel0 = 1 an0 an1 an2 an3 an4 an8 an5 an9 an6 an10 an7 an11 100b 101b 110b 111b ch2 to ch0 000b do not set. 001b 010b 011b b0 0 b3 b2 b1 md a/d operating mode select bit (2) b7 b6 b5 b4 0 ch2 rw analog input pin select bits (note 4) 0 : one-shot mode rw rw adgsel0 rw a/d input group select bit (4) 0 : selects port p0 group (an0 to an7) 1 : selects port p1 group (an8 to an11) ch1 rw ch0 ? (b5) reserved bit set to 0. rw adst a/d conversion start flag 0 : stops a/d conversion 1 : starts a/d conversion rw set ?ad frequency to 10 mhz or below . the analog input pin can be selected according to a combination of bits ch0 to ch2 and the adgsel0 bit. cks0 frequency select bit 0 [when cks1 in adcon1 register = 0] 0 : select f4 1 : select f2 [when cks1 in adcon1 register = 1] 0 : select f1 (3) 1 : select foco-f rw if the adcon0 register is rew ritten during a/d conversion, the conversion result is undefined. after changing the a/d operating mode, select the analog input pin again. r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 344 of 453 rej09b0278-0210 figure 18.5 adcon1 register in one-shot mode a/d control register 1 (1) symbol address after reset adcon1 00d7h 00h bit symbol bit name function rw notes: 1. 2. when the vcut bit is set to 1 (connected) from 0 (not connected), w ait for 1 s or more before starting a/d conversion. b3 b2 vcut b1 b0 00 refer to the description of the cks0 bit in the adcon0 register function. b7 b6 b5 b4 ? (b2-b0) 001 0 bits rw if the adcon1 register is rew ritten during a/d conversion, the conversion result is undefined. cks1 rw rw rw ? (b6-b7) reserved bits vref connect bit (2) rw set to 0. frequency select bit 1 1 : vref connected reserved bits set to 0. 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 345 of 453 rej09b0278-0210 18.2 repeat mode in repeat mode, the input voltage of one selected pin is a/d converted repeatedly. table 18.3 lists the specifications of repeat mode. figure 18.6 shows the ad con0 register in repeat mode and figure 18.7 shows the adcon1 register in repeat mode. table 18.3 specifications of repeat mode item specification function the input voltage of one pin select ed by bits ch2 to ch0 and adgsel0 is a/d converted repeatedly start conditions set the adst bit to 1 (a/d conversion starts) stop condition set the adst bit to 0 interrupt request generation timing not generated input pin select one of an0 to an11 reading of result of a/d converter read ad register r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 346 of 453 rej09b0278-0210 figure 18.6 adcon0 register in repeat mode a/d control register 0 (1) symbol address after reset adcon0 00d6h 00h bit symbol bit name function rw notes: 1. 2. 3. 4. adgsel0 = 0 adgsel0 = 1 an0 an1 an2 an3 an4 an8 an5 an9 an6 an10 an7 an11 100b 101b 110b 111b ch2 to ch0 000b do not set. 001b 010b 011b set ?ad frequency to 10 mhz or below . the analog input pin can be selected according to a combination of bits ch0 to ch2 and the adgsel0 bit. cks0 frequency select bit 0 [when cks1 in adcon1 register = 0] 0 : select f4 1 : select f2 [when cks1 in adcon1 register = 1] 0 : select f1 (3) 1 : do not set. rw if the adcon0 register is rew ritten during a/d conversion, the conversion result is undefined. after changing a/d operation mode, select the analog input pin again. adst a/d conversion start flag 0 : stops a/d conversion 1 : starts a/d conversion rw ? (b5) reserved bit set to 0. rw 1 : repeat mode rw rw adgsel0 rw a/d input group select bit (4) 0 : selects port p0 group (an0 to an7) 1 : selects port p1 group (an8 to an11) ch1 rw ch0 ch2 rw analog input pin select bits (note 4) md a/d operating mode select bit (2) b7 b6 b5 b4 01 b3 b2 b1 b0 r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 347 of 453 rej09b0278-0210 figure 18.7 adcon1 register in repeat mode a/d control register 1 (1) symbol address after reset adcon1 00d7h 00h bit symbol bit name function rw notes: 1. 2. 3. when the vcut bit is set to 1 (connected) from 0 (not connected), w ait for 1 s or more before starting a/d conversion. b3 b2 vcut b1 b0 0 00 refer to the description of the cks0 bit in the adcon0 register function. b7 b6 b5 b4 ? (b2-b0) 001 0 bits rw if the adcon1 register is rew ritten during a/d conversion, the conversion result is undefined. cks1 rw rw rw ? (b6-b7) reserved bits set the bits bit to 0 (8-bit mode) in repeat mode. vref connect bit (3) 1 : vref connected reserved bits set to 0. 8/10-bit mode select bit (2) 0 : 8-bit mode rw set to 0. frequency select bit 1 r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 348 of 453 rej09b0278-0210 18.3 sample and hold when the smp bit in the adcon2 register is set to 1 (sample and hold function enabled), the a/d conversion rate per pin increases. the sample and hold function is available in all operating modes. start a/d conversion after selecting whether the samp le and hold circuit is to be used or not. figure 18.8 shows a timing diagram of a/d conversion. figure 18.8 timing diagram of a/d conversion 18.4 a/d conversion cycles figure 18.9 shows the a/d conversion cycles. figure 18.9 a/d conversion cycles sampling time 4? ad cycles sample and hold disabled conversion time of 1st bit 2nd bit comparison time sampling time 2.5? ad cycles comparison time sampling time 2.5? ad cycles comparison time * repeat until conversion ends sampling time 4? ad cycles sample and hold enabled conversion time of 1st bit 2nd bit comparison time comparison time comparison time * repeat until conversion ends comparison time a/d conversion mode without sample & hold without sample & hold with sample & hold with sample & hold 8 bits 10 bits 8 bits 10 bits conversion time comparison time comparison time end process sampling time end process conversion time at the 1st bit sampling time conversion time at the 2nd bit and the follows 49 ad 4 ad 2.0 ad 2.5 ad 2.5 ad 8.0 ad 59 ad 4 ad 2.0 ad 2.5 ad 2.5 ad 8.0 ad 28 ad 4 ad 2.5 ad 0.0 ad 2.5 ad 4.0 ad 33 ad 4 ad 2.5 ad 0.0 ad 2.5 ad 4.0 ad r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 349 of 453 rej09b0278-0210 18.5 internal equivalent circuit of analog input figure 18.10 shows the internal equivalent circuit of analog input. figure 18.10 internal equivalent circuit of analog input vcc parasitic diode chopper-type amplifier a/d successive conversion register comparison voltage b1 b2 b0 vcc vss an0 vss i=12 an11 vref avss vref comparison reference voltage (vref) generator sw1 sw2 avcc amp sw3 avss vin sw4 sw5 sw1 parasitic diode on resistor approx. 2k ? wiring resistor approx. 0.2k ? on resistor approx. 0.6k ? on resistor approx. 2k ? wiring resistor approx. 0.2k ? i ladder-type switches a/d control register 0 on resistor approx. 0.6k f analog input voltage sampling control signal on resistor approx. 5k ? c = approx.1.5pf a/d conversion interrupt request sw1 conducts only on the ports selected for analog input. sw2 and sw3 are open when a/d conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left. sw4 conducts only when a/d conversion is not in progress. sw5 conducts when compare operation is in progress. control signal for sw2 control signal for sw3 sampling compari son connect to connect to connect to connect to note: 1. use only as a standard for designing this data. mass production may cause some changes in device characteristics. i ladder-type wiring resistors resistor ladder reference control signal b4 r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 350 of 453 rej09b0278-0210 18.6 output impedance of sensor under a/d conversion to carry out a/d conversion properly, charging the internal capacitor c shown in figure 18.11 has to be completed within a specified period of time. t (sampling time) as the specified time. let ou tput impedance of sensor equivalent circuit be r0, internal resistance of microcom puter be r, precision (error) of the a/d converter be x, and the resolution of a/d converter be y (y is 1 024 in the 10-bit mode, and 256 in the 8-bit mode). vc is generally and when t = t, hence, figure 18.11 shows the analog input pin and external sens or equivalent circuit. when the difference between vin and vc becomes 0.1lsb, we find impedance r0 wh en voltage between pins vc changes from 0 to vin- (0.1/1024) vin in time t. (0.1/1024) means that a/d precisi on drop due to insufficient capacitor charge is held to 0.1lsb at time of a/d conversion in the 10-bit mode. actu al error however is the value of absolute precision added to 0.1lsb. when f(xin) = 10 mhz, t = 0.25 s in the a/d conversion mode without sample and hold. output impedance r0 for sufficiently charging capacitor c within time t is determined as follows. t = 0.25 s, r = 2.8 k ? , c = 6.0 pf, x = 0.1, and y = 1024. hence, thus, the allowable output impedance of the sensor equivale nt circuit, making the precision (error) 0.1lsb or less, is approximately 1.7 k ? . maximum. figure 18.11 analog input pin and exte rnal sensor equivalent circuit r0 r (2.8 k ? ) c (6.0 pf) vin vc mcu sensor equivalent circuit note: 1. the capacity of the terminal is assumed to be 4.5 pf. r0 t c x y --- - ln ? ------------------- ?r ? = 1 cr0 r + () -------------------------- ?t x y --- - ln = e 1 cr0 r + () -------------------------- t ? x y --- - = vc vin x y --- - vin vin 1 x y --- - ? ?? ?? = ? = vc vin 1 e 1 cr0 r + () -------------------------- ? t ? ?? ?? ?? = r0 0.25 10 6 ? 6.0 10 12 ? 0.1 1024 ----------- - ln ? -------------------------------------------------- - ? =2.8 3 10 ? 1.7 3 10 r8c/26 group, r8c/27 group 18. a/d converter rev.2.10 sep 26, 2008 page 351 of 453 rej09b0278-0210 18.7 notes on a/d converter ? write to each bit (other th an bit 6) in the adcon0 register, each b it in the adcon1 register, or the smp bit in the adcon2 register when a/d conversi on is stopped (before a trigger occurs). when the vcut bit in the adcon1 register is changed from 0 (vref no t connected) to 1 (vref connected), wait for at least 1 s before starting the a/d conversion. ? after changing the a/d operating mode, select an analog input pin again. ? when using the one-shot mode, ensure that a/d conversion is completed before reading the ad register. the ir bit in the adic register or the adst bit in the ad con0 register can be used to determine whether a/d conversion is completed. ? when using the repeat mode, select the fr equency of the a/d converter operating clock ad or more for the cpu clock during a/d conversion. ? if the adst bit in the adcon0 register is set to 0 (a /d conversion stops) by a program and a/d conversion is forcibly terminated duri ng an a/d conversion operatio n, the conversion result of the a/d converter will be undefined. if the adst bit is set to 0 by a program, do not use the value of the ad register. ? connect 0.1 f capacitor between the p4_2 /vref pin and avss pin. ? do not enter stop mode during a/d conversion. ? do not enter wait mode when the cm02 bit in the cm0 re gister is set to 1 (peripheral function clock stops in wait mode) during a/d conversion. r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 352 of 453 rej09b0278-0210 19. flash memory 19.1 overview in the flash memory, rewrite operations to the flash memory can be pe rformed in three modes : cpu rewrite, standard serial i/o, and parallel i/o. table 19.1 lists the flash memory performance (refer to tables 1.1 and 1.2 functions and specifications for items not listed in table 19.1 ). notes: 1. definition of programming and erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be er ased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1-kbyte block, and then the block is erased, the programming/ erasure endurance still stands at one. when performing 1 00 or more rewrites, the actual erase count can be reduced by executing programming operations in such a way that all blank areas are used before performing an erase operation. avoid rewriting only particular blocks and try to average out th e programming and erasure endurance of the blocks. it is also advisable to retain data on t he erasure endurance of eac h block and limit the number of erase operations to a certain number. 2. blocks a and b are implement ed only in th e r8c/27 group. 3. to perform programming and erasure, use vcc = 2. 7 to 5.5 v as the supply voltage. do not perform programming and erasure at less than 2.7 v. table 19.1 flash me mory performance item specification flash memory operating mode 3 modes (cpu rewrite, standard serial i/o, and parallel i/o) division of erase block refer to figures 19.1 and 19.2 programming method byte unit erase method block erase programming and erasure control method (3) program and erase control by software command rewrite control method rewrite control for blocks 0 and 1 by fmr02 bit in fmr0 register rewrite control for block 0 by fmr15 bit and block 1 by fmr16 bit in fmr1 register number of commands 5 commands programming and erasure endurance (1) blocks 0 and 1 (program rom) r8c/26 group: 100 times; r8c/27 group: 1,000 times blocks a and b (data flash) (2) 10,000 times id code check function standard serial i/o mode supported rom code protect parallel i/o mode supported table 19.2 flash memory rewrite modes flash memory rewrite mode cpu rewrite mode standard serial i/o mode parallel i/o mode function user rom area is rewritten by executing software commands from the cpu. ew0 mode: rewritable in the ram ew1 mode: rewritable in flash memory user rom area is rewritten by a dedicated serial programmer. user rom area is rewritten by a dedicated parallel programmer. areas which can be rewritten user rom area user ro m area user rom area operating mode single chip mode boot mode parallel i/o mode rom programmer none serial programmer parallel programmer r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 353 of 453 rej09b0278-0210 19.2 memory map the flash memory contains a user rom area and a boot rom area (reserved area). figure 19.1 shows the flash memory block diagram for r8c/26 group. figure 19.2 shows a flash memory block diagram for r8c/27 group. the user rom area of the r8c/27 group contains an area (program rom) which stores mcu operating programs and blocks a and b (data fl ash) each 1 kbyte in size. the user rom area is divided into several blocks. the us er rom area can be rewritten in cpu rewrite mode and standard serial i/o and parallel i/o modes. when rewriting blocks 0 and 1 in cpu rewrite mode, se t the fmr02 bit in the fmr0 register to 1 (rewrite enabled). when the fmr15 bit in the fm r1 register is set to 0 (rewrite enabled), block 0 is rewritable. when the fmr16 bit is set to 0 (rewrite enabled), block 1 is rewritable. the rewrite control program for standard serial i/o mode is stored in the boot rom area before shipment. the boot rom area and the user rom area share the same address, but have separate memory areas. figure 19.1 flash memory block diagram for r8c/26 group boot rom area (reserved area) (2) user rom area user rom area 8 kbytes 0e000h 0ffffh 08000h block 0: 16 kbytes (1) 0c000h 0ffffh 24 kbytes rom product block 1: 16 kbytes (1) block 0: 16 kbytes (1) 0bfffh 0c000h 0ffffh 32 kbytes rom product program rom user rom area user rom area block 0: 8 kbytes (1) 0e000h 0ffffh block 0: 16 kbytes (1) 0c000h 0ffffh 16 kbytes rom product program rom 8 kbytes rom product block 1: 8 kbytes (1) 0a000h 0bfffh notes: 1. when the fmr02 bit in the fmr0 register is set to 1 (rewrite enabled) and the fmr15 bit in the fmr1 register is set to 0 (rewrite enabled), block 0 is rewritable. when the fmr16 bit is se t to 0 (rewrite enabled), block 1 is rewritable (only for cpu rewrite mode). 2. this area is for storing the boot program provided by renesas technology. r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 354 of 453 rej09b0278-0210 figure 19.2 flash memory block diagram for r8c/27 group boot rom area (reserved area) (2) 8 kbytes 0e000h 0ffffh user rom area block 0: 16 kbytes (1) 0c000h 0ffffh block b: 1 kbyte block a: 1 kbyte 02400h 02bffh 24 kbytes rom product 08000h block 1: 16 kbytes (1) user rom area block 0: 16 kbytes (1) 0bfffh 0c000h 0ffffh block b: 1 kbyte block a: 1 kbyte 02400h 02bffh 32 kbytes rom product program rom data flash user rom area block 0: 8 kbytes (1) 0e000h 0ffffh user rom area block 0: 16 kbytes (1) 0c000h 0ffffh block b: 1 kbyte block a: 1 kbyte 02400h 02bffh 16 kbytes rom product program rom data flash block b: 1 kbyte block a: 1 kbyte 02400h 02bffh 8 kbytes rom product block 1: 8 kbytes (1) 0a000h 0bfffh notes: 1. when the fmr02 bit in the fmr0 register is set to 1 (rewri te enabled) and the fmr15 bit in the fmr1 register is set to 0 (rewrite enabled), block 0 is rewritable. when the fmr16 bit is se t to 0 (rewrite enabled), block 1 is rewritable (only for cpu rewrite mode). 2. this area is for storing the boot program provided by renesas technology. r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 355 of 453 rej09b0278-0210 19.3 functions to prevent re writing of flash memory standard serial i/o mode ha s an id code check function, and parallel i/o mode has a rom code protect function to prevent the flash memory from being read or rewritten easily. 19.3.1 id code check function this function is used in standard serial i/o mode. unless the flash memory is blank, the id codes sent from the programmer and the id codes written in the flash memory are checked to see if they match. if the id codes do not match, the commands sent from the programmer ar e not acknowledged. the id codes consist of 8 bits of data each, the areas of which, beginning with the first byte, are 00ffdfh, 00ffe3h, 00ffebh, 00ffefh, 00fff3h, 00fff7h, and 00fffbh. write pr ograms in which the id codes are set at these addresses and write them to the flash memory. figure 19.3 address for stored id code 4 bytes address note: 1. the ofs register is assigned to 00ffffh. refer to figure 19.4 ofs register for ofs register details. id1 id2 id3 id4 id5 id6 id7 (note 1) undefined instruction vector overflow vector brk instruction vector address match vector oscillation stop detection/watchdog timer/voltage monitor 1 and voltage monitor 2 vector address break reset vector (reserved) single step vector 00ffdfh to 00ffdch 00ffe3h to 00ffe0h 00ffe7h to 00ffe4h 00ffebh to 00ffe8h 00ffefh to 00ffech 00fff3h to 00fff0h 00fff7h to 00fff4h 00fffbh to 00fff8h 00ffffh to 00fffch r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 356 of 453 rej09b0278-0210 19.3.2 rom code protect function the rom code protect function disables reading or changing the contents of the on-chip flash memory by the ofs register in parallel i/o mode. figure 19.4 shows the ofs register. the rom code protect function is enabled by writing 0 to the romcp1 bit and 1 to the romcr bit. it disables reading or changing the contents of the on-chip flash memory. once rom code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel i/o mode. to disable rom code protect, erase the block including the ofs register with cpu rewrite mode or standard serial i/o mode. figure 19.4 ofs register option function select register (1) symbol address when shipping ofs 0ffffh ffh (3) bit symbol bit name function rw notes: 1. 2. 3. 4. 5. 6. csproini count source protect mode after reset select bit 0 : count source protect mode enabled after reset 1 : count source protect mode disabled after reset rw lvd1on voltage detection 1 circuit start bit (5, 6) 0 : voltage monitor 1 reset enabled after hardw are reset 1 : voltage monitor 1 reset disabled after hardw are reset rw romcp1 rom code protect bit 0 : rom code protect enabled 1 : rom code protect disabled rw romcr rom code protect disabled bit 0 : rom code protect disabled 1 : romcp1 enabled rw ? (b1) rw reserved bit set to 1. wdton rw watchdog timer start select bit 0 : starts w atchdog timer automatically after reset 1 : watchdog timer is inactive after reset 1 1 b7 b6 b5 b4 b3 b2 b1 b0 ? (b4) reserved bit set to 1. rw lvd0on voltage detection 0 circuit start bit (2, 4) 0 : voltage monitor 0 reset enabled after hardw are reset 1 : voltage monitor 0 reset disabled after hardw are reset rw for n, d version only. for j, k version, set the lvd0on bit to 1 (voltage monitor 0 reset disabled after hardw are reset). the lvd1on bit setting is valid only by a hardw are reset. when the pow er-on reset function is used, set the lvd1on bit to 0 (voltage monitor 1 reset enabled after hardw are reset). for j, k version only. for n, d version, set the lvd1on bit to 1 (voltage monitor 1 reset disabled after hardw are reset). the ofs register is on the flash memory. write to the ofs register w ith a program. after w riting is completed, do not w rite additions to the ofs register. if the block including the ofs register is erased, ffh is set to the ofs register. the lvd0on bit setting is valid only by a hardw are reset. to use the pow er-on reset, set the lvd0on bit to 0 (voltage monitor 0 reset enabled after hardw are reset). r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 357 of 453 rej09b0278-0210 19.4 cpu rewrite mode in cpu rewrite mode, the user rom area can be rewr itten by executing software commands from the cpu. therefore, the user rom area can be rewritten directly while the mcu is mounted on a board without using a rom programmer. execute the progra m and block erase commands only to blocks in the user rom area. the flash module has an erase-suspend function when an in terrupt request is generated during an erase operation in cpu rewrite mode. it performs an interrupt process afte r the erase operation is halted temporarily. during erase- suspend, the user rom area can be read by a program. in case an interrupt request is generated during an auto -program operation in cpu rewrite mode, the flash module contains a program-suspend function which performs the interrupt process after the auto-program operation is suspended. during program-suspend, the user rom area can be read by a program. cpu rewrite mode has an erase wr ite 0 mode (ew0 mode) and an erase write 1 mode (ew1 mode). table 19.3 lists the differences between ew0 mode and ew1 mode. note: 1. when the fmr02 bit in the fmr0 register is set to 1 (rewrite enabled), rewriting block 0 is enabled by setting the fmr15 bit in the fmr1 register to 0 (rewrite enabled), and rewriting block 1 is enabled by setting the fmr16 bit to 0 (rewrite enabled). table 19.3 differences between ew0 mode and ew1 mode item ew0 mode ew1 mode operating mode single-chip mode single-chip mode areas in which a rewrite control program can be located user rom area user rom area areas in which a rewrite control program can be executed necessary to transfer to any area other than the flash memory (e.g., ram) before executing executing directly in user rom or ram area possible areas which can be rewritten user rom area user rom area however, blocks which contain a rewrite control program are excluded (1) software command restrictions none ? program and block erase commands cannot be run on any block which contains a rewrite control program ? read status register command cannot be executed modes after program or erase read status register mode read array mode modes after read status register read status register mode do not execute this command cpu status during auto- write and auto-erase operating hold state (i/o ports hold state before the command is executed) flash memory status detection ? read bits fmr00, fmr06, and fmr07 in the fmr0 register by a program ? execute the read status register command and read bits sr7, sr5, and sr4 in the status register. read bits fmr00, fmr06, and fmr07 in the fmr0 register by a program conditions for transition to erase-suspend set bits fmr40 and fmr41 in the fmr4 register to 1 by a program. the fmr40 bit in the fmr4 register is set to 1 and the interrupt request of the enabled maskable interrupt is generated conditions for transitions to program-suspend set bits fmr40 and fmr42 in the fmr4 register to 1 by a program. the fmr40 bit in the fmr4 register is set to 1 and the interrupt request of the enabled maskable interrupt is generated cpu clock 5 mhz or below no restriction (on clock frequency to be used) r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 358 of 453 rej09b0278-0210 19.4.1 ew0 mode the mcu enters cpu rewrite mode and software commands can be acknowledged by setting the fmr01 bit in the fmr0 register to 1 (cpu rewrite mode enabled). in this case, since th e fmr11 bit in the fmr1 register is set to 0, ew0 mode is selected. use software commands to control pr ogram and erase operations. the fmr0 register or the status register can be used to determine when program and erase operations complete. during auto-erasure, set the fmr40 bi t to 1 (erase-suspend enabled) and the fmr41 bit to 1 (request erase- suspend). wait for td(sr-sus) and ensure that the fmr46 bit is set to 1 (read enabled) before accessing the user rom area. the auto-erase operat ion can be restarted by setting the fmr41 bit to 0 (erase restarts). to enter program-suspend during the auto-program operati on, set the fmr40 bit to 1 (suspend enabled) and the fmr42 bit to 1 (request program-suspend). wait for td(s r-sus) and ensure that the fmr46 bit is set to 1 (read enabled) before accessing the user rom area. the auto-program operation can be restarted by setting the fmr42 bit to 0 (program restarts). 19.4.2 ew1 mode the mcu is switched to ew1 mode by setting the fmr11 bit to 1 (ew1 mode) after setting the fmr01 bit to 1 (cpu rewrite mode enabled). the fmr0 register can be used to determine when progra m and erase operations complete. do not execute commands that use the read st atus register in ew1 mode. to enable the erase-suspend function during auto-erasure, ex ecute the block erase co mmand after setting the fmr40 bit to 1 (erase-suspend enabled) . the interrupt to enter erase-suspend should be in interrupt enabled status. after waiting for td(sr-sus) after the bloc k erase command is executed, the interrupt request is acknowledged. when an interrupt request is generated, the fmr41 bit is automatically set to 1 (re quests erase-suspend) and the auto-erase operation suspends. if an auto-erase operati on does not complete (fmr00 bit is 0) after an interrupt process completes, the auto-erase operation restar ts by setting the fmr41 bit to 0 (erasure restarts) to enable the program-suspend function during auto-p rogramming, execute the pr ogram command after setting the fmr40 bit to 1 (suspend enabled). the interrupt to enter program-suspend should be in interrupt enabled status. after waiting for td(sr-sus) after the program command is executed, an interrupt request is acknowledged. when an interrupt request is generated, the fmr42 bit is automatically set to 1 (request program-suspend) and the auto-program oper ation suspends. when the auto-program operation does not complete (fmr00 bit is 0) after the interrupt process completes, the auto-program op eration can be restarted by setting the fmr42 bit to 0 (programming restarts). r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 359 of 453 rej09b0278-0210 figure 19.5 shows the fmr0 register, figure 19.6 sh ows the fmr1 register and figure 19.7 shows the fmr4 register. 19.4.2.1 fmr00 bit this bit indicates the operating status of the flash me mory. the bits value is 0 during programming, erasure (including suspend periods), or erase-suspend mode; otherwise, it is 1. 19.4.2.2 fmr01 bit the mcu is made ready to accept commands by setting the fmr01 bit to 1 (cpu rewrite mode). 19.4.2.3 fmr02 bit rewriting of block 0 and block 1 does not accept program or block erase commands if the fmr02 bit is set to 0 (rewrite disabled). rewriting of block 0 and block 1 is controlled by bits fmr15 and fmr16 if the fmr02 bit is set to 1 (rewrite enabled). 19.4.2.4 fmstp bit this bit is used to initialize the flash memory contro l circuits, and also to reduce the amount of current consumed by the flash memory. access to the flash memory is disabled by setting the fmstp bit to 1. therefore, the fmstp bit must be written to by a program tran sferred to the ram. in the following cases, set the fmstp bit to 1: ? when flash memory access resulted in an error whil e erasing or programming in ew0 mode (fmr00 bit not reset to 1 (ready)) ? to provide lower consumption in high-speed on-chip oscillator mode, low-speed on-chip oscillator mode (xin clock stops), and low-speed clock mode (xin clock stops). figure 19.11 shows the process to reduce power consum ption in high-speed on-c hip oscillator mode, low- speed on-chip oscillator mode (xin clock stops) an d low-speed clock mode (xin clock stops). handle according to this flowchart. note that when going to stop or wait mode while the cpu re write mode is disabled, the fmr0 register does not need to be set because the power for the flash memory is automatically turned off and is turned back on again after returning from stop or wait mode. 19.4.2.5 fmr06 bit this is a read-only bit indicating the status of an auto-program operation. the bit is set to 1 when a program error occurs; otherwise, it is cleared to 0. for details, refer to the description in 19.4.5 full status check . 19.4.2.6 fmr07 bit this is a read-only bit indicating the st atus of an auto-erase operation. the bit is set to 1 when an erase error occurs; otherwise, it is set to 0. refer to 19.4.5 full status check for details. 19.4.2.7 fmr11 bit setting this bit to 1 (ew1 mo de) places the mcu in ew1 mode. 19.4.2.8 fmr15 bit when the fmr02 bit is set to 1 (rewrite enabled) and the fmr15 bit is set to 0 (rewrite enabled), block 0 accepts program and block erase commands. 19.4.2.9 fmr16 bit when the fmr02 bit is set to 1 (rewrite enabled) and the fmr16 bit is set to 0 (rewrite enabled), block 1 accepts program and block erase commands. r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 360 of 453 rej09b0278-0210 19.4.2.10 fmr40 bit the suspend function is enabled by setting the fmr40 bit to 1 (enable). 19.4.2.11 fmr41 bit in ew0 mode, the mcu enters erase-suspend mode when the fmr41 bit is set to 1 by a program. the fmr41 bit is automatically set to 1 (request erase-suspend) when an interrupt request of an enabled interrupt is generated in ew1 mode, and then the mcu enters erase-suspend mode. set the fmr41 bit to 0 (erase restarts) when the auto-erase operation restarts. 19.4.2.12 fmr42 bit in ew0 mode, the mcu enters program-suspend mode when the fmr42 bit is set to 1 by a program. the fmr42 bit is automatically set to 1 (request program- suspend) when an interrupt request of an enabled interrupt is generated in ew1 mode, and th en the mcu enters program-suspend mode. set the fmr42 bit to 0 (program restart) when the auto-program operation restarts. 19.4.2.13 fmr43 bit when the auto-erase operation starts, the fmr43 bit is set to 1 (erase execution in progress). the fmr43 bit remains set to 1 (erase execution in progress) during erase-suspend operation. when the auto-erase operation ends, the fm r43 bit is set to 0 (erase not executed). 19.4.2.14 fmr44 bit when the auto-program operation star ts, the fmr44 bit is set to 1 (program execution in progress). the fmr44 bit remains set to 1 (program execution in progress) during program-suspend operation. when the auto-program operatio n ends, the fmr44 bit is set to 0 (program not executed). 19.4.2.15 fmr46 bit the fmr46 bit is set to 0 (reading disabled) during auto -program or auto-erase ex ecution and set to 1 (reading enabled) in suspend mode. do not access the flash memory while this bit is set to 0. 19.4.2.16 fmr47 bit power consumption when reading the flash memory can be reduced by set ting the fmr47 bit to 1 (enabled) in low-speed clock mode (xin clock stops) and low- speed on-chip oscillator mode (xin clock stops). r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 361 of 453 rej09b0278-0210 figure 19.5 fmr0 register flash memory control register 0 symbol address after reset fmr0 01b7h 00000001b bit symbol bit name function rw ry /by _ __ status flag notes: 1. 2. 3. 4. 5. 6. when setting the fmr01 bit to 0 (cpu rew rite mode disabled), the fmr02 bit is set to 0 (disables rew rite). fmr07 b3 b2 b1 b0 0 : disables rew rite 1 : enables rew rite flash memory stop bit (3, 5) 0 : enables flash memory operation 1 : stops flash memory (enters low -pow er consumption state and flash memory is reset) fmr01 block 0, 1 rew rite enable bit (2, 6) 0 : busy (w riting or erasing in progress) 1 : ready cpu rew rite mode select bit (1) 0 : cpu rew rite mode disabled 1 : cpu rew rite mode enabled 00 b7 b6 b5 b4 reserved bits set to 0. rw fmr02 rw rw ? (b5-b4) fmr00 fmstp rw ro ro ro this bit is set to 0 by executing the clear status command. this bit is enabled w hen the fmr01 bit is set to 1 (cpu rew rite mode enabled). when the fmr01 bit is set to 0, w riting 1 to the fmstp bit causes the fmstp bit to be set to 1. the flash memory does not enter low -pow er consumption state nor is it reset. fmr06 to set this bit to 1, set it to 1 immediately after setting it first to 0. do not generate an interrupt betw een setting the bit to 0 and setting it to 1. enter read array mode and set this bit to 0. set this bit to 1 immediately after setting it first to 0 w hile the fmr01 bit is set to 1. do not generate an interrupt betw een setting the bit to 0 and setting it to 1. set this bit by a program transferred to the ram. program status flag (4) 0 : completed successfully 1 : terminated by error erase status flag (4) 0 : completed successfully 1 : terminated by error r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 362 of 453 rej09b0278-0210 figure 19.6 fmr1 register flash memory control register 1 symbol address after reset fmr1 01b5h 1000000xb bit symbol bit name function rw notes: 1. 2. 3. fmr16 block 1 rew rite disable bit (2,3) to set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the fmr01 bit is set to 1 (cpu rew rite mode enable) . do not generate an interrupt betw een setting the bit to 0 and setting it to 1. this bit is set to 0 by setting the fmr01 bit to 0 (cpu rew rite mode disabled). reserved bit set to 1. when the fmr01 bit is set to 1 (cpu rew rite mode enabled), bits fmr15 and fmr16 can be w ritten to. to set this bit to 0, set it to 0 immediately after setting it first to 1. to set this bit to 1, set it to 1. ? (b7) 0 rw rw rw ro rw reserved bit 0 : enables rew rite 1 : disables rew rite rw fmr15 ? (b0) reserved bits when read, the content is undefined. ew1 mode select bit (1, 2) 0 : ew0 mode 1 : ew1 mode block 0 rew rite disable bit (2,3) 0 : enables rew rite 1 : disables rew rite b7 b6 b5 b4 10 b3 b2 set to 0. 0 b1 b0 fmr11 ? (b4-b2) r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 363 of 453 rej09b0278-0210 figure 19.7 fmr4 register flash memory control register 4 symbol address after reset fmr4 01b3h 01000000b bit symbol bit name function rw notes: 1. 2. 3. 4. 5. in high-speed clock mode and high-speed on-chip osc illator m ode, set the fmr47 bit to 0 (disabled). program command flag 0 : program not executed 1 : program execution in progress ro the fmr42 bit is enabled only w hen the fmr40 bit is set to 1 (enable) and programming to the fmr42 bit is enabled until auto-programming ends after a program command is generated. (this bit is set to 0 during periods other than the above.) in ew0 mode, 0 or 1 can be programmed to the fmr42 bit by a program. in ew1 mode, the fmr42 bit is automatically set to 1 by generating a maskable interrupt during auto-programming w hen the fmr40 bit is set to 1. 1 cannot be w ritten to the fmr42 bit by a program. fmr47 read status flag rw low -pow er consumption read mode enable bit (1, 4, 5) 0 : disable 1 : enable fmr46 program-suspend request bit (3) 0 : program restart 1 : program-suspend request rw fmr43 erase command flag 0 : erase not executed 1 : erase execution in progress ro fmr44 rw rw erase-suspend function enable bit (1) 0 : disables reading 1 : enables reading res er v ed bit 0 : disable 1 : enable erase-suspend request bit (2) 0 : erase restart 1 : erase-suspend request ro ro b7 b6 b5 b4 fmr41 ? (b5) 0 fmr40 fmr42 set the fmr01 bit in the fmr0 register to 0 (cpu rew rite mode disabled) in low -pow er-consumption read mode. to set this bit to 1, set it to 1 immediately after setting it first to 0. do not generate an interrupt betw een setting the bit to 0 and setting it to 1. this bit is enabled w hen the fmr40 bit is set to 1 (enable) and it can be w ritten to during the period betw een issuing an erase command and completing the erase. (this bit is set to 0 during periods other than the above.) in ew0 mode, it can be set to 0 or 1 by a program. in ew1 mode, it is automatically set to 1 if a maskable interrupt is generated during an erase operation w hile the fmr40 bit is set to 1. do not set this bit to 1 by a program (0 can be w ritten). b3 b2 set to 0. b1 b0 r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 364 of 453 rej09b0278-0210 figure 19.8 shows the timing of suspend operation. figure 19.8 timing of suspend operation fmr00 bit in fmr0 register fmr46 bit in fmr4 register fmr44 bit in fmr4 register fmr43 bit in fmr4 register 1 0 1 0 1 0 1 0 erasure starts erasure suspends programming starts programming suspends programming restarts programming ends during erasure during programming during programming erasure restarts erasure ends during erasure check that the fmr43 bit is set to 1 (during erase execution), and that the erase-operation has not ended. check that the fmr44 bit is set to 1 (during program execution), and that the program has not ended. check the status, and that the programming ends normally. check the status, and that the erasure ends normally. remains 0 during suspend remains 1 during suspend note: 1. if program-suspend is entered during erase-suspend, always restart programming. the above figure shows an example of the use of program-suspend during programming following erase-suspend. r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 365 of 453 rej09b0278-0210 figure 19.9 shows the how to set and exit ew0 mode. figure 19.10 shows the how to set and exit ew1 mode. figure 19.9 how to set and exit ew0 mode figure 19.10 how to set and exit ew1 mode set registers (1) cm0 and cm1 transfer a rewrite control program which uses cpu rewrite mode to the ram. jump to the rewrite control program which has been transferred to the ram. (the subsequent process is executed by the rewrite control program in the ram.) write 0 to the fmr01 bit before writing 1 (cpu rewrite mode enabled) (2) execute the read array command (3) execute software commands write 0 to the fmr01 bit (cpu rewrite mode disabled) jump to a specified address in the flash memory rewrite control program notes: 1. select 5 mhz or below for the cpu clock by the cm06 bit in the cm0 register and bits cm16 to cm17 in the cm1 register. 2. to set the fmr01 bit to 1, write 0 to the fmr01 bit before writing 1. do not generate an interrupt between writing 0 and 1. write to the fmr01 bit in the ram. 3. disable the cpu rewrite mode after executing the read array command. ew0 mode operating procedure write 0 to the fmr01 bit before writing 1 (cpu rewrite mode enabled) (1) write 0 to the fmr11 bit before writing 1 (ew1 mode) execute software commands write 0 to the fmr01 bit (cpu rewrite mode disabled) note: 1. to set the fmr01 bit to 1, write 0 to the fmr01 bit before writing 1. do not generate an interrupt between writing 0 and 1. ew1 mode operating procedure program in rom r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 366 of 453 rej09b0278-0210 figure 19.11 process to reduce power consumpt ion in high-speed on-c hip oscillator mode, low-speed on-chip oscillator mode (xin clock stops) and low-speed clock mode (xin clock stops) transfer a high-speed on-chip oscillator mode, low- speed on-chip oscillator mo de (xin clock stops), and low-speed clock mode (xin clock stops) program to the ram. jump to the high-speed on-c hip oscillator mode, low- speed on-chip oscillator mo de (xin clock stops), and low-speed clock mode (xin clock stops) program which has been transferred to the ram. (the subsequent processing is executed by the program in the ram.) write 0 to the fmr01 bit before writing 1 (cpu rewrite mode enabled) switch the clock source for the cpu clock. turn xin off process in high-speed on-chip oscillator mode, low-speed on-ch ip oscillator mode (xin clock stops), and low-speed clock mode (xin clock stops) write 0 to the fmr01 bit (cpu rewrite mode disabled) jump to a specified address in the flash memory high-speed on-chip oscillator mode, low-speed on-chip oscillator mode (xin clock stops), and low-speed clock mode (xin clock stops) program notes: 1. set the fmr01 bit to 1 (cpu rewrite mode enabled) before setting the fmstp bit to 1. 2. before switching to a different clock source for the cpu, make sure the designated clock is stable. 3. insert a 30 s wait time in a program. do not access to the flash memory during this wait time. write 1 to the fmstp bit (flash memory stops. low power consumption mode) (1) wait until the flash memory circuit stabilizes (30 s) (3) write 0 to the fmstp bit (flash memory operation) turn xin clock on wait until oscillation stabilizes switch the clock source for cpu clock (2) r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 367 of 453 rej09b0278-0210 19.4.3 software commands the software commands are described below. read or write commands and data in 8-bit units. srd: status register data (d7 to d0) wa: write address (ensure the address specified in the first bus cycle is the same address as the write address specified in the second bus cycle.) wd: write data (8 bits) ba: given block address : any specified address in the user rom area 19.4.3.1 read array command the read array command reads the flash memory. the mcu enters read array mode when ffh is written in the first bus cycle. when the read address is entered in the following bus cycles , the content of the specified addr ess can be read in 8-bit units. since the mcu remains in read array mode until another command is written, the contents of multiple addresses can be read continuously. in addition, the mcu enters r ead array mode after a reset. 19.4.3.2 read status register command the read status register command is used to read the status register. when 70h is written in the first bus cy cle, the status register can be read in the second bus cycle (refer to 19.4.4 status registers ). when reading the status register, specify an addr ess in the user rom area. do not execute this command in ew1 mode. the mcu remains in read status register mode until the next read array command is written. 19.4.3.3 clear status register command the clear status register command sets the status register to 0. when 50h is written in the first bus cycle, bits fmr06 to fmr07 in the fmr0 register and sr4 to sr5 in the status register are set to 0. table 19.4 software commands command first bus cycle second bus cycle mode address data (d7 to d0) mode address data ( d7 to d0) read array write ffh read status register write 70h read srd clear status register write 50h program write wa 40h write wa wd block erase write 20h write ba d0h r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 368 of 453 rej09b0278-0210 19.4.3.4 program command the program command writes data to the flash memory in 1-byte units. by writing 40h in the first bus cycle and data in the s econd bus cycle to the writ e address, an auto-program operation (data program and verify) will start. make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle. the fmr00 bit in the fmr0 register can be used to determine whether auto-programming has completed. when suspend function disabled, the fmr00 bit is set to 0 during auto-programming and set to 1 when auto- programming completes. when suspend function enabled, the fmr44 bit is set to 1 during auto-programming and set to 0 when auto- programming completes. the fmr06 bit in the fmr0 register can be used to de termine the result of auto -programming after it has been finished (refer to 19.4.5 full status check ). do not write additions to the already programmed addresses. when the fmr02 bit in the fmr0 register is set to 0 (r ewriting disabled) or the fmr02 bit is set to 1 (rewriting enabled) and the fmr15 bit in the fmr1 register is set to 1 (rewriting disabled), program commands targeting block 0 are not acknowledged. when the fmr16 bit is set to 1 (rewriting disabled), program commands targeting block 1 are not acknowledged. figure 19.12 shows the program command (when su spend function disabled). figure 19.13 shows the program command (when suspend function enabled). in ew1 mode, do not execute this command for any a ddress which a rewrite cont rol program is allocated. in ew0 mode, the mcu enters read status register mode at the same time auto-p rogramming starts and the status register can be read. the status register bit 7 (sr7) is set to 0 at the same time auto-programming starts and set back to 1 when auto-programming completes. in this case, the mcu remains in read status register mode until the next read array command is written. the status register ca n be read to determine the result of auto-programming after auto-programming has completed. figure 19.12 program command (when suspend function disabled) start write the command code 40h to the write address write data to the write address fmr00 = 1? full status check program completed no yes r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 369 of 453 rej09b0278-0210 figure 19.13 program command (when suspend function enabled) start write the command code 40h to the write address write data to the write address fmr44 = 0 ? full status check program completed no yes ew0 mode fmr40 = 1 start write the command code 40h write data to the write address fmr44 = 0 ? full status check program completed no yes ew1 mode fmr40 = 1 maskable interrupt (2) reit access flash memory fmr42 = 0 notes: 1. in ew0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the ram area. 2. td(sr-sus) is needed until the interrupt request is acknowledged after it is generated. the interrupt to enter suspend should be in interrupt enabled status. 3. when no interrupt is used, the instruction to enable interrupts is not needed. 4. td(sr-sus) is needed until program is suspended after the fmr42 bit in the fmr4 register is set to 1. maskable interrupt (1) fmr46 = 1 ? reit yes fmr42 = 1 (4) fmr42 = 0 access flash memory fmr44 = 1 ? yes no access flash memory no i = 1 (enable interrupt) i = 1 (enable interrupt) (3) r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 370 of 453 rej09b0278-0210 19.4.3.5 block erase when 20h is written in the first bus cycle and d0h is wr itten to a given address of a block in the second bus cycle, an auto-erase operation (erase an d verify) of the specified block starts. the fmr00 bit in the fmr0 re gister can determine whether auto-erasure has completed. the fmr00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes. the fmr07 bit in the fmr0 register can be used to dete rmine the result of auto-erasure after auto-erasure has completed (refer to 19.4.5 full status check ). when the fmr02 bit in the fmr0 register is set to 0 (r ewriting disabled) or the fmr02 bit is set to 1 (rewriting enabled) and the fmr15 bit in the fmr1 register is set to 1 (rewriting disabled), the block erase commands targeting block 0 are not acknowledged. when the fmr16 bit is set to 1 (rewriting disabled), the block erase commands targeting block 1 are not acknowledged. do not use the block erase command during program-suspend. figure 19.14 shows the block erase command (when er ase-suspend function disabled). figure 19.15 shows the block erase command (when er ase-suspend function enabled). in ew1 mode, do not execute this command for any addr ess to which a rewrite control program is allocated. in ew0 mode, the mcu enters read stat us register mode at the same time auto-erasure starts and the status register can be read. the status register bit 7 (sr7) is set to 0 at the same time auto-erasure starts and set back to 1 when auto-erasure completes. in th is case, the mcu remains in read stat us register mode until the next read array command is written. figure 19.14 block erase command (when erase-suspend function disabled) start write the command code 20h write d0h to a given block address fmr00 = 1? full status check block erase completed no yes r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 371 of 453 rej09b0278-0210 figure 19.15 block erase command (when erase-suspend function enabled) start write the command code 20h write d0h to any block address fmr00 = 1 ? full status check block erase completed no yes ew0 mode fmr40 = 1 start write the command code 20h write d0h to any block address fmr00 = 1 ? full status check block erase completed no yes ew1 mode i = 1 (enable interrupt) maskable interrupt (2) reit access flash memory fmr41 = 0 notes: 1. in ew0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the ram area. 2. td(sr-sus) is needed until the interrupt request is acknowledged after it is generated. the interrupt to enter suspend should be in interrupt enabled status. 3. when no interrupt is used, the instruction to enable interrupts is not needed. 4. td(sr-sus) is needed until erase is suspended after the fmr41 bit in the fmr4 register is set to 1. maskable interrupt (1) fmr46 = 1 ? reit yes fmr41 = 1 (4) fmr41 = 0 access flash memory fmr43 = 1 ? yes no access flash memory no i = 1 (enable interrupt) (3) fmr40 = 1 r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 372 of 453 rej09b0278-0210 19.4.4 status registers the status register indicates the oper ating status of the flash memory and whether an erase or program operation has completed normally or in error. status of the stat us register can be read by bits fmr00, fmr06, and fmr07 in the fmr0 register. table 19.5 lists the status register bits. in ew0 mode, the status register can be read in the following cases: ? when a given address in the user rom area is read after writing the read status register command ? when a given address in the user rom area is read after executing the program or block erase command but before executing th e read array command. 19.4.4.1 sequencer status (sr7 and fmr00 bits) the sequencer status bits indicate the operating status of the flash memory. sr7 is set to 0 (busy) during auto- programming and auto-erasure, and is set to 1 (rea dy) at the same time the operation completes. 19.4.4.2 erase status (sr5 and fmr07 bits) refer to 19.4.5 full status check . 19.4.4.3 program status (sr4 and fmr06 bits) refer to 19.4.5 full status check . d0 to d7: indicate the data bus which is read when the read status register command is executed. bits fmr07 (sr5) to fmr06 (sr4) are set to 0 by executing the clear status register command. when the fmr07 bit (sr5) or fmr06 bit (sr4) is set to 1, the program and block erase commands cannot be accepted. table 19.5 status register bits status register bit fmr0 register bit status name description value after reset 01 sr0 (d0) ? reserved ??? sr1 (d1) ? reserved ??? sr2 (d2) ? reserved ??? sr3 (d3) ? reserved ??? sr4 (d4) fmr06 program status completed normally error 0 sr5 (d5) fmr07 erase status completed normally error 0 sr6 (d6) ? reserved ??? sr7 (d7) fmr00 sequencer status busy ready 1 r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 373 of 453 rej09b0278-0210 19.4.5 full status check when an error occurs, bits fmr06 to fmr07 in the fmr0 register are set to 1, indicating the occurrence of an error. therefore, checking th ese status bits (full status check) can be used to determine the execution result. table 19.6 lists the errors and fmr0 register status. figure 19.16 shows the full status check and handling procedure for indi vidual errors. note: 1. the mcu enters read array mode when ffh is writ ten in the second bus cycle of these commands. at the same time, the comma nd code written in the first bus cycle is disabled. table 19.6 errors and fmr0 register status fmr0 register (status register) status error error occurrence condition fmr07 (sr5) fmr06 (sr4) 1 1 command sequence error ? when a command is not written correctly ? when invalid data other than that which can be written in the second bus cycle of the block erase command is written (i.e., other than d0h or ffh) (1) ? when the program command or block erase command is executed while rewriting is disabled by the fmr02 bit in the fmr0 register, or the fmr15 or fmr16 bit in the fmr1 register. ? when an address not allocated in flash memory is input during erase command input ? when attempting to erase the block for which rewriting is disabled during erase command input. ? when an address not allocated in flash memory is input during write command input. ? when attempting to write to a block for which rewriting is disabled during the write command input. 1 0 erase error ? when the block erase command is executed but auto- erasure does not complete correctly 0 1 program error ? when the program command is executed but not auto- programming does not complete. r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 374 of 453 rej09b0278-0210 figure 19.16 full status check and ha ndling procedure for individual errors note: 1. to rewrite to the address where the program error occurs, check if the full status check is complete normally and write to the address after the block erase command is executed. full status check fmr06 = 1 and fmr07 = 1? fmr07 = 1? fmr06 = 1? full status check completed no yes yes no yes no command sequence error erase error program error command sequence error execute the clear status register command (set these status flags to 0) check if command is properly input re-execute the command erase error execute the clear status register command (set these status flags to 0) erase command re-execution times 3 times? re-execute block erase command program error execute the clear status register command (set these status flags to 0) specify the other a ddress besides the write address where the error occurs for the program address (1) re-execute program command block targeting for erasure cannot be used no yes r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 375 of 453 rej09b0278-0210 19.5 standard serial i/o mode in standard serial i/o mode, the user rom area can be rewritten while the mcu is mounted on-board by using a serial programmer which is suitable for the mcu. there are three types of standard serial i/o modes: ? standard serial i/o mode 1 ........... .clock synchronous serial i/o used to connect with a serial programmer ? standard serial i/o mode 2 ........... .clock asynchronous serial i/o used to connect with a serial programmer ? standard serial i/o mode 3 ........... .special clock asynchronous serial i/o used to connect with a serial programmer this mcu uses standard serial i/o mode 2 and standard serial i/o mode 3. refer to appendix 2. connection examples between s erial writer and on-chip debugging emulator . contact the manufacturer of your serial programmer fo r details. refer to the user?s manual of your serial programmer for instructions on how to use it. table 19.7 lists the pin functions (flash memory standard serial i/o mode 2), table 19.8 lists the pin functions (flash memory standard serial i/o mode 3), and figure 19.17 shows the pin connections for standard serial i/o mode 3. after processing the pins shown in table 19.8 and rewriting the flash memory using the programmer, apply ?h? to the mode pin and reset the hardware to run a pr ogram in the flash memory in single-chip mode. 19.5.1 id code check function the id code check function determines whether the id codes sent from the serial programmer and those written in the flash memory match (refer to 19.3 functions to prevent rewriting of flash memory ). table 19.7 pin functions (flash memory standard serial i/o mode 2) pin name i/o description vcc,vss power input apply the voltage guaranteed for programming and erasure to the vcc pin and 0 v to the vss pin. reset reset input i reset input pin. p4_6/xin/xcin p4_6 inpu t/clock input i connect a ceramic resonator or crystal oscillator between the xin/xcin and xout/xcout pins. p4_7/xout/xcout p4_7 input/clock output i/o p0_0 to p0_7 input port p0 i input ?h? or ?l? level signal or leave the pin open. p1_0 to p1_7 input port p1 i p3_0, p3_1, p3_3 to p3_6 input port p3 i p4_2/vref inpu t port p4 i p5_3, p5_4 input port p5 i mode mode i/o input ?l?. p3_7 txd output o serial data output pin. p4_5 rxd input i serial data input pin. r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 376 of 453 rej09b0278-0210 figure 19.17 pin connections for standard serial i/o mode 3 table 19.8 pin functions (flash memory standard serial i/o mode 3) pin name i/o description vcc,vss power input apply the voltage guaranteed for programming and erasure to the vcc pin and 0 v to the vss pin. reset reset input i reset input pin. p4_6/xin/xcin p4_6 inpu t/clock input i connect a ceramic resonator or crystal oscillator between the xin/xcin and xout/xcout pins when connecting external os cillator. apply ?h? and ?l? or leave the pin open when using as input port. p4_7/xout/xcout p4_7 input/clock output i/o p0_0 to p0_7 input port p0 i input ?h? or ?l? level signal or leave the pin open. p1_0 to p1_7 input port p1 i p3_0, p3_1, p3_3 to p3_7 input port p3 i p4_2/vref, p4_5 input port p4 i p5_3, p5_4 input port p5 i mode mode i/o serial data i/o pin. connect to the flash programmer. note: 1. it is not necessary to connect an oscillating circuit when operating with the on-chip oscillator clock. package: plqp0032gb-a mode setting signal value mode reset voltage from programmer vss vcc connect oscillator circuit (1) vcc mode vss r8c/26 group r8c/27 group 29 28 27 26 25 32 31 30 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 578 1234 6 r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 377 of 453 rej09b0278-0210 19.5.1.1 example of circuit applicati on in the standard serial i/o mode figure 19.18 shows an example of pin processing in standard serial i/o mode 2, figure 19.19 shows an example of pin processing in standard serial i/o mode 3. since the controlled pins vary depending on the programmer, refer to the manual of your serial programmer for details. figure 19.18 example of pin processing in standard serial i/o mode 2 figure 19.19 example of pin processing in standard serial i/o mode 3 notes: 1. in this example, modes are switched between single-chip mode and standard serial i/o mode by controlling the mode input with a switch. 2. connecting the oscillation is necessary. set the main clock frequency 1 mhz to 20 mhz. refer to appendix figure 2.1 connection example with m16c flash starter (m3a-0806) . mcu txd rxd data output data input mode notes: 1. controlled pins and external circ uits vary depending on the programmer. refer to the programmer manual for details. 2. in this example, modes are switched between single-chip mode and standard serial i/o mode by connecting a programmer. 3. when operating with the on-chip oscillator clock, it is not necessary to connect an oscillating circuit. mcu mode reset user reset signal mode i/o reset input r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 378 of 453 rej09b0278-0210 19.6 parallel i/o mode parallel i/o mode is used to input a nd output software commands, addresses and data necessary to control (read, program, and erase) the on-chip flash memory. use a pa rallel programmer which suppor ts this mcu. contact the manufacturer of the parallel programmer for more inform ation, and refer to the user?s manual of the parallel programmer for details on how to use it. rom areas shown in figures 19.1 and 19.2 can be rewritten in parallel i/o mode. 19.6.1 rom code protect function the rom code protect function disables the reading and rewriting of the flash memory. (refer to 19.3 functions to prevent rewriting of flash memory .) r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 379 of 453 rej09b0278-0210 19.7 notes on flash memory 19.7.1 cpu rewrite mode 19.7.1.1 operating speed before entering cpu rewrite mode (ew0 mode), select 5 mhz or below for the cpu clock using the cm06 bit in the cm0 register and bits cm16 to cm17 in the cm1 register. this does not apply to ew1 mode. 19.7.1.2 prohibited instructions the following instru ctions cannot be used in ew0 mode because th ey reference internal data in flash memory: und, into, and brk. 19.7.1.3 interrupts table 19.9 lists the ew0 mode interrupts and table 19.10 lists the ew1 mode interrupt. notes: 1. do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in rom. 2. do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is alloca ted in block 0. table 19.9 ew0 mode interrupts mode status when maskable interrupt request is acknowledged when watchdog timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2 interrupt request is acknowledged ew0 during auto-erasure any interrupt can be used by allocating a vector in ram once an interrupt request is acknowledged, the auto-programming or auto-erasure is forcibly stopped immediately and the flash memory is reset. interrupt handling starts after the fixed period and the flash memory restarts. since the block during auto- erasure or the address during auto- programming is forcibly stopped, the normal value may not be read. execute auto-erasure again and ensure it completes normally. since the watchdog timer does not stop during the command operation, interrupt requests may be generated. reset the watchdog timer regularly. auto-programming r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 380 of 453 rej09b0278-0210 notes: 1. do not use the address match interrupt while a command is executing because the vector of the address match interrupt is allocated in rom. 2. do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is alloca ted in block 0. table 19.10 ew1 mode interrupt mode status when maskable interrupt request is acknowledged when watchdog timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2 interrupt request is acknowledged ew1 during auto-erasure (erase-suspend function enabled) auto-erasure is suspended after td(sr-sus) and interrupt handling is executed. auto- erasure can be restarted by setting the fmr41 bit in the fmr4 register to 0 (erase restart) after interrupt handling completes. once an interrupt request is acknowledged, auto-programming or auto-erasure is forcibly stopped immediately and the flash memory is reset. interrupt handling starts after the fixed period and the flash memory restarts. since the block during auto- erasure or the address during auto- programming is forcibly stopped, the normal value may not be read. execute auto-erasure again and ensure it completes normally. since the watchdog timer does not stop during the command operation, interrupt requests may be generated. reset the watchdog timer regularly using the erase-suspend function. during auto-erasure (erase-suspend function disabled) auto-erasure has priority and the interrupt request acknowledgement is put on standby. interrupt handling is executed after auto-erasure completes. during auto- programming (program suspend function enabled) auto-programming is suspended after td(sr-sus) and interrupt handling is executed. auto-programming can be restarted by setting the fmr42 bit in the fmr4 register to 0 (program restart) after interrupt handling completes. during auto- programming (program suspend function disabled) auto-programming has priority and the interrupt request acknowledgement is put on standby. interrupt handling is executed after auto-programming completes. r8c/26 group, r8c/27 group 19. flash memory rev.2.10 sep 26, 2008 page 381 of 453 rej09b0278-0210 19.7.1.4 how to access write 0 before writing 1 when setting the fmr01, fmr02, or fmr11 bit to 1. do not generate an interrupt between writing 0 and 1. 19.7.1.5 rewriting user rom area in ew0 mode, if the supply voltage drops while rewr iting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. in this case, use standard serial i/o mode. 19.7.1.6 program do not write additions to th e already programmed address. 19.7.1.7 entering stop mode or wait mode do not enter stop mode or wait mode during erase-suspend. 19.7.1.8 program and erase voltage for flash memory to perform programming and erasure, use vcc = 2.7 to 5.5 v as the supply voltage. do not perform programming and erasure at less than 2.7 v. r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 382 of 453 rej09b0278-0210 20. electrical characteristics 20.1 n, d version notes: 1. v cc = 2.2 to 5.5 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. the average output current indicates the av erage value of current measured during 100 ms. table 20.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage -0.3 to 6.5 v v i input voltage -0.3 to v cc + 0.3 v v o output voltage -0.3 to v cc + 0.3 v p d power dissipation t opr = 25 c500mw t opr operating ambient temperature -20 to 85 (n version) / -40 to 85 (d version) c t stg storage temperature -65 to 150 c table 20.2 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 2.2 ? 5.5 v v ss /av ss supply voltage ? 0 ? v v ih input ?h? voltage 0.8 v cc ? v cc v v il input ?l? voltage 0 ? 0.2 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ?? -160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ?? -80 ma i oh(peak) peak output ?h? current except p1_0 to p1_7 ?? -10 ma p1_0 to p1_7 ?? -40 ma i oh(avg) average output ?h? current except p1_0 to p1_7 ?? -5 ma p1_0 to p1_7 ?? -20 ma i ol(sum) peak sum output ?l? currents sum of all pins i ol(peak) ?? 160 ma i ol(sum) average sum output ?l? currents sum of all pins i ol(avg) ?? 80 ma i ol(peak) peak output ?l? currents except p1_0 to p1_7 ?? 10 ma p1_0 to p1_7 ?? 40 ma i ol(avg) average output ?l? current except p1_0 to p1_7 ?? 5ma p1_0 to p1_7 ?? 20 ma f (xin) xin clock input oscillation frequency 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz f (xcin) xcin clock input oscillation frequency 2.2 v v cc 5.5 v 0 ? 70 khz ? system clock ocd2 = 0 xln clock selected 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz ocd2 = 1 on-chip oscillator clock selected fra01 = 0 low-speed on-chip oscillator clock selected ? 125 ? khz fra01 = 1 high-speed on-chip oscillator clock selected 3.0 v v cc 5.5 v ?? 20 mhz fra01 = 1 high-speed on-chip oscillator clock selected 2.7 v v cc 5.5 v ?? 10 mhz fra01 = 1 high-speed on-chip oscillator clock selected 2.2 v v cc 5.5 v ?? 5mhz r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 383 of 453 rej09b0278-0210 notes: 1. av cc = 2.2 to 5.5 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. when the analog input voltage is over the reference voltage, t he a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. figure 20.1 ports p0, p1, and p3 to p5 timing measurement circuit table 20.3 a/d converter characteristics symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ?? 10 bits ? absolute accuracy 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 3 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 2 lsb 10-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 5 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 2 lsb 10-bit mode ad = 5 mhz, v ref = av cc = 2.2 v ?? 5 lsb 8-bit mode ad = 5 mhz, v ref = av cc = 2.2 v ?? 2 lsb r ladder resistor ladder v ref = av cc 10 ? 40 k ? t conv conversion time 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 3.3 ?? s 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 2.8 ?? s v ref reference voltage 2.2 ? av cc v v ia analog input voltage (2) 0 ? av cc v ? a/d operating clock frequency without sample and hold v ref = av cc = 2.7 to 5.5 v 0.25 ? 10 mhz with sample and hold v ref = av cc = 2.7 to 5.5 v 1 ? 10 mhz without sample and hold v ref = av cc = 2.2 to 5.5 v 0.25 ? 5mhz with sample and hold v ref = av cc = 2.2 to 5.5 v 1 ? 5mhz p0 p1 p3 p4 p5 30pf r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 384 of 453 rej09b0278-0210 notes: 1. v cc = 2.7 to 5.5 v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 1, 000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in bloc k a, a 1 kbyte block, and t hen the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. in a system that executes multiple prog ramming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possibl e is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of re writes can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erasure endurance of ea ch block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute th e clear status register command , then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information s hould contact their renesas tech nical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. table 20.4 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) r8c/26 group 100 (3) ?? times r8c/27 group 1,000 (3) ?? times ? byte program time ? 50 400 s ? block erase time ? 0.4 9 s t d(sr-sus) time delay from suspend request until suspend ?? 97 + cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3 + cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.2 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ?? year r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 385 of 453 rej09b0278-0210 notes: 1. v cc = 2.7 to 5.5 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. standard of block a and block b when program and erase endurance exceeds 1,000 times. byte program time to 1,000 times is the same as that in program rom. 5. in a system that executes multiple prog ramming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possibl e is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of re writes can be minimized by programming up to 128 groups before erasing them all in one operati on. in addition, averaging the erasure endurance between blocks a and b can further reduce the actual erasure endurance. it is also advisable to retain data on the er asure endurance of each block and limit the number of erase operations to a certain number. 6. if an error occurs during block erase, attempt to execute th e clear status register command , then execute the block erase command at least three times until the erase error does not occur. 7. customers desiring program/erase failure rate information s hould contact their renesas tech nical support representative. 8. -40 c for d version. 9. the data hold time includes time that the pow er supply is off or the clock is not supplied. table 20.5 flash memory (data flash block a, block b) electrical characteristics (4) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ?? times ? byte program time (program/erase endurance 1,000 times) ? 50 400 s ? byte program time (program/erase endurance > 1,000 times) ? 65 ? s ? block erase time (program/erase endurance 1,000 times) ? 0.2 9 s ? block erase time (program/erase endurance > 1,000 times) ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ?? 97 + cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3 + cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.2 ? 5.5 v ? program, erase temperature -20 (8) ? 85 c ? data hold time (9) ambient temperature = 55 c20 ?? year r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 386 of 453 rej09b0278-0210 figure 20.2 time de lay until suspend notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = -20 to 85 c (n version) / -40 to 85 c (d version). 2. necessary time until the voltage detecti on circuit operates when setti ng to 1 again after setting the vca25 bit in the vca2 register to 0. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = -20 to 85 c (n version) / -40 to 85 c (d version). 2. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 3. necessary time until the voltage detecti on circuit operates when setti ng to 1 again after setting the vca26 bit in the vca2 register to 0. 4. this parameter shows the voltage detecti on level when the power supply drops. the voltage detection level when the power supply rises is hi gher than the voltage detection level when the power supply drops by approximately 0.1 v. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = -20 to 85 c (n version) / -40 to 85 c (d version). 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 3. necessary time until the voltage detection circuit operates after setting to 1 again after setting the vca27 bit in the vca2 register to 0. table 20.6 voltage detection 0 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level 2.2 2.3 2.4 v ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 0.9 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ?? 300 s vccmin mcu operating voltage minimum value 2.2 ?? v table 20.7 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level (4) 2.70 2.85 3.00 v ? voltage monitor 1 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s table 20.8 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level 3.3 3.6 3.9 v ? voltage monitor 2 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s fmr46 suspend request (maskable interrupt request) fixed time t d(sr-sus) clock-dependent time access restart r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 387 of 453 rej09b0278-0210 notes: 1. the measurement condition is t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. this condition (external power v cc rise gradient) does not apply if v cc 1.0 v. 3. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvd0on bit in the ofs register to 0, the vw0c0 and vw0c6 bits in the vw0c register to 1 res pectively, and the vca25 bit in the vca2 register to 1. 4. t w(por1) indicates the duration the external power v cc must be held below the effective voltage (v por1 ) to enable a power on reset. when turning on the power for the first time, maintain t w(por1) for 30 s or more if -20 c t opr 85 c, maintain t w(por1) for 3,000 s or more if -40 c t opr < -20 c. figure 20.3 reset circuit electrical characteristics table 20.9 power-on reset circuit, voltage monitor 0 reset electrical characteristics (3) symbol parameter condition standard unit min. typ. max. v por1 power-on reset valid voltage (4) ?? 0.1 v v por2 power-on reset or voltage monitor 0 reset valid voltage 0 ? v det0 v t rth external power v cc rise gradient (2) 20 ?? mv/msec notes: 1. when using the voltage monitor 0 digital filter, ensure that the voltage is within the mcu operation voltage range (2.2 v or above) during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit for details. 3. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to 6. voltage detection circuit for details. v det0 (3) v por1 internal reset signal (?l? valid) t w(por1) sampling time (1, 2) v det0 (3) 1 f oco-s 32 1 f oco-s 32 v por2 2.2 v external power v cc t rth t rth r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 388 of 453 rej09b0278-0210 notes: 1. v cc = 2.2 to 5.5 v, t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. these standard values show when the fra1 register value after reset is assumed. 3. these standard values show when the corrected value of the fra6 register is written to the fra1 register. 4. this enables the setting errors of bit rates such as 9600 bp s and 38400 bps to be 0% when the serial interface is used in uart mode. note: 1. v cc = 2.2 to 5.5 v, t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power su pply generation circuit stabilizes during power-on. 3. time until system clock supply starts after t he interrupt is acknowledged to exit stop mode. table 20.10 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco40m high-speed on-chip oscillator frequency temperature ? supply voltage dependence v cc = 4.75 to 5.25 v 0 c t opr 60 c (2) 39.2 40 40.8 mhz v cc = 3.0 to 5.5 v -20 c t opr 85 c (2) 38.8 40 41.2 mhz v cc = 3.0 to 5.5 v -40 c t opr 85 c (2) 38.4 40 41.6 mhz v cc = 2.7 to 5.5 v -20 c t opr 85 c (2) 38 40 42 mhz v cc = 2.7 to 5.5 v -40 c t opr 85 c (2) 37.6 40 42.4 mhz v cc = 2.2 to 5.5 v -20 c t opr 85 c (3) 35.2 40 44.8 mhz v cc = 2.2 to 5.5 v -40 c t opr 85 c (3) 34 40 46 mhz v cc = 5.0 v 10% -20 c t opr 85 c (2) 38.8 40 40.8 mhz v cc = 5.0 v 10% -40 c t opr 85 c (2) 38.4 40 40.8 mhz high-speed on-chip oscillator frequency when correction value in fra7 register is written to fra1 register (4) v cc = 5.0 v, t opr = 25 c ? 36.864 ? mhz v cc = 3.0 to 5.5 v -20 c t opr 85 c -3% ? 3% % ? value in fra1 register after reset 08h (3) ? f7h (3) ? ? oscillation frequency adjustment unit of high- speed on-chip oscillator adjust fra1 register (value after reset) to -1 ? +0.3 ? mhz ? oscillation st ability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 400 ? a table 20.11 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 30 125 250 khz ? oscillation st ability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 15 ? a table 20.12 power supply circuit timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabiliz ation during power-on (2) 1 ? 2000 s t d(r-s) stop exit time (3) ?? 150 s r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 389 of 453 rej09b0278-0210 notes: 1. v cc = 2.2 to 5.5 v, v ss = 0 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) table 20.13 timing requirements of clock synchronous serial i/o with chip select (1) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ?? t cyc (2) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ?? 1 t cyc (2) slave ?? 1 s t fall ssck clock falling time master ?? 1 t cyc (2) slave ?? 1 s t su sso, ssi data input setup time 100 ?? ns t h sso, ssi data input hold time 1 ?? t cyc (2) t lead scs setup time slave 1t cyc + 50 ?? ns t lag scs hold time slave 1t cyc + 50 ?? ns t od sso, ssi data output delay time ?? 1 t cyc (2) t sa ssi slave access time 2.7 v v cc 5.5 v ?? 1.5t cyc + 100 ns 2.2 v v cc < 2.7 v ?? 1.5t cyc + 200 ns t or ssi slave out open time 2.7 v v cc 5.5 v ?? 1.5t cyc + 100 ns 2.2 v v cc < 2.7 v ?? 1.5t cyc + 200 ns r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 390 of 453 rej09b0278-0210 figure 20.4 i/o timing of clock synchronous serial i/o with chip select (master) v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 391 of 453 rej09b0278-0210 figure 20.5 i/o timing of clock synchronous serial i/o with chip select (slave) v ih or v oh v ih or v oh scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 392 of 453 rej09b0278-0210 figure 20.6 i/o timing of clock synchronous serial i/o with chip select (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v ih or v oh r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 393 of 453 rej09b0278-0210 notes: 1. v cc = 2.2 to 5.5 v, v ss = 0 v and t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) figure 20.7 i/o timing of i 2 c bus interface table 20.14 timing requirements of i 2 c bus interface (1) symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ?? ns t sclh scl input ?h? width 3t cyc + 300 (2) ?? ns t scll scl input ?l? width 5t cyc + 500 (2) ?? ns t sf scl, sda input fall time ?? 300 ns t sp scl, sda input spike pulse rejection time ?? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ?? ns t stah start condition input hold time 3t cyc (2) ?? ns t stas retransmit start condition input setup time 3t cyc (2) ?? ns t stop stop condition input setup time 3t cyc (2) ?? ns t sdas data input setup time 1t cyc + 20 (2) ?? ns t sdah data input hold time 0 ?? ns sda t stah t scll t buf v ih v il t sclh scl t sr t sf t sdah t scl t stas t sp t stop t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. retransmit start condition r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 394 of 453 rej09b0278-0210 note: 1. v cc = 4.2 to 5.5 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), f(xin) = 20 mhz, unless otherwise specified. table 20.15 electrical characteristics (1) [v cc = 5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p1_0 to p1_7, xout i oh = ? 5 ma v cc - 2.0 ? v cc v i oh = -200 av cc - 0.5 ? v cc v p1_0 to p1_7 drive capacity high i oh = -20 ma v cc - 2.0 ? v cc v drive capacity low i oh = -5 ma v cc - 2.0 ? v cc v xout drive capacity high i oh = -1 ma v cc - 2.0 ? v cc v drive capacity low i oh = -500 av cc - 2.0 ? v cc v v ol output ?l? voltage except p1_0 to p1_7, xout i ol = 5 ma ?? 2.0 v i ol = 200 a ?? 0.45 v p1_0 to p1_7 drive capacity high i ol = 20 ma ?? 2.0 v drive capacity low i ol = 5 ma ?? 2.0 v xout drive capacity high i ol = 1 ma ?? 2.0 v drive capacity low i ol = 500 a ?? 2.0 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.1 0.5 ? v reset 0.1 1.0 ? v i ih input ?h? current vi = 5 v, v cc = 5 v ?? 5.0 a i il input ?l? current vi = 0 v, v cc = 5 v ?? -5.0 a r pullup pull-up resistance vi = 0 v, v cc = 5 v 30 50 167 k ? r fxin feedback resistance xin ? 1.0 ? m ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 395 of 453 rej09b0278-0210 table 20.16 electrical characteristics (2) [vcc = 5 v] (t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 10 17 ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 915ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6 ? ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 5 ? ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 20 mhz low-speed on-chip oscillator on = 125 khz no division ? 10 15 ma xin clock off high-speed on-chip oscillator on foco = 20 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 5.5 10 ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 130 300 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 130 300 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 30 ? a r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 396 of 453 rej09b0278-0210 table 20.17 electrical characteristics (3) [vcc = 5 v] (t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 25 75 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 23 60 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 4.0 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 2.2 ? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.8 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.2 ? a r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 397 of 453 rej09b0278-0210 timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v at t opr = 25 c) [v cc = 5 v] figure 20.8 xin input and xcin input timing diagram when v cc = 5 v figure 20.9 traio input timing diagram when v cc = 5 v table 20.18 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input ?h? width 25 ? ns t wl(xin) xin input ?l? width 25 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 20.19 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 5 v traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio) r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 398 of 453 rej09b0278-0210 i = 0 or 1 figure 20.10 serial interfa ce timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 20.11 external interrupt inti input timing diagram when v cc = 5 v table 20.20 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 20.21 external interrupt inti (i = 0, 1, 3) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 250 (1) ? ns t w(inl) inti input ?l? width 250 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0 or 1 v cc = 5 v inti input t w(inl) t w(inh) i = 0, 1, 3 v cc = 5 v r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 399 of 453 rej09b0278-0210 note: 1. v cc = 2.7 to 3.3 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), f(xin) = 10 mhz, unless otherwise specified. table 20.22 electrical characteristics (3) [v cc = 3 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p1_0 to p1_7, xout i oh = -1 ma v cc - 0.5 ? v cc v p1_0 to p1_7 drive capacity high i oh = -5 ma v cc - 0.5 ? v cc v drive capacity low i oh = -1 ma v cc - 0.5 ? v cc v xout drive capacity high i oh = -0.1 ma v cc - 0.5 ? v cc v drive capacity low i oh = -50 av cc - 0.5 ? v cc v v ol output ?l? voltage except p1_0 to p1_7, xout i ol = 1 ma ?? 0.5 v p1_0 to p1_7 drive capacity high i ol = 5 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.1 0.3 ? v reset 0.1 0.4 ? v i ih input ?h? current vi = 3 v, v cc = 3 v ?? 4.0 a i il input ?l? current vi = 0 v, v cc = 3 v ?? -4.0 a r pullup pull-up resistance vi = 0 v, v cc = 3 v 66 160 500 k ? r fxin feedback resistance xin ? 3.0 ? m ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 400 of 453 rej09b0278-0210 table 20.23 electrical characteristics (4) [vcc = 3 v] (t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 59ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 130 300 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 130 300 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 30 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 25 70 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 23 55 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.8 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 2.0 ? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.7 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.1 ? a r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 401 of 453 rej09b0278-0210 timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v at t opr = 25 c) [v cc = 3 v] figure 20.12 xin input and xcin input timing diagram when v cc = 3 v figure 20.13 traio input timing diagram when v cc = 3 v table 20.24 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 100 ? ns t wh(xin) xin input ?h? width 40 ? ns t wl(xin) xin input ?l? width 40 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 20.25 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 3 v traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio) r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 402 of 453 rej09b0278-0210 i = 0 or 1 figure 20.14 serial interfa ce timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 20.15 external interrupt inti input timing diagram when v cc = 3 v table 20.26 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 20.27 external interrupt inti (i = 0, 1, 3) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 380 (1) ? ns t w(inl) inti input ?l? width 380 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v i = 0 or 1 inti input t w(inl) t w(inh) v cc = 3 v i = 0, 1, 3 r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 403 of 453 rej09b0278-0210 note: 1. v cc = 2.2 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), f(xin) = 5 mhz, unless otherwise specified. table 20.28 electrical characteristics (5) [v cc = 2.2 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p1_0 to p1_7, xout i oh = -1 ma v cc - 0.5 ? v cc v p1_0 to p1_7 drive capacity high i oh = -2 ma v cc - 0.5 ? v cc v drive capacity low i oh = -1 ma v cc - 0.5 ? v cc v xout drive capacity high i oh = -0.1 ma v cc - 0.5 ? v cc v drive capacity low i oh = -50 av cc - 0.5 ? v cc v v ol output ?l? voltage except p1_0 to p1_7, xout i ol = 1 ma ?? 0.5 v p1_0 to p1_7 drive capacity high i ol = 2 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.05 0.3 ? v reset 0.05 0.15 ? v i ih input ?h? current vi = 2.2 v ?? 4.0 a i il input ?l? current vi = 0 v ?? -4.0 a r pullup pull-up resistance vi = 0 v 100 200 600 k ? r fxin feedback resistance xin ? 5 ? m ? r fxcin feedback resistance xcin ? 35 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 404 of 453 rej09b0278-0210 table 20.29 electrical characteristics (6) [vcc = 2.2 v] (t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.2 to 2.7 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 3.5 ? ma xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 5 mhz low-speed on-chip oscillator on = 125 khz no division ? 3.5 ? ma xin clock off high-speed on-chip oscillator on foco = 5 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 100 230 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 100 230 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 25 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 22 60 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 20 55 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.0 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 1.8 ? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.7 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.1 ? a r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 405 of 453 rej09b0278-0210 timing requirements (unless otherwise specified: v cc = 2.2 v, v ss = 0 v at t opr = 25 c) [v cc = 2.2 v] figure 20.16 xin input and xcin input timing diagram when v cc = 2.2 v figure 20.17 traio input timing diagram when v cc = 2.2 v table 20.30 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 200 ? ns t wh(xin) xin input ?h? width 90 ? ns t wl(xin) xin input ?l? width 90 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 20.31 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 500 ? ns t wh(traio) traio input ?h? width 200 ? ns t wl(traio) traio input ?l? width 200 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 2.2 v traio input t c(traio) t wl(traio) t wh(traio) v cc = 2.2 v r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 406 of 453 rej09b0278-0210 i = 0 or 1 figure 20.18 serial interfa ce timing diagram when v cc = 2.2 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 20.19 external interrupt inti input timing diagram when v cc = 2.2 v table 20.32 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 800 ? ns t w(ckh) clki input ?h? width 400 ? ns t w(ckl) clki input ?l? width 400 ? ns t d(c-q) txdi output delay time ? 200 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 150 ? ns t h(c-d) rxdi input hold time 90 ? ns table 20.33 external interrupt inti (i = 0, 1, 3) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 1000 (1) ? ns t w(inl) inti input ?l? width 1000 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 2.2 v i = 0 or 1 inti input t w(inl) t w(inh) v cc = 2.2 v i = 0, 1, 3 r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 407 of 453 rej09b0278-0210 20.2 j, k version notes: 1. v cc = 2.7 to 5.5 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. the average output current indicates the av erage value of current measured during 100 ms. table 20.34 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage -0.3 to 6.5 v v i input voltage -0.3 to v cc + 0.3 v v o output voltage -0.3 to v cc + 0.3 v p d power dissipation -40 c t opr 85 c300mw 85 c t opr 125 c125mw t opr operating ambient temperature -40 to 85 (j version) / -40 to 125 (k version) c t stg storage temperature -65 to 150 c table 20.35 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 2.7 ? 5.5 v v ss /av ss supply voltage ? 0 ? v v ih input ?h? voltage 0.8 v cc ? v cc v v il input ?l? voltage 0 ? 0.2 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ?? -60 ma i oh(peak) peak output ?h? current ?? -10 ma i oh(avg) average output ?h? current ?? -5 ma i ol(sum) peak sum output ?l? currents sum of all pins i ol(peak) ?? 60 ma i ol(peak) peak output ?l? currents ?? 10 ma i ol(avg) average output ?l? current ?? 5ma f (xin) xin clock input oscillation frequency 3.0 v v cc 5.5 v (other than k version) 0 ? 20 mhz 3.0 v v cc 5.5 v (k version) 0 ? 16 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz ? system clock ocd2 = 0 xln clock selected 3.0 v v cc 5.5 v (other than k version) 0 ? 20 mhz 3.0 v v cc 5.5 v (k version) 0 ? 16 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz ocd2 = 1 on-chip oscillator clock selected fra01 = 0 low-speed on-chip oscillator clock selected ? 125 ? khz fra01 = 1 high-speed on-chip oscillator clock selected (other than k version) ?? 20 mhz fra01 = 1 high-speed on-chip oscillator clock selected ?? 10 mhz r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 408 of 453 rej09b0278-0210 notes: 1. av cc = 2.7 to 5.5 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. when the analog input voltage is over the reference voltage, t he a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. figure 20.20 ports p0, p1, and p3 to p5 timing measurement circuit table 20.36 a/d converter characteristics symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ?? 10 bits ? absolute accuracy 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 3 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 2 lsb 10-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 5 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 2 lsb r ladder resistor ladder v ref = av cc 10 ? 40 k ? t conv conversion time 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 3.3 ?? s 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 2.8 ?? s v ref reference voltage 2.7 ? av cc v v ia analog input voltage (2) 0 ? av cc v ? a/d operating clock frequency without sample and hold 0.25 ? 10 mhz with sample and hold 1 ? 10 mhz p0 p1 p3 p4 p5 30pf r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 409 of 453 rej09b0278-0210 notes: 1. v cc = 2.7 to 5.5 v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 1, 000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in bloc k a, a 1 kbyte block, and t hen the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. in a system that executes multiple prog ramming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possibl e is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of re writes can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erasure endurance of ea ch block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute th e clear status register command , then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information s hould contact their renesas tech nical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. table 20.37 flash memory (progr am rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) r8c/26 group 100 (3) ?? times r8c/27 group 1,000 (3) ?? times ? byte program time ? 50 400 s ? block erase time ? 0.4 9 s t d(sr-sus) time delay from suspend request until suspend ?? 97 + cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3 + cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.7 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ?? year r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 410 of 453 rej09b0278-0210 notes: 1. v cc = 2.7 to 5.5 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. standard of block a and block b when program and erase endurance exceeds 1,000 times. byte program time to 1,000 times is the same as that in program rom. 5. in a system that executes multiple prog ramming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possibl e is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of re writes can be minimized by programming up to 128 groups before erasing them all in one operati on. in addition, averaging the erasure endurance between blocks a and b can further reduce the actual erasure endurance. it is also advisable to retain data on the er asure endurance of each block and limit the number of erase operations to a certain number. 6. if an error occurs during block erase, attempt to execute th e clear status register command , then execute the block erase command at least three times until the erase error does not occur. 7. customers desiring program/erase failure rate information s hould contact their renesas tech nical support representative. 8. 125 c for k version. 9. the data hold time includes time that the power supply is off or the clock is not supplied. table 20.38 flash memory (data flash blo ck a, block b) electrical characteristics (4) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ?? times ? byte program time (program/erase endurance 1,000 times) ? 50 400 s ? byte program time (program/erase endurance > 1,000 times) ? 65 ? s ? block erase time (program/erase endurance 1,000 times) ? 0.2 9 s ? block erase time (program/erase endurance > 1,000 times) ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ?? 97 + cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3 + cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.7 ? 5.5 v ? program, erase temperature -40 ? 85 (8) c ? data hold time (9) ambient temperature = 55 c20 ?? year r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 411 of 453 rej09b0278-0210 figure 20.21 time de lay until suspend notes: 1. the measurement condition is v cc = 2.7 to 5.5 v and t opr = -40 to 85 c (j version) / -40 to 125 c (k version). 2. hold v det2 > v det1 . 3. necessary time until the voltage detecti on circuit operates when setti ng to 1 again after setting the vca26 bit in the vca2 register to 0. 4. this parameter shows the voltage detecti on level when the power supply drops. the voltage detection level when the power supply rises is hi gher than the voltage detection level when the power supply drops by approximately 0.1 v. 5. time until the voltage monitor 1 reset is generated after the voltage passes v det1 when v cc falls. when using the digital filter, its sampling time is added to t d(vdet1-a) . when using the voltage monitor 1 reset, maintain this time until v cc = 2.0 v after the voltage passes v det1 when the power supply falls. notes: 1. the measurement condition is v cc = 2.7 to 5.5 v and t opr = -40 to 85 c (j version) / -40 to 125 c (k version). 2. hold v det2 > v det1 . 3. time until the voltage monitor 2 reset/interr upt request is generated after the voltage passes v det2 . 4. necessary time until the voltage detection circuit operates after setting to 1 again after setting the vca27 bit in the vca2 register to 0. 5. when using the digital filter, its sampling time is added to t d(vdet2-a) . when using the voltage monitor 2 reset, maintain this time until v cc = 2.0 v after the voltage passes v det2 when the power supply falls. table 20.39 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level (2, 4) 2.70 2.85 3.0 v t d(vdet1-a) voltage monitor 1 reset generation time (5) ? 40 200 s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s vccmin mcu operating voltage minimum value 2.70 ?? v table 20.40 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level (2) 3.3 3.6 3.9 v t d(vdet2-a) voltage monitor 2 reset/interrupt request generation time (3, 5) ? 40 200 s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (4) ?? 100 s fmr46 suspend request (maskable interrupt request) fixed time t d(sr-sus) clock-dependent time access restart r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 412 of 453 rej09b0278-0210 notes: 1. the measurement condition is t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. this condition (the minimu m value of external power v cc rise gradient) does not apply if v por2 1.0 v. 3. to use the power-on reset function, enable voltage monitor 1 rese t by setting the lvd1on bit in the ofs register to 0, the vw1c0 and vw1c6 bits in the vw1c register to 1 respec tively, and the vca26 bit in the vca2 register to 1. 4. t w(por1) indicates the duration the external power v cc must be held below the effective voltage (v por1 ) to enable a power on reset. when turning on the power for the first time, maintain t w(por1) for 30 s or more if -20 c t opr 125 c, maintain t w(por1) for 3,000 s or more if -40 c t opr < -20 c. figure 20.22 reset circuit electrical characteristics table 20.41 power-on reset circuit, voltage monitor 1 reset electrical characteristics (3) symbol parameter condition standard unit min. typ. max. v por1 power-on reset valid voltage (4) ?? 0.1 v v por2 power-on reset or voltage monitor 1 reset valid voltage 0 ? v det1 v t rth external power v cc rise gradient v cc 3.6 v 20 (2) ?? mv/msec v cc > 3.6 v 20 (2) ? 2,000 mv/msec v det1 (3) v por1 internal reset signal (?l? valid) t w(por1) v det1 (3) v por2 32 1 f oco-s 32 1 f oco-s 2.0 v t rth t rth external power v cc notes: 1. when using the voltage monitor 1 digital filter, ensure vcc is 2.0 v or higher during the sampling time. 2. the sampling clock can be selected. refer to 6. voltage detection circuit for details. 3. v det1 indicates the voltage detection level of the voltage detection 1 circuit. refer to 6. voltage detection circuit for details. sampling time (1, 2) t d(vdet1-a) r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 413 of 453 rej09b0278-0210 notes: 1. v cc = 2.7 to 5.5 v, t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. these standard values show when the fra1 register value after reset is assumed. note: 1. v cc = 2.7 to 5.5 v, t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. notes: 1. the measurement condition is v cc = 2.7 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power su pply generation circuit stabilizes during power-on. 3. time until system clock supply starts after t he interrupt is acknowledged to exit stop mode. table 20.42 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco40m high-speed on-chip oscillator frequency temperature supply voltage dependence v cc = 4.75 to 5.25 v 0 c t opr 60 c (2) 39.2 40 40.8 mhz v cc = 3.0 to 5.5 v -20 c t opr 85 c (2) 38.8 40 41.2 mhz v cc = 3.0 to 5.5 v -40 c t opr 85 c (2) 38.4 40 41.6 mhz v cc = 3.0 to 5.5 v -40 c t opr 125 c (2) 38 40 42 mhz v cc = 2.7 to 5.5 v -40 c t opr 125 c (2) 37.6 40 42.4 mhz ? value in fra1 register after reset 08h ? f7h ? ? oscillation frequency adjustment unit of high- speed on-chip oscillator adjust fra1 register (value after reset) to -1 ? +0.3 ? mhz ? oscillation st ability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 400 ? a table 20.43 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 40 125 250 khz ? oscillation st ability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 15 ? a table 20.44 power supply circuit timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabiliz ation during power-on (2) 1 ? 2000 s t d(r-s) stop exit time (3) ?? 150 s r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 414 of 453 rej09b0278-0210 notes: 1. v cc = 2.7 to 5.5 v, v ss = 0 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. 1t cyc = 1/f1(s) table 20.45 timing requirements of clock synchronous serial i/o with chip select (1) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ?? t cyc (2) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ?? 1 t cyc (2) slave ?? 1 s t fall ssck clock falling time master ?? 1 t cyc (2) slave ?? 1 s t su sso, ssi data input setup time 100 ?? ns t h sso, ssi data input hold time 1 ?? t cyc (2) t lead scs setup time slave 1t cyc + 50 ?? ns t lag scs hold time slave 1t cyc + 50 ?? ns t od sso, ssi data output delay time ?? 1 t cyc (2) t sa ssi slave access time ?? 1.5t cyc + 100 ns t or ssi slave out open time ?? 1.5t cyc + 100 ns r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 415 of 453 rej09b0278-0210 figure 20.23 i/o timing of clock synchronous serial i/o with chip select (master) v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 416 of 453 rej09b0278-0210 figure 20.24 i/o timing of clock synchronous serial i/o with chip select (slave) v ih or v oh v ih or v oh scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 417 of 453 rej09b0278-0210 figure 20.25 i/o timing of clock synchronous serial i/o with chip select (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v ih or v oh r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 418 of 453 rej09b0278-0210 notes: 1. v cc = 2.7 to 5.5 v, v ss = 0 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified. 2. 1t cyc = 1/f1(s) figure 20.26 i/o timing of i 2 c bus interface table 20.46 timing requirements of i 2 c bus interface (1) symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ?? ns t sclh scl input ?h? width 3t cyc + 300 (2) ?? ns t scll scl input ?l? width 5t cyc + 500 (2) ?? ns t sf scl, sda input fall time ?? 300 ns t sp scl, sda input spike pulse rejection time ?? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ?? ns t stah start condition input hold time 3t cyc (2) ?? ns t stas retransmit start condition input setup time 3t cyc (2) ?? ns t stop stop condition input setup time 3t cyc (2) ?? ns t sdas data input setup time 1t cyc + 20 (2) ?? ns t sdah data input hold time 0 ?? ns sda t stah t scll t buf v ih v il t sclh scl t sr t sf t sdah t scl t stas t sp t stop t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. retransmit start condition r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 419 of 453 rej09b0278-0210 note: 1. v cc = 4.2 to 5.5 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), f(xin) = 20 mh z, unless otherwise specified. table 20.47 electrical characteristics (1) [v cc = 5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except xout i oh = -5 ma v cc - 2.0 ? v cc v i oh = -200 av cc - 0.3 ? v cc v xout drive capacity high i oh = -1 ma v cc - 2.0 ? v cc v drive capacity low i oh = -500 av cc - 2.0 ? v cc v v ol output ?l? voltage except xout i ol = 5 ma ?? 2.0 v i ol = 200 a ?? 0.45 v xout drive capacity high i ol = 1 ma ?? 2.0 v drive capacity low i ol = 500 a ?? 2.0 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.1 0.5 ? v reset 0.1 1.0 ? v i ih input ?h? current vi = 5 v, v cc = 5v ?? 5.0 a i il input ?l? current vi = 0 v, v cc = 5v ?? -5.0 a r pullup pull-up resistance vi = 0 v, v cc = 5v 30 50 167 k ? r fxin feedback resistance xin ? 1.0 ? m ? v ram ram hold voltage during stop mode 2.0 ?? v r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 420 of 453 rej09b0278-0210 table 20.48 electrical characteristics (2) [vcc = 5 v] (t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 10 17 ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 915ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6 ? ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 5 ? ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 20 mhz (j version) low-speed on-chip oscillator on = 125 khz no division ? 10 15 ma xin clock off high-speed on-chip oscillator on foco = 20 mhz (j version) low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 5.5 10 ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 130 300 a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 25 75 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 23 60 a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.8 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.2 ? a xin clock off, t opr = 125 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 4.0 ? a r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 421 of 453 rej09b0278-0210 timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v at t opr = 25 c) [v cc = 5 v] figure 20.27 xin input timing diagram when v cc = 5 v figure 20.28 traio input timing diagram when v cc = 5 v table 20.49 xin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input ?h? width 25 ? ns t wl(xin) xin input ?l? width 25 ? ns table 20.50 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 5 v traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio) r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 422 of 453 rej09b0278-0210 i = 0 or 1 figure 20.29 serial interfa ce timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 20.30 external interrupt inti input timing diagram when v cc = 5 v table 20.51 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 20.52 external interrupt inti (i = 0, 1, 3) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 250 (1) ? ns t w(inl) inti input ?l? width 250 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0 or 1 v cc = 5 v inti input t w(inl) t w(inh) i = 0, 1, 3 v cc = 5 v r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 423 of 453 rej09b0278-0210 note: 1. v cc = 2.7 to 3.3 v at t opr = -40 to 85 c (j version) / -40 to 125 c (k version), f(xin) = 10 mh z, unless otherwise specified. table 20.53 electrical characteristics (3) [v cc = 3 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except xout i oh = -1 ma v cc - 0.5 ? v cc v xout drive capacity high i oh = -0.1 ma v cc - 0.5 ? v cc v drive capacity low i oh = -50 av cc - 0.5 ? v cc v v ol output ?l? voltage except xout i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0,clk1, ssi, scl, sda, sso 0.1 0.3 ? v reset 0.1 0.4 ? v i ih input ?h? current vi = 3 v, v cc = 3v ?? 4.0 a i il input ?l? current vi = 0 v, v cc = 3v ?? -4.0 a r pullup pull-up resistance vi = 0 v, v cc = 3v 66 160 500 k ? r fxin feedback resistance xin ? 3.0 ? m ? v ram ram hold voltage during stop mode 2.0 ?? v r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 424 of 453 rej09b0278-0210 table 20.54 electrical characteristics (4) [vcc = 3 v] (t opr = -40 to 85 c (j version) / -40 to 125 c (k version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 59ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 130 300 a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 25 70 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 23 55 a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.7 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.1 ? a xin clock off, t opr = 125 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 3.8 ? a r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 425 of 453 rej09b0278-0210 timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v at t opr = 25 c) [v cc = 3 v] figure 20.31 xin input timing diagram when v cc = 3 v figure 20.32 traio input timing diagram when v cc = 3 v table 20.55 xin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 100 ? ns t wh(xin) xin input ?h? width 40 ? ns t wl(xin) xin input ?l? width 40 ? ns table 20.56 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 3 v traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio) r8c/26 group, r8c/27 group 20. electrical characteristics rev.2.10 sep 26, 2008 page 426 of 453 rej09b0278-0210 i = 0 or 1 figure 20.33 serial interfa ce timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 20.34 external interrupt inti input timing diagram when v cc = 3 v table 20.57 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 20.58 external interrupt inti (i = 0, 1, 3) input symbol parameter standard unit min. max. t w(inh) inti input ?h? width 380 (1) ? ns t w(inl) inti input ?l? width 380 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v i = 0 or 1 inti input t w(inl) t w(inh) v cc = 3 v i = 0, 1, 3 r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 427 of 453 rej09b0278-0210 21. usage notes 21.1 notes on clock generation circuit 21.1.1 stop mode when entering stop mode, set the fmr01 bit in the fmr0 register to 0 (cpu rewrite mode disabled) and the cm10 bit in the cm1 register to 1 (stop mode). an instruction queue pre-reads 4 bytes from the instruction which sets the cm10 bit to 1 (stop mode) and the program stops. insert at least 4 nop instructions following the jmp.b instruction after the instruction which sets the cm10 bit to 1. ? program example to enter stop mode bclr 1,fmr0 ; cpu rewrite mode disabled bset 0,prcr ; protect disabled fset i ; enable interrupt bset 0,cm1 ; stop mode jmp.b label_001 label_001 : nop nop nop nop 21.1.2 wait mode when entering wait mode, set the fmr01 bit in the fm r0 register to 0 (cpu re write mode disabled) and execute the wait instruction. an instruction queue pre-reads 4 bytes from the wait instruction and the program stops. insert at least 4 nop instructions after the wait instruction. ? program example to execute the wait instruction bclr 1,fmr0 ; cpu rewrite mode disabled fset i ; enable interrupt wait ; wait mode nop nop nop nop 21.1.3 oscillation stop detection function since the oscillation stop detection function cannot be used if the xin clock frequency is 2 mhz or below, set bits ocd1 to ocd0 to 00b. 21.1.4 oscillation circuit constants ask the manufacturer of the oscillator to specify th e best oscillation circuit constants for your system. to use this mcu with supply voltage below vcc = 2.7 v, it is recommended to set the cm11 bit in the cm1 register to 1 (on-chip feedback resistor disabled), the cm15 bit to 1 (high drive capacity), and connect the feedback resistor to the chip externally. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 428 of 453 rej09b0278-0210 21.2 notes on interrupts 21.2.1 reading address 00000h do not read address 00000h by a program. when a mask able interrupt request is acknowledged, the cpu reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. at this time, the acknowledged interrupt ir bit is set to 0. if address 00000h is read by a program, the ir bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. this may cause the interrupt to be cancel ed, or an unexpected interrupt to be generated. 21.2.2 sp setting set any value in the sp before an interrupt is acknowledged. the sp is set to 0000h afte r reset. therefore, if an interrupt is acknowledged before setting a value in the sp, the program may run out of control. 21.2.3 external interrupt and key input interrupt either ?l? level or an ?h? le vel of width shown in the el ectrical characteristics is ne cessary for the signal input to pins int0 , int1 , int3 and pins ki0 to ki3 , regardless of the cpu clock. for details, refer to table 20.21 (vcc = 5v), table 20.27 (vcc = 3v), table 20.3 3 (vcc = 2.2v), table 20.52 (vcc = 5v), ta bl e 2 0.5 8 (vcc = 3v) external interrupt inti (i = 0, 1, 3) input . r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 429 of 453 rej09b0278-0210 21.2.4 changing interrupt sources the ir bit in the interrupt control register may be se t to 1 (interrupt requested) when the interrupt source changes. when using an interrupt, set the ir bit to 0 (n o interrupt requested) after changing the interrupt source. in addition, changes of interrupt so urces include all factors that change the interr upt sources assigned to individual software interrupt numbers, polarities, and timing. therefore, if a mode change of a peripheral function involves interrupt sources, edge polarities, and ti ming, set the ir bit to 0 (no interrupt requested) after the change. refer to the individual periph eral function for its related interrupts. figure 21.1 shows an exam ple of procedure for changing interrupt sources. figure 21.1 example of procedure for changing interrupt sources notes: 1. execute the above settings i ndividually. do not execute two or more settings at once (by one instruction). 2. to prevent interrupt request s from being generated, disable the peripheral function before changing the interrupt source. in this case, use the i flag if all maskable interrupts can be disabled. if all maskable interrupts cannot be disabled, use bits ilvl0 to ilvl2 of the interrupt whose source is changed. 3. refer to 12.6.5 changing interrupt control register contents for the instructions to be used and usage notes. interrupt source change disable interrupts (2, 3) set the ir bit to 0 (interrupt not requested) using the mov instruction (3) change interrupt source (including mode of peripheral function) enable interrupts (2, 3) change completed ir bit: the interrupt control register bit of an interrupt whose source is changed. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 430 of 453 rej09b0278-0210 21.2.5 changing interrupt c ontrol regist er contents (a) the contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. if in terrupt requests may be generated, disable interrupts before changing the interrupt control register contents. (b) when changing the contents of an interrupt contro l register after disabling interrupts, be careful to choose appropriate instructions. changing any bit other than ir bit if an interrupt request corresponding to a register is generated while executing the instruction, the ir bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. if this causes a problem, use the following instructions to change the register : and, or, bclr, bset changing ir bit if the ir bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used. therefore, use the mov instruct ion to set the ir bit to 0. (c) when disabling interrupts using the i flag, set the i flag as shown in the sample programs below. refer to (b) regarding changing the contents of interrupt control registers by the sample programs. sample programs 1 to 3 are for preventi ng the i flag from being set to 1 (interrupts enabled) before the interrupt control register is changed for reasons of the internal bus or the instruction queue buffer. example 1: use nop instructions to prevent i flag from being set to 1 before interrupt control register is changed int_switch1: fclr i ; disable interrupts and.b #00h,0056h ; set traic register to 00h nop ; nop fset i ; enable interrupts example 2: use dummy read to delay fset instruction int_switch2: fclr i ; disable interrupts and.b #00h,0056h ; set traic register to 00h mov.w mem,r0 ; dummy read fset i ; enable interrupts example 3: use popc instruction to change i flag int_switch3: pushc flg fclr i ; disable interrupts and.b #00h,0056h ; set traic register to 00h popc flg ; enable interrupts r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 431 of 453 rej09b0278-0210 21.3 notes on timers 21.3.1 notes on timer ra ? timer ra stops counting after a rese t. set the values in the timer ra and timer ra prescalers before the count starts. ? even if the prescaler and timer ra are read out in 16- bit units, these registers are read 1 byte at a time by the mcu. consequently, the timer va lue may be updated during the period when these two registers are being read. ? in pulse period measurement mode, bits tedgf and tundf in the tracr register can be set to 0 by writing 0 to these bits by a program. however, these b its remain unchanged if 1 is written. when using the read-modify-write instruction for the tracr regi ster, the tedgf or tundf bit may be set to 0 although these bits are set to 1 while the instruction is being executed. in this case, write 1 to the tedgf or tundf bit which is not supposed to be set to 0 with the mov instruction. ? when changing to pulse period m easurement mode from another mode, the contents of bits tedgf and tundf are undefined. write 0 to bits tedgf and tundf before the count starts. ? the tedgf bit may be set to 1 by the first timer ra prescaler underflow generate d after the count starts. ? when using the pulse period measur ement mode, leave two or more periods of the timer ra prescaler immediately after the count starts, then set the tedgf bit to 0. ? the tcstf bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the tstart bit to 1 (count starts) while the count is stopped. during this time, do not access registers associated with timer ra (1) other than the tcstf bit. timer ra starts counting at the first valid edge of the count source after the tcstf bit is set to 1 (during count). the tcstf bit remains 1 for 0 to 1 cycle of the count source after setting the tstart bit to 0 (count stops) while the count is in progress. timer ra c ounting is stopped when the tcstf bit is set to 0. during this time, do not access re gisters associated with timer ra (1) other than the tcstf bit. note: 1. registers associated with timer ra : tracr, traioc, tramr, trapre, and tra. ? when the trapre register is continuously written during count operation (tcstf bit is set to 1), allow three or more cycles of the count source clock for each write interval. ? when the tra register is continuously written during count operation (tcstf bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 432 of 453 rej09b0278-0210 21.3.2 notes on timer rb ? timer rb stops counting after a reset. set the values in the timer rb and timer rb prescalers before the count starts. ? even if the prescaler and timer rb is read out in 16-bit units, these registers are read 1 byte at a time by the mcu. consequently, the timer value may be updated during the period when these two registers are being read. ? in programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the tstart bit in the trbcr register to 0, 0 (stops counting) or setting the tossp bit in the trbocr register to 1 (stops one-shot), the timer reload s the value of reload register and stops. therefore, in programmable one-shot generation mode and prog rammable wait one-shot generation mode, read the timer count value before the timer stops. ? the tcstf bit remains 0 (count stops) for 1 to 2 cycl es of the count source after setting the tstart bit to 1 (count starts) while the count is stopped. during this time, do not access re gisters associated with timer rb (1) other than the tcstf bit. timer rb starts counting at the first valid edge of the count source after the tcstf bit is set to 1 (during count). the tcstf bit remains 1 for 1 to 2 cycles of the count source after setting the tstart bit to 0 (count stops) while the count is in progress. timer rb count ing is stopped when the tcstf bit is set to 0. during this time, do not access re gisters associated with timer rb (1) other than the tcstf bit. note: 1. registers associated with timer rb: trbcr, trbocr, trbioc, trbmr, trbpre, trbsc, and trbpr. ? if the tstop bit in the trbcr register is set to 1 during timer operation, timer rb stops immediately. ? if 1 is written to the tosst or tossp bit in the t rbocr register, the value of the tosstf bit changes after one or two cycles of the count source have elapsed. if the tossp bit is written to 1 during the period between when the tosst bit is written to 1 and when the tosstf bit is set to 1, the tosstf bit may be set to either 0 or 1 depending on the content state. likewise, if the tosst bit is written to 1 during the period between when the tossp bit is written to 1 and when th e tosstf bit is set to 0, the tosstf bit may be set to either 0 or 1. 21.3.2.1 timer mode the following workaround should be performed in timer mode. to write to registers trbpre and trbpr during count operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously, allow th ree or more cycles of the count source for each write interval. ? when the trbpr register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 433 of 453 rej09b0278-0210 21.3.2.2 programmable waveform generation mode the following three workarounds should be performe d in programmable waveform generation mode. (1) to write to registers trbpre and trbpr during c ount operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously, allow th ree or more cycles of the count source for each write interval. ? when the trbpr register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. (2) to change registers trbpre and trbpr during coun t operation (tcstf bit is set to 1), synchronize the trbo output cycle using a timer rb interrupt, etc. this operation should be preformed only once in the same output cycle. also, make sure that writi ng to the trbpr register does not occur during period a shown in figures 21.2 and 21.3. the following shows the detailed workaround examples. ? workaround example (a): as shown in figure 21.2, write to registers trbsc and trbpr in the timer rb interrupt routine. these write operations must be completed by the beginning of period a. figure 21.2 workaround example (a) when timer rb interrupt is used trbo pin output count source/ prescaler underflow signal primary period period a ir bit in trbic register secondary period (b) interrupt sequence instruction in interrupt routine interrupt request is acknowledged (a) interrupt request is generated ensure sufficient time set the secondary and then the primary register immediately (a) period between interrupt request generation and the completion of execution of an instruction. the length of time varies depending on the instruction being executed. the divx instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 20 cycles. 21 cycles for address match and single-step interrupts. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 434 of 453 rej09b0278-0210 ? workaround example (b): as shown in figure 21.3 detect the start of the pr imary period by the trbo pin output level and write to registers trbsc and trbpr. these write operations must be completed by the beginning of period a. if the port register?s bit value is read after the port direction register?s bit corresponding to the trbo pin is set to 0 (input mode), the read value indicates the trbo pin output value. figure 21.3 workaround example (b) when trbo pin output value is read (3) to stop the timer counting in the primary period, use the tstop bit in the trbcr register. in this case, registers trbpre and trbpr are initialized and th eir values are set to the values after reset. 21.3.2.3 programmable one-shot generation mode the following two workarounds should be performe d in programmable one-shot generation mode. (1) to write to registers trbpre and trbpr during c ount operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously du ring count operation (tcstf bit is set to 1), allow three or more cycles of the co unt source for each write interval. ? when the trbpr register is written continuously du ring count operation (tcstf bit is set to 1), allow three or more cycles of the prescal er underflow for each write interval. (2) do not set both the trbpre and trbpr registers to 00h. trbo pin output count source/ prescaler underflow signal primary period period a read value of the port register?s bit corresponding to the trbo pin (when the bit in the port direction register is set to 0) secondary period (i) the trbo output inversion is detected at the end of the secondary period. ensure sufficient time upon detecting (i), set the secondary and then the primary register immediately. (ii) (iii) r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 435 of 453 rej09b0278-0210 21.3.2.4 programmable wait one-shot generation mode the following three workarounds should be performe d in programmable wait one-shot generation mode. (1) to write to registers trbpre and trbpr during c ount operation (tcstf bit is set to 1), note the following points: ? when the trbpre register is written continuously, allow th ree or more cycles of the count source for each write interval. ? when the trbpr register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. (2) do not set both the trbpre and trbpr registers to 00h. (3) set registers trbsc and trbpr using the following procedure. (a) to use ?int0 pin one-shot trigger enabled? as the count start condition set the trbsc register an d then the trbpr register. at this time, after writing to the trbpr register, allow an interval of 0.5 or more cycles of the count source before trigger input from the int0 pin. (b) to use ?writing 1 to tosst bit? as the start condition set the trbsc register, the trbpr register, and then tosst bit. at this time, after writing to the trbpr register, allow an interval of 0.5 or more cycles of the count source before writing to the tosst bit. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 436 of 453 rej09b0278-0210 21.3.3 notes on timer rc 21.3.3.1 trc register ? the following note applies when the cclr bit in the trccr1 register is set to 1 (clear trc register at compare match with trcgra register). when using a program to write a value to the trc regi ster while the tstart bit in the trcmr register is set to 1 (count starts), ensure that the write does not overlap with the timing with which the trc register is set to 0000h. if the timing of the write to the trc register and th e setting of the trc register to 0000h coincide, the write value will not be written to the trc regist er and the trc register will be set to 0000h. ? reading from the trc register immedi ately after writing to it can result in the value previous to the write being read out. to prevent this, execute the jmp.b inst ruction between the read a nd the write instructions. program example mov.w #xxxxh, trc ;write jmp.b l1 ;jmp.b instruction l1: mov.w trc,data ;read 21.3.3.2 trcsr register reading from the trcsr register immediately after writin g to it can result in the value previous to the write being read out. to prevent this, execute the jmp.b inst ruction between the read and the write instructions. program example mov.b #xxh, trcsr ;write jmp.b l1 ;jmp.b instruction l1: mov.b trcsr,data ;read 21.3.3.3 count source switching ? stop the count before switching the count source. switching procedure (1) set the tstart bit in the trcmr register to 0 (count stops). (2) change the settings of bits tck2 to tck0 in the trccr1 register. ? after switching the count source from foco40m to anot her clock, allow a minimum of two cycles of f1 to elapse after changing the clock setting before stopping foco40m. switching procedure (1) set the tstart bit in the trcmr register to 0 (count stops). (2) change the settings of bits tck2 to tck0 in the trccr1 register. (3) wait for a minimum of two cycles of f1. (4) set the fra00 bit in the fra0 register to 0 (high-speed on-chip oscillator off). 21.3.3.4 input capture function ? the pulse width of the input capture signal should be three cycles or more of the timer rc operation clock (refer to table 14.11 timer rc operation clock ). ? the value of the trc register is transferred to th e trcgrj register one or two cycles of the timer rc operation clock after the input capture signal is input to the trcioj (j = a, b, c, or d) pin (when the digital filter function is not used). 21.3.3.5 trcmr regist er in pwm2 mode when the csel bit in the trccr2 register is set to 1 (count stops at compare match with the trcgra register), do not set the trcmr register at co mpare match timing of registers trc and trcgra. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 437 of 453 rej09b0278-0210 21.3.4 notes on timer re 21.3.4.1 starting and stopping count timer re has the tstart bit for instructing the count to start or stop, and the tcstf bit, which indicates count start or stop. bits tstart an d tcstf are in the trecr1 register. timer re starts counting and the tcstf bit is set to 1 (count starts) when the tstart bit is set to 1 (count starts). it takes up to 2 cycles of the count source until the tcstf bit is set to 1 after setting the tstart bit to 1. during this time, do not access re gisters associated with timer re (1) other than the tcstf bit. also, timer re stops counting when setting the tstart bit to 0 (count stops) and the tcstf bit is set to 0 (count stops). it takes the time for up to 2 cycles of the count source until the tcstf bit is set to 0 after setting the tstart bit to 0. during this ti me, do not access registers associated with timer re other than the tcstf bit. note: 1. registers associated with timer re: tresec, tremin, trehr, trewk, trecr1, trecr2, and trecsr. 21.3.4.2 register setting write to the following registers or bits when timer re is stopped. ? registers tresec, tremin, trehr, trewk, and trecr2 ? bits h12_h24, pm, and int in trecr1 register ? bits rcs0 to rcs3 in trecsr register timer re is stopped when bits tstart and tcstf in the trecr1 register are set to 0 (timer re stopped). also, set all above-mentioned registers and bits (immedia tely before timer re count starts) before setting the trecr2 register. figure 21.4 shows a setting example in real-time clock mode. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 438 of 453 rej09b0278-0210 figure 21.4 setting example in real-time clock mode stop timer re operation tcstf in trecr1 = 0? tstart in trecr1 = 0 trerst in trecr1 = 1 trerst in trecr1 = 0 setting of registers trecsr, tresec, tremin, trehr, trewk, and bits h12_h24, pm, and int in trecr1 register setting of trecr2 tstart in trecr1 = 1 tcstf in trecr1 = 1? treic 00h (disable timer re interrupt) setting of treic (ir bit 0, select interrupt priority level) timer re register and control circuit reset select clock output select clock source seconds, minutes, hours, days of week, operating mode set a.m./p.m., interrupt timing select interrupt source start timer re operation r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 439 of 453 rej09b0278-0210 21.3.4.3 time reading proce dure of real-time clock mode in real-time clock mode, read registers tresec, tr emin, trehr, and trewk wh en time data is updated and read the pm bit in the trecr1 register when th e bsy bit is set to 0 (not while data is updated). also, when reading several registers, an incorrect time will be r ead if data is updated before another register is read after reading any register. in order to prevent this, use the reading procedure shown below. ? using an interrupt read necessary contents of regi sters tresec, tremin, trehr, a nd trewk and the pm bit in the trecr1 register in the timer re interrupt routine. ? monitoring with a program 1 monitor the ir bit in the treic regi ster with a program and read necessa ry contents of registers tresec, tremin, trehr, and trewk and the pm bit in the trecr1 register after the ir bit in the treic register is set to 1 (timer re interrupt request generated). ? monitoring with a program 2 (1) monitor the bsy bit. (2) monitor until the bsy bit is set to 0 after the bsy bit is set to 1 (approximately 62.5 ms while the bsy bit is set to 1). (3) read necessary contents of re gisters tresec, tremin, trehr, and trewk and the pm bit in the trecr1 register after the bsy bit is set to 0. ? using read results if they are the same value twice (1) read necessary contents of re gisters tresec, tremin, trehr, and trewk and the pm bit in the trecr1 register. (2) read the same register as (1) and compare the contents. (3) recognize as the correct value if th e contents match. if the contents do not match, repeat until the read contents match with th e previous contents. also, when reading several registers, r ead them as continuously as possible. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 440 of 453 rej09b0278-0210 21.4 notes on serial interface ? when reading data from the uirb (i = 0 or 1) register eith er in the clock synchronous serial i/o mode or in the clock asynchronous serial i/o mode. ensu re the data is read in 16-bit units. when the high-order byte of the uirb register is read, bits per and fe r in the uirb register and the ri bit in the uic1 register are set to 0. to check receive errors, read the uirb register and then use the read data. example (when reading r eceive buffer register): mov.w 00a6h,r0 ; read the u0rb register ? when writing data to the uitb register in the clock asynchronous serial i/o mode with 9-bit transfer data length, write data to the high-order byte first then the low-order byte, in 8-bit units. example (when reading tran smit buffer register): mov.b #xxh,00a3h ; write the high-order byte of u0tb register mov.b #xxh,00a2h ; write the low-order byte of u0tb register r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 441 of 453 rej09b0278-0210 21.5 notes on clock sync hronous serial interface 21.5.1 notes on clock synchronous serial i/o with chip select set the iicsel bit in the pmr register to 0 (select clock synchronous serial i/o with chip select function) to use the clock synchronous serial i/o with chip select function. 21.5.2 notes on i 2 c bus interface set the iicsel bit in the pmr register to 1 (select i 2 c bus interface function) to use the i 2 c bus interface. 21.5.2.1 multimaster operation the following actions must be performed to use the i 2 c bus interface in multimaster operation. ? transfer rate set the transfer rate by 1/1.8 or faster than the fastes t rate of the other masters. for example, if the fastest transfer rate of the other masters is set to 400 kbps, the i 2 c-bus transfer rate in this mcu should be set to 223 kbps (= 400/1.18) or more. ? bits mst and trs in the iccr1 register setting (a) use the mov instruction to set bits mst and trs. (b) when arbitration is lost, confirm the contents of b its mst and trs. if the contents are other than the mst bit set to 0 and the trs bit set to 0 (slave recei ve mode), set the mst bit to 0 and the trs bit to 0 again. 21.5.2.2 master receive mode either of the following actions must be performed to use the i 2 c bus interface in ma ster receive mode. (a) in master receive mode while the rdrf bit in the icsr register is set to 1, read the icdrr register before the rising edge of the 8th clock. (b) in master receive mode, set the rcvd bit in th e iccr1 register to 1 (disables the next receive operation) to perform 1-byte communications. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 442 of 453 rej09b0278-0210 21.6 notes on hardware lin for the time-out processing of the head er and response fields, use another timer to measure the duration of time with a synch break detection interrupt as the starting point. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 443 of 453 rej09b0278-0210 21.7 notes on a/d converter ? write to each bit (other th an bit 6) in the adcon0 register, each b it in the adcon1 register, or the smp bit in the adcon2 register when a/d conversi on is stopped (before a trigger occurs). when the vcut bit in the adcon1 register is changed from 0 (vref no t connected) to 1 (vref connected), wait for at least 1 s before starting the a/d conversion. ? after changing the a/d operating mode, select an analog input pin again. ? when using the one-shot mode, ensure that a/d conversion is completed before reading the ad register. the ir bit in the adic register or the adst bit in the ad con0 register can be used to determine whether a/d conversion is completed. ? when using the repeat mode, select the fr equency of the a/d converter operating clock ad or more for the cpu clock during a/d conversion. ? if the adst bit in the adcon0 register is set to 0 (a /d conversion stops) by a program and a/d conversion is forcibly terminated duri ng an a/d conversion operatio n, the conversion result of the a/d converter will be undefined. if the adst bit is set to 0 by a program, do not use the value of the ad register. ? connect 0.1 f capacitor between the p4_2 /vref pin and avss pin. ? do not enter stop mode during a/d conversion. ? do not enter wait mode when the cm02 bit in the cm0 re gister is set to 1 (peripheral function clock stops in wait mode) during a/d conversion. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 444 of 453 rej09b0278-0210 21.8 notes on flash memory 21.8.1 cpu rewrite mode 21.8.1.1 operating speed before entering cpu rewrite mode (ew0 mode), select 5 mhz or below for the cpu clock using the cm06 bit in the cm0 register and bits cm16 to cm17 in the cm1 register. this does not apply to ew1 mode. 21.8.1.2 prohibited instructions the following instru ctions cannot be used in ew0 mode because th ey reference internal data in flash memory: und, into, and brk. 21.8.1.3 interrupts table 21.1 lists the ew0 mode interrupts and table 21.2 lists the ew1 mode interrupt. notes: 1. do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in rom. 2. do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0. table 21.1 ew0 mode interrupts mode status when maskable interrupt request is acknowledged when watchdog timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2 interrupt request is acknowledged ew0 during auto-erasure any interrupt can be used by allocating a vector in ram once an interrupt request is acknowledged, the auto-programming or auto-erasure is forcibly stopped immediately and the flash memory is reset. interrupt handling starts after the fixed period and the flash memory restarts. since the block during auto- erasure or the address during auto- programming is forcibly stopped, the normal value may not be read. execute auto-erasure again and ensure it completes normally. since the watchdog timer does not stop during the command operation, interrupt requests may be generated. reset the watchdog timer regularly. auto-programming r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 445 of 453 rej09b0278-0210 notes: 1. do not use the address match interrupt while a command is executing because the vector of the address match interrupt is allocated in rom. 2. do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0. table 21.2 ew1 mode interrupt mode status when maskable interrupt request is acknowledged when watchdog timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2 interrupt request is acknowledged ew1 during auto-erasure (erase-suspend function enabled) auto-erasure is suspended after td(sr-sus) and interrupt handling is executed. auto- erasure can be restarted by setting the fmr41 bit in the fmr4 register to 0 (erase restart) after interrupt handling completes. once an interrupt request is acknowledged, auto-programming or auto-erasure is fo rcibly stopped immediately and the flash memory is reset. interrupt handling starts after the fixed period and the flash memory restarts. since the block during auto- erasure or the address during auto- programming is forcibly stopped, the normal value may not be read. execute auto-erasure again and ensure it completes normally. since the watchdog timer does not stop during the command operation, interrupt requests may be generated. reset the watchdog timer regularly using the erase-suspend function. during auto-erasure (erase-suspend function disabled) auto-erasure has priority and the interrupt request acknowledgement is put on standby. interrupt handling is executed after auto-erasure completes. during auto- programming (program suspend function enabled) auto-programming is suspended after td(sr-sus) and interrupt handling is executed. auto-programming can be restarted by setting the fmr42 bit in the fmr4 register to 0 (program restart) after interrupt handling completes. during auto- programming (program suspend function disabled) auto-programming has priority and the interrupt request acknowledgement is put on standby. interrupt handling is executed after auto-programming completes. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 446 of 453 rej09b0278-0210 21.8.1.4 how to access write 0 before writing 1 when setting the fmr01, fmr02, or fmr11 bit to 1. do not generate an interrupt between writing 0 and 1. 21.8.1.5 rewriting user rom area in ew0 mode, if the supply voltage drops while rewr iting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. in this case, use standard serial i/o mode. 21.8.1.6 program do not write additions to th e already programmed address. 21.8.1.7 entering stop mode or wait mode do not enter stop mode or wait mode during erase-suspend. 21.8.1.8 program and erase voltage for flash memory to perform programming and erasure, use vcc = 2.7 to 5.5 v as the supply voltage. do not perform programming and erasure at less than 2.7 v. r8c/26 group, r8c/27 group 21. usage notes rev.2.10 sep 26, 2008 page 447 of 453 rej09b0278-0210 21.9 notes on noise 21.9.1 inserting a bypass capacitor between vcc and vss pins as a countermeasure against noise and latch-up connect a bypass capacitor (at least 0.1 f) using the shortest and thickest write possible. 21.9.2 countermeasures against noise er ror of port control registers during rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the capacity of the mcu's internal noise control circuitry. in such cases the contents of the port related registers may be changed. as a firmware countermeasure, it is recommended that the port registers, port direc tion registers, and pull-up control registers be reset periodically. however, examin e the control processing fully before introducing the reset routine as conflicts may be created betw een the reset routine and interrupt routines. r8c/26 group, r8c/27 group 22. notes for on-chip debugger rev.2.10 sep 26, 2008 page 448 of 453 rej09b0278-0210 22. notes for on-chip debugger when using the on-chip debugger to develop and debug pr ograms for the r8c/26 group and r8c/27 group take note of the following. (1) do not access the registers associated with uart1. (2) some of the user flash memory and ram areas ar e used by the on-ship debugger. these areas cannot be accessed by the user. refer to the on-chip debugger manual for which areas are used. (3) do not set the address match interrupt (registers aier, rmad0, and rmad1 and fixed vector tables) in a user system. (4) do not use the brk instruction in a user system. (5) debugging is available under the condition of supply voltage vcc = 2.7 to 5.5 v. debugging with the on-chip debugger under less than 2.7 v is not allowed. connecting and using the on-chip debugger has some special restrictions. refer to the on-chip debugger manual for details. r8c/26 group, r8c/27 group appendix 1. package dimensions rev.2.10 sep 26, 2008 page 449 of 453 rej09b0278-0210 appendix 1. package dimensions diagrams showing the latest package dimensions and mounti ng information are available in the ?packages? section of the renesas technology website. 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark * 3 f 32 25 24 17 16 9 8 1 * 1 * 2 x b p e h e e d h d z d z e detail f l 1 l a c a 2 a 1 previous code jeita package code renesas code plqp0032gb-a 32p6u-a mass[typ.] 0.2g p-lqfp32-7x7-0.80 1.0 0.125 0.35 0.7 0.7 0.20 0.20 0.145 0.09 0.42 0.37 0.32 max nom min dimension in millimeters symbol reference 7.1 7.0 6.9 d 7.1 7.0 6.9 e 1.4 a 2 9.2 9.0 8.8 9.2 9.0 8.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section b 1 c 1 bp c r8c/26 group, r8c/27 group appendix 2. connection examples between serial writer and on-chip debugging emulator rev.2.10 sep 26, 2008 page 450 of 453 rej09b0278-0210 appendix 2. connection examples b etween serial writer and on-chip debugging emulator appendix figure 2.1 shows a connection example with m16c flash starter (m3a-0806) and appendix figure 2.2 shows a connection example with e8 emulator (r0e000080kce00). appendix figure 2.1 connection example with m16c flash starter (m3a-0806) appendix figure 2.2 connection example with e8 emulator (r0e000080kce00) note: 1. an oscillation circuit must be connected, even when operating with the on-chip oscillator clock. rxd 4 7 vss 1 vcc 10 m16c flash starter (m3a-0806) rxd txd vss vcc txd reset mode connect oscillation circuit (1) 29 28 27 26 25 32 31 30 9 10 11 12 13 14 15 16 5 7 8 1 2 3 4 6 24 23 22 21 20 19 18 17 r8c/26 group r8c/27 group note: 1. it is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock. mode e8 emulator (r0e000080kce00) reset 12 10 8 6 4 2 vss 13 7 mode vcc 14 vss vcc connect oscillation circuit (1) 29 28 27 26 25 32 31 30 9 10 11 12 13 14 15 16 5 7 8 1 2 3 4 6 24 23 22 21 20 19 18 17 r8c/26 group r8c/27 group 4.7k ? 10% 4.7k ? or more open collector buffer user logic r8c/26 group, r8c/27 group a ppendix 3. example of osc illation evaluation circuit rev.2.10 sep 26, 2008 page 451 of 453 rej09b0278-0210 appendix 3. example of osc illation evaluation circuit appendix figure 3.1 shows an example of oscillation evaluation circuit. appendix figure 3.1 example of oscillation evaluation circuit connect oscillation circuit note: 1. after reset, the xin and xcin clocks stop. write a program to oscill ate the xin and xcin clocks. vss vcc reset 29 28 27 26 25 32 31 30 9 10 11 12 13 14 15 16 5 7 8 1 2 3 4 6 24 23 22 21 20 19 18 17 r8c/26 group r8c/27 group rev.2.10 sep 26, 2008 page 452 of 453 rej09b0278-0210 r8c/26 group, r8c/27 group index [ a ] ad ....................................................................................... 341 adcon0 ............................................................................. 340 adcon1 ............................................................................. 341 adcon2 ............................................................................. 341 adic .................................................................................... 115 aier .................................................................................... 130 [ c ] cm0 ....................................................................................... 81 cm1 ....................................................................................... 82 cpsrf .................................................................................. 86 cspr .................................................................................. 138 [ f ] fmr0 .................................................................................. 361 fmr1 .................................................................................. 362 fmr4 .................................................................................. 363 fra0 ..................................................................................... 84 fra1 ..................................................................................... 84 fra2 ..................................................................................... 85 fra4 ..................................................................................... 85 fra6 ..................................................................................... 85 fra7 ..................................................................................... 85 [ i ] iccr1 ................................................................................. 293 iccr2 ................................................................................. 294 icdrr ................................................................................. 298 icdrs ................................................................................. 298 icdrt ................................................................................. 298 icier ................................................................................... 296 icmr ................................................................................... 295 icsr .................................................................................... 297 iicic .................................................................................... 116 int0ic ................................................................................. 117 int1ic ................................................................................. 117 int3ic ................................................................................. 117 inten ................................................................................. 124 intf .................................................................................... 125 [ k ] kien .................................................................................... 128 kupic ................................................................................. 115 [ l ] lincr ................................................................................. 325 linst .................................................................................. 326 [ o ] ocd ...................................................................................... 83 ofs ....................................................................... 27, 137, 356 [ p ] p1drr .................................................................................. 64 pdi (i = 0, 1, and 3 to 5) ........................................................ 60 pi (i = 0, 1, and 3 to 5) ........................................................... 61 pinsr1 ......................................................................... 62, 247 pinsr2 ................................................................................. 62 pinsr3 ................................................................................. 62 pm0 ....................................................................................... 77 pm1 ....................................................................................... 77 pmr ............................................................... 63, 247, 269, 299 prcr .................................................................................. 109 pur0 ..................................................................................... 64 pur1 ..................................................................................... 64 [ r ] rmad0 ................................................................................ 130 rmad1 ................................................................................ 130 [ s ] s0ric .................................................................................. 115 s0tic .................................................................................. 115 s1ric .................................................................................. 115 s1tic ................................................................................... 115 sar ..................................................................................... 298 sscrh ................................................................................ 262 sscrl ................................................................................. 263 sser ................................................................................... 265 ssmr .................................................................................. 264 ssmr2 ................................................................................ 267 ssrdr ................................................................................ 268 sssr ................................................................................... 266 sstdr ................................................................................ 268 ssuic .................................................................................. 116 [ t ] tra ..................................................................................... 145 tracr ................................................................................ 144 traic .................................................................................. 115 traioc ....................................... 144, 146, 149, 151, 153, 156 tramr ................................................................................ 145 trapre .............................................................................. 145 trbcr ................................................................................ 160 trbic .................................................................................. 115 trbioc ............................................... 161, 163, 167, 170, 175 trbmr ................................................................................ 161 trbocr ............................................................................. 160 trbpr ................................................................................ 162 trbpre .............................................................................. 162 trbsc ................................................................................ 162 trc ..................................................................................... 188 trccr1 ...................................................... 185, 208, 212, 217 trccr2 .............................................................................. 189 trcdf ................................................................................ 190 trcgra ............................................................................. 188 trcgrb ............................................................................. 188 trcgrc ............................................................................. 188 trcgrd ............................................................................. 188 trcic .................................................................................. 116 trcier ............................................................................... 186 trcior0 ............................................................. 192, 201, 206 trcior1 ............................................................. 192, 202, 207 trcmr ................................................................................ 184 trcoer ............................................................................. 191 trcsr ................................................................................ 187 trecr1 ...................................................................... 228, 235 trecr2 ...................................................................... 229, 235 trecsr ...................................................................... 230, 236 trehr ................................................................................ 227 treic .................................................................................. 115 tremin ....................................................................... 226, 234 tresec ...................................................................... 226, 234 trewk ................................................................................ 227 index rev.2.10 sep 26, 2008 page 453 of 453 rej09b0278-0210 r8c/26 group, r8c/27 group index [ u ] u0brg ................................................................................ 244 u0c0 ................................................................................... 245 u0c1 ................................................................................... 246 u0mr .................................................................................. 244 u0rb ................................................................................... 243 u0tb ................................................................................... 243 u1brg ................................................................................ 244 u1c0 ................................................................................... 245 u1c1 ................................................................................... 246 u1mr .................................................................................. 244 u1rb ................................................................................... 243 u1tb ................................................................................... 243 [ v ] vca1 ..................................................................................... 39 vca2 ................................................................... 39, 40, 86, 87 vw0c .................................................................................... 41 vw1c .............................................................................. 42, 43 vw2c .................................................................................... 44 [ w ] wdc .................................................................................... 137 wdtr ................................................................................. 138 wdts .................................................................................. 138 c - 1 revision history r8c/26 group, r8c/27 group hardware manual rev. date description page summary 0.10 jan 30, 2006 ? first edition issued 1.00 nov 08, 2006 all pages ?preliminary? deleted 2 table 1.1 revised 3 table 1.2 revised 4 figure 1.1 revised 5 table 1.3 revised 6 table 1.4 revised 7 figure 1.4 revised 9 table 1.6 revised 15 table 4.1; ? 001ch: ?00h? ?00h, 10000000b? revised ? 000fh: ?000xxxxxb? ?00x11111b? revised ? 0029h: ?high-spee d on-chip oscillator cont rol register 4, fra4, when shipping? added ? 002bh: ?high-speed on -chip oscillator control register 6, fra6, when shipping? added ? 0032h: ?00h, 01000000b? ?00h, 00100000b? revised ? 0038h: ?00001000b, 01001001b? ?0000x000b, 0100x001b? revised ? note3 and 4 revised; note6 added 18 table 4.4; ? 00e0h, 00e1h, 00e5h, 00e8h, 00e9h: ?xxh? ?00h? revised ? 00fdh: ?xx00000000b? ?00h? revised 23 table 5.2 revised 24 figure 5.4 note2 revised 25 5.1.1 (2), 5.1.2 (4) revised 26 figure 5.5, figure 5.6 revised 27 figure 5.7 revised 28 5.3 revised 33 figure 6.5; vca2 register note6 revised 35 figure 6.7 revised 46 figure 7.2 revised 52 figure 7.9 pinsr2 register revised 53 figure 7.10 revised 58 table 7.17 revised 60 table 7.25 revised 64 table 7.35, table 7.36 revised 65 table 7.37, table 7.39 revised 69 table 10.1 note5 revised 70 figure 10.1 revised 71 figure 10.2 revised r8c/26 group, r8c/27 group hard ware manual revision history c - 2 revision history r8c/26 group, r8c/27 group hardware manual 1.00 nov 08, 2006 73 figure 10.4 revised 74 figure 10.5; fra0 register note2 and fra1 register note1 revised 75 figure 10.6; fra2 register revised, registers fra4 and fra6 added 76 figure 10.8 note6 revised 77 figure 10.9 note1 revised 78 10.2.2 revised 80 10.4.3 revised, 10.4.8 added 81 table 10.2 revised 83 10.5.2.2, 10.5.2.3 revised 84 10.5.2.4, table 10.3 revised 85 figure 10.11 added 86 10.5.2.5 added, figure 10.12 revised 88 10.5.3.3 revised, figure 10.13 added 91 10.6.1 revised 92 figure 10.16 revised 93 figure 10.17 revised 94 10.7.1 revised, 10.7.2 added, 10.7.4 foco40m deleted 95 figure 11.1 revised 96 figure 12.1 revised 103 figure 12.5 note3 revised 106 table 12.5 revised 108 figure 12.10 revised 111 figure 12.13 revised 117 table 12.8 revised 121 12.6.7 deleted 122 figure 13.1 revised 123 figure 13.2 revised 126 table 13.3 note2 revised 127 14 revised 129 14.1, figure 14.1 revised 130 figure 14.2 revised 131 figure 14.3 revised 132 table 14.2, figure 14.4 revised 133 14.1.1.1, figure 14.5 added 134 table 14.3 revised 135 figure 14.6 revised 136 table 14.4 revised 137 figure 14.7 revised 138 table 14.5 revised rev. date description page summary c - 3 revision history r8c/26 group, r8c/27 group hardware manual 1.00 nov 08, 2006 139 figure 14.8 revised 140 figure 14.9 revised 141 table 14.6 revised 142 figure 14.10 revised 143 figure 14.11 revised 145 14.2, figure 14.12 revised 146 figure 14.13 revised 147 figure 14.14 revised 148 figure 14.15 revised 149 table 14.7, figure 14.16 revised 150 14.2.1.1 added 151 figure 14.17 added 152 table 14.8 revised 153 figure 14.18 revised 154 figure 14.19 revised 155 table 14.9 revised 156 figure 14.20 revised 158 14.2.3.1 added 159 table 14.10 revised 160 figure 14.22 revised 161 figure 14.23 revised 162 14.2.5 revised 178 figure 14.38 revised 182 figure 14.40 revised 190 figure 14.47 revised 194 figure 14.50 revised 198 table 14.22 revised 199 figure 14.54 revised 203 table 14.24 revised 205 14.4 revised 206 figure 14.59 revised 214 figure 14.69 revised 226 figure 15.4; u0mr to u1mr register revised 228 figure 15.6 revised 229 figure 15.7; pmr register revised 230 table 15.1 note2 revised 232 figure 15.8 revised 235 table 15.4 note1 revised 236 ?txd0? ?txdi? revised rev. date description page summary c - 4 revision history r8c/26 group, r8c/27 group hardware manual 1.00 nov 08, 2006 237 figure 15.11 revised 238 figure 15.12 revised 242 table 16.2 note2 deleted 245 figure 16.3 revised 246 figure 16.4 revised 249 figure 16.7 revised 250 figure 16.8 sstdr register note1 deleted 251 figure 16.9 revised 258 16.2.5.2 revised 259 figure 16.14 note2 deleted 262 16.2.5.4 revised 263 figure 16.17 note2 deleted 265 figure 16.18 revised 266 16.2.6.2 revised 267 figure 16.19 revised 271 16.2.8.1 revised 274 figure 16.23 revised 275 figure 16.24 note1 revised 277 figure 16.26 note3 revised 282 figure 16.31 revised 285 figure 16.32 revised 287 figure 16.33, figure 16.34 revised 289 figure 16.35 revised 290 figure 16.36 revised 301 to 304 figure 16.46 to figure 16.49 figure title revised and figure 16.47 revised 306 to 320 17 ?sync? ?synch? revised 308 figure 17.2 revised 310 figure 17.4 revised 311 figure 17.5 revised 312 figure 17.6 revised 313 17.4.2 (5), figure 17.7 revised 314 figure 17.8 revised 315 figure 17.9 revised 316 figure 17.10 revised 317 figure 17.11 revised 318 17.4.4, figure 17.12 added 319 17.5, table 17.2 revised 321 table 18.1 revised 322 figure 18.1 revised rev. date description page summary c - 5 revision history r8c/26 group, r8c/27 group hardware manual 1.00 nov 08, 2006 324 figure 18.3 revised 325 table 18.2 revised 329 figure 18.6 revised 331 18.3 revised 332 figure 18.10 revised 333 18.6 revised 334 18.7 revised 335 table 19.1 revised 339 figure 19.4 note2 revised 340 table 19.3 revised 342 19.4.2.1 revised 346 figure 19.7 revised 347 figure 19.8 revised 350 19.4.3.1, 19.4.3.2 revised 351 19.4.3.4 revised, figure 19.12 title revised 352 figure 19.13 added 353 figure 19.14 title revised 354 figure 19.15 revised 357 figure 19.16 revised 364 19.7.1.7 deleted 365 table 20.2 revised 366 figure 20.1 title revised 367 table 20.4 revised 368 table 20.5 revised 369 figure 20.2 title revised and table 20.7 note4 added 370 table 20.9, figure 20.3 revised and table 20.10 deleted 371 table 20.10, table 20.11 revised 377 table 20.15 revised 378 table 20.16 revised 379 table 20.17 revised 382 table 20.22 revised 383 table 20.23 revised 387 table 20.29 revised 390 21.1.1 revised, 21.1.2 added, 21.1.4 foco40m deleted 393 21.2.7 deleted 395 21.3.2 revised 401 21.5.1.1 revised 402 21.6 revised 403 21.7 revised rev. date description page summary c - 6 revision history r8c/26 group, r8c/27 group hardware manual 1.00 nov 08, 2006 406 21.8.1.7 deleted 408 22 (2) revised, (5) deleted 409 appendix 1; ?diagrams showing the latest...website.? added 1.10 jan 17, 2007 ? ?j, k version? added 1 1 ?j and k versions are under development...notice.? added 1.1 revised 2 table 1.1 revised 3 table 1.2 revised 4 figure 1.1 note3 added 5 table 1.3 and figure 1.2 revised 6 table 1.4 and figure 1.3 revised 7 figure 1.4 note3 added 8 table 1.5 revised 9 table 1.6 note2 added 13 figure 3.1 revised 14 figure 3.2 revised 15 table 4.1; ?0000h to 003fh? ?0000h to 002fh? revised ? note3 added 16 table 4.2; ?0040h to 007fh? ?0030h to 007fh? revised ? 0032h, 0036h: value after reset is revised ? 0038h: note revised ? notes 2, 5, 6 revised and notes 7, 8 added 18 table 4.4 note2 added 19 table 4.5 note2 added 22 5 ?(for n, d version only)? added table 5.1 note1 added figure 5.1 figure title ?(n, d version)? added 23 figure 5.2 added 25 figure 5.5 revised 27 figures 5.6 and 5.7 revised 28 5.2 revised figure 5.8 revised 29 figure 5.9 added 30 5.3, 5.4 titles ?(n, d version)? added 5.5 added 32 6 ?...voltage monitor 0 reset (for n, d version only), voltage monitor 1 interrupt (for n, d version only)...? revised table 6.1 table title ?(n, d version)? added 33 table 6.2 added figure 6.1 figure title ?(n, d version)? added rev. date description page summary c - 7 revision history r8c/26 group, r8c/27 group hardware manual 1.10 jan 17, 2007 34 figure 6.2 added figure 6.3 figure title ?(for n, d version only)? added 35 figure 6.4 figure title ?(n, d version)? added figure 6.5 added 37 figure 6.7; vca2 register figure title and note6 revised 38 figure 6.8 added 39 figure 6.9 figure title ?(for n, d version only)? added 40 figure 6.10 figure title ?(n, d version)? added 41 figure 6.11 added 42 figure 6.12 note8 revised 44 6.2 title ?(for n, d version only)? added 45 6.3 title ?(n, d version)? added 46 figure 6.14 figure title ?(n, d version)? added 47 6.4 added 50 7 note1 added and table 7.1 note3 revised 56 figure 7.5 revised 62 figure 7.13 ?(for n, d version only)? added 63 table 7.4 note1 revised 73 table 7.35 note1 added and table 7.36 note2 added 78 10 revised and table 10.1 ?(for n, d version only)? added 79 figure 10.1 note1 added 80 figure 10.2 note12 added 81 figure 10.3 note10 added 83 figure 10.5; fra0 register note2 revised 84 figure 10.6; fra2 register note2 added, registers fra4 and fra6 ?for n, d version only? added 85 figure 10.7 ?(for n, d version only)? added, figure 10.8 figure title and note6 revised 86 figure 10.9 added 87 figure 10.10 added 88 figure 10.11 note1 revised 89 10.2.2 revised 90 10.3 title ?(for n, d version only)? added 91 10.4.1, 10.4.2, and 10.4.8 revised 92 table 10.2 note1 added 93 10.5.1.2 and 10.5.1.4 revised 95 table 10.3 revised 96 figure 10.13 revised 97 10.5.2.5 and figure 10.14 revised rev. date description page summary c - 8 revision history r8c/26 group, r8c/27 group hardware manual 1.10 jan 17, 2007 98 table 10.4 note1 added 99 figure 10.15 revised 101 figure 10.17 ?(for n, d version only)? added 103 table 10.6 note1 added 104 figure 10.19 ?(n, d version)? added 105 figure 10.20 added 106 10.7.1, 10.7.2 revised 110 12.1.3.1 revised 12.1.3.3 ?(for n, d version only)? added 111 table 12.1 note2 added 118 table 12.5 note1 added 120 figure 12.10 note1 added 121 figure 12.11 note2 added 127 table 12.6 revised 131 12.6.4 deleted 135 figure 13.2; ofs register revised 140 table 14.1 notes 1, 2 added 141 figure 14.1 note1 added 143 figure 14.3 note2 added 146 table 14.3 note2 added 150 table 14.5 note1 added 153 table 14.6 note2 added 167 table 14.9 note2 added 171 table 14.10 note2 added 213 figure 14.56 revised 217 14.4 ?(for j, k version...)? added 218 14.4.1 title ?(for n, d version only)? added 226 figure 14.69 note1 added 227 table 14.27 note1 added 230 figure 14.74 note2 added 252 15.3 revised 287 figure 16.24 note7 added 317 16.3.8.2, 16.3.8.3 added 333 table 18.1 revised 335 figure 18.2 note4 revised 338 figure 18.4 note4 revised 341 figure 18.6 note4 revised 346 18.7 revised 351 figure 19.4 revised rev. date description page summary c - 9 revision history r8c/26 group, r8c/27 group hardware manual 1.10 jan 17, 2007 353 19.4.1, 19.4.2 revised 361 figure 19.11 revised 364 figure 19.13 revised 368 table 19.6 revised 383 table 20.10 revised 402 to 421 20.2 j, k version added 422 21.1.1, 21.1.2 revised 423 21.2.4 deleted 432 21.4 revised 434 21.5.2.2, 21.5.2.3 added 436 21.7 revised 443 appendix figure 2.1 note2 deleted 1.20 may 18, 2007 ? ?renesas technical update? reflected: tn-16c-a164a/e, tn-16c-a167a/e 2 table 1.1 revised 3 table 1.2 revised 5 table 1.3 revised 6 figure 1.2 revised 7 table 1.4 revised 8 figure 1.3 revised 9 figure 1.4 note4 added 15 figure 3.1 part number revised 16 figure 3.2 part number revised 26 figure 5.4 revised 54 figure 7.1 revised 55 figure 7.2 revised 68 table 7.18 revised 70 table 7.24 revised 82 figure 10.2 note3 revised 85 figure 10.5 fra1 register revised 98 10.5.2.4 revised 104 10.6.1 revised 124 12.2.1 revised 134 figure 12.20 note2 revised 141 14 ?two 16-bit timers? ?a 16-bit timer? revised 147 figure 14.5 revised 158 14.1.6 revised 159 figure 14.12 revised 165 figure 14.17 revised rev. date description page summary c - 10 revision history r8c/26 group, r8c/27 group hardware manual 1.20 may 18, 2007 173 table 14.10 revised 176 to 179 14.2.5.1 to 14.2.5.4 added 203 table 14.18 revised 229 figure 14.69 revised 243 figure 15.4 uimr register note2 deleted 253 table 15.5 note2 added 261 figure 16.2 note4 deleted 262 figure 16.3 note4 deleted 263 figure 16.4 note2 deleted 264 figure 16.5 note1 deleted 265 figure 16.6 note2 revised and note7 deleted 266 figure 16.7 note5 revised 267 figure 16.8 registers sstdr and ssrdr; note1 deleted 288 16.2.8.1 deleted 292 figure 16.24 note6 deleted 293 figure 16.25 note5 deleted 294 figure 16.26 note7 deleted 295 figure 16.27 note3 deleted 296 figure 16.28 note7 deleted 297 figure 16.29 registers sar, icdrt, and icdrr; note1 deleted 321 16.3.8.1 deleted 350 18.7 revised 351 table 19.2 revised 356 table 19.3 revised 358 19.4.2.4 revised 359 19.4.2.15 revised 360 figure 19.5 notes 3 and 5 revised 362 figure 19.7 note5 revised 364 figure 19.9 revised 365 figure 19.11 revised 367 19.4.3.4 revised 368 figure 19.13 revised 370 figure 19.15 revised 387 table 20.10 revised 410 table 20.39 note4 added 412 table 20.42 revised 428 figure 21.1 note2 revised 430 21.3.1 revised 431 to 434 21.3.2.1 to 21.3.2.4 added rev. date description page summary c - 11 revision history r8c/26 group, r8c/27 group hardware manual 1.20 may 18, 2007 440 21.5.1.2 and 21.5.2.1 deleted 442 21.7 revised 450 appendix figure 3.1 note1 revised 1.30 jun 01, 2007 162 figure 14.15 trbpr register note2 revised 176 14.2.5 note revised 328 figure 17.6 revised 329 figure 17.7 ?b0clr bit? revised 331 figure 17.9 revised 433 figure 21.3 revised 2.00 mar 01, 2008 1, 407 1.1, 20.2 ?j and k versions are ...? deleted 5, 7 table 1.3, table 1.4 revised 11 table 1.6 note3 added 15, 16 figure 3.1, figure 3.2; ?expanded area? deleted 17 table 4.1 ?002ch? added 18 table 4.2 ?0036h?; j, k version ?0100x000b? ?0100x001b? 27, 137, 356 figure 5.5, figure 13.2, figure 19.4; ?ofs register? revised 67 table 7.14 revised 70 table 7.26 revised 71 table 7.28 revised 80 figure 10.1 revised 81 figure 10.2 ?set to 0.? ?do not set to 1.? 85 figure 10.6 ?fra7 register? added 90 10.2.2 revised 93 10.4.9 added 95 10.5.1.4 ?... clock ...? ?... on-chip oscillator ...? 114 table 12.2 ?reference? revised 124 12.2.1 ?the int0 pin is shared ...? deleted table 12.6 added 142 table 14.1 ?? fc32? deleted 143 figure 14.1 ?tstart? ?tcstf? 159 14.2 ?the reload register and ...? deleted figure 14.2 ?tstrat? ?tstart? 162 figure 14.15 revised 166 table 14.8 ?(p1_3)? ?? trbo pin select function ...? added 169, 174 table 14.9, table 14.10 ?? trbo pin select function ...? added 170 figure 14.20 ?... when write, ...? ?... if necessary, ...? 189 figure 14.33 revised 192 figure 14.36 trcior0: b3 revised, note4 added rev. date description page summary c - 12 revision history r8c/26 group, r8c/27 group hardware manual 2.00 mar 01, 2008 199 14.3.4 ?the trcgra register can also select foco128 signal ...? added table 14.16 revised 200 figure 14.42 revised 201 figure 14.43 b3 revised, note3 added 206 figure 14.47 b3 revised 209 figure 14.50 ?? the cclr bit ... 0 ...? ? c - 13 revision history r8c/26 group, r8c/27 group hardware manual 2.10 sep 26, 2008 412 table 20.41 revised figure 20.22 revised rev. date description page summary r8c/26 group, r8c/27 group hardware manual publication date: rev.0.10 jan 30, 2006 rev.2.10 sep 26, 2008 published by: sales strategic planning div. renesas technology corp. ? 2008. renesas technology corp., all rights reserved. printed in japan r8c/26 group, r8c/27 group rej09b0278-0210 hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan |
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